From f55d28ea992dcc077452ff0cf7442597bd450f3c Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 19 Mar 2015 14:26:51 +0100 Subject: [PATCH] trbnet fifos are generated for ecp5 --- lattice/ecp5/FIFO/FIFO.sbx | 2011 ++ .../ecp5/FIFO/archv/FIFO_36x128_OutReg.zip | Bin 0 -> 52528 bytes .../archv/FIFO_DC_36x128_DynThr_OutReg.zip | Bin 0 -> 78579 bytes .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst | 3 + .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn | 3014 +++ .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc | 2 + .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc | 50 + .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd | Bin 0 -> 124667 bytes .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo | Bin 0 -> 49806 bytes .../FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd | 1053 ++ .../fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd | 1 + .../fifo_18x256_oreg/fifo_18x256_oreg.cst | 3 + .../fifo_18x256_oreg/fifo_18x256_oreg.edn | 2679 +++ .../fifo_18x256_oreg/fifo_18x256_oreg.fdc | 2 + .../fifo_18x256_oreg/fifo_18x256_oreg.lpc | 50 + .../fifo_18x256_oreg/fifo_18x256_oreg.ngd | Bin 0 -> 110186 bytes .../fifo_18x256_oreg/fifo_18x256_oreg.ngo | Bin 0 -> 44033 bytes .../fifo_18x256_oreg/fifo_18x256_oreg.vhd | 915 + .../fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd | 1 + .../fifo_18x512_oreg/fifo_18x512_oreg.cst | 3 + .../fifo_18x512_oreg/fifo_18x512_oreg.edn | 2742 +++ .../fifo_18x512_oreg/fifo_18x512_oreg.fdc | 2 + .../fifo_18x512_oreg/fifo_18x512_oreg.lpc | 50 + .../fifo_18x512_oreg/fifo_18x512_oreg.ngd | Bin 0 -> 113968 bytes .../fifo_18x512_oreg/fifo_18x512_oreg.ngo | Bin 0 -> 45226 bytes .../fifo_18x512_oreg/fifo_18x512_oreg.vhd | 949 + .../fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd | 1 + .../fifo_36x16k_oreg/fifo_36x16k_oreg.cst | 3 + .../fifo_36x16k_oreg/fifo_36x16k_oreg.edn | 8720 +++++++++ .../fifo_36x16k_oreg/fifo_36x16k_oreg.fdc | 2 + .../fifo_36x16k_oreg/fifo_36x16k_oreg.lpc | 50 + .../fifo_36x16k_oreg/fifo_36x16k_oreg.ngd | Bin 0 -> 366496 bytes .../fifo_36x16k_oreg/fifo_36x16k_oreg.ngo | Bin 0 -> 167525 bytes .../fifo_36x16k_oreg/fifo_36x16k_oreg.vhd | 3166 ++++ .../fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd | 1 + .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst | 3 + .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn | 3251 ++++ .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc | 2 + .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc | 50 + .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd | Bin 0 -> 146570 bytes .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo | Bin 0 -> 56088 bytes .../FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd | 1095 ++ .../fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd | 1 + .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst | 3 + .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn | 3557 ++++ .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc | 2 + .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc | 50 + .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd | Bin 0 -> 155884 bytes .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo | Bin 0 -> 62646 bytes .../FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd | 1218 ++ .../fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd | 1 + .../fifo_36x32k_oreg/fifo_36x32k_oreg.cst | 3 + .../fifo_36x32k_oreg/fifo_36x32k_oreg.edn | 15178 ++++++++++++++++ .../fifo_36x32k_oreg/fifo_36x32k_oreg.fdc | 2 + .../fifo_36x32k_oreg/fifo_36x32k_oreg.lpc | 50 + .../fifo_36x32k_oreg/fifo_36x32k_oreg.ngd | Bin 0 -> 663218 bytes .../fifo_36x32k_oreg/fifo_36x32k_oreg.ngo | Bin 0 -> 297027 bytes .../fifo_36x32k_oreg/fifo_36x32k_oreg.vhd | 5813 ++++++ .../fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd | 1 + .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst | 3 + .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn | 4721 +++++ .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc | 2 + .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc | 50 + .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd | Bin 0 -> 193125 bytes .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo | Bin 0 -> 85455 bytes .../FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd | 1721 ++ .../fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd | 1 + .../fifo_36x512_oreg/fifo_36x512_oreg.cst | 3 + .../fifo_36x512_oreg/fifo_36x512_oreg.edn | 2868 +++ .../fifo_36x512_oreg/fifo_36x512_oreg.fdc | 2 + .../fifo_36x512_oreg/fifo_36x512_oreg.lpc | 50 + .../fifo_36x512_oreg/fifo_36x512_oreg.ngd | Bin 0 -> 133300 bytes .../fifo_36x512_oreg/fifo_36x512_oreg.ngo | Bin 0 -> 49006 bytes .../fifo_36x512_oreg/fifo_36x512_oreg.vhd | 949 + .../fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd | 1 + .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst | 3 + .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn | 6047 ++++++ .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc | 2 + .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc | 50 + .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd | Bin 0 -> 244357 bytes .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo | Bin 0 -> 112810 bytes .../FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd | 2200 +++ .../fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd | 1 + lattice/ecp5/PLL/PLL.sbx | 661 + lattice/ecp5/PLL/archv/pll_in200_out100.zip | Bin 0 -> 136545 bytes lattice/ecp5/PLL/pll_in200_out100/licbug.txt | 16 + .../PLL/pll_in200_out100/pll_in200_out100.cmd | 18 + .../PLL/pll_in200_out100/pll_in200_out100.edn | 234 + .../PLL/pll_in200_out100/pll_in200_out100.fdc | 2 + .../PLL/pll_in200_out100/pll_in200_out100.lpc | 93 + .../PLL/pll_in200_out100/pll_in200_out100.ngd | Bin 0 -> 5580 bytes .../PLL/pll_in200_out100/pll_in200_out100.ngo | Bin 0 -> 3532 bytes .../PLL/pll_in200_out100/pll_in200_out100.vhd | 86 + .../pll_in200_out100/pll_in200_out100_ngd.asd | 1 + .../pll_in200_out100/syn_results/.recordref | 0 .../syn_results/dm/layer0.xdm | 177 + .../pll_in200_out100/syn_results/licbug.txt | 1 + .../syn_results/pll_in200_out100.areasrr | 16 + .../syn_results/pll_in200_out100.edn | 236 + .../syn_results/pll_in200_out100.fse | 0 .../syn_results/pll_in200_out100.htm | 9 + .../syn_results/pll_in200_out100.prj | 46 + .../syn_results/pll_in200_out100.srd | Bin 0 -> 5517 bytes .../syn_results/pll_in200_out100.srf | 373 + .../syn_results/pll_in200_out100.srm | Bin 0 -> 6222 bytes .../syn_results/pll_in200_out100.srr | 373 + .../syn_results/pll_in200_out100.srs | Bin 0 -> 5590 bytes .../syn_results/pll_in200_out100.vhm | 139 + .../syn_results/pll_in200_out100.vm | 120 + .../syn_results/pll_in200_out100_synplify.lpf | 20 + .../syn_results/run_options.txt | 67 + .../syn_results/scratchproject.prs | 65 + .../syn_results/synlog/map.srr.rptmap | 1 + .../synlog/pll_in200_out100_compiler.srr | 47 + .../pll_in200_out100_compiler.srr.rptmap | 1 + .../synlog/pll_in200_out100_fpga_mapper.srr | 257 + .../pll_in200_out100_fpga_mapper.srr_Min | 116 + .../synlog/pll_in200_out100_fpga_mapper.szr | Bin 0 -> 6303 bytes .../synlog/pll_in200_out100_multi_srs_gen.srr | 9 + .../synlog/pll_in200_out100_premap.srr | 49 + .../synlog/pll_in200_out100_premap.szr | Bin 0 -> 2174 bytes .../syn_results/synlog/pre_map.srr.rptmap | 1 + .../pll_in200_out100_compiler_notes.txt | 11 + .../pll_in200_out100_compiler_runstatus.xml | 41 + .../pll_in200_out100_compiler_warnings.txt | 2 + ...l_in200_out100_fpga_mapper_area_report.xml | 26 + .../pll_in200_out100_fpga_mapper_errors.txt | 0 .../pll_in200_out100_fpga_mapper_notes.txt | 11 + ...ll_in200_out100_fpga_mapper_opt_report.xml | 14 + ...pll_in200_out100_fpga_mapper_runstatus.xml | 46 + ...in200_out100_fpga_mapper_timing_report.xml | 23 + .../pll_in200_out100_fpga_mapper_warnings.txt | 1 + .../report/pll_in200_out100_premap_errors.txt | 0 .../report/pll_in200_out100_premap_notes.txt | 2 + .../pll_in200_out100_premap_runstatus.xml | 46 + .../pll_in200_out100_premap_warnings.txt | 0 .../syn_results/syntmp/closed.png | Bin 0 -> 3672 bytes .../syn_results/syntmp/namekey.txt | 0 .../syn_results/syntmp/open.png | Bin 0 -> 452 bytes .../syn_results/syntmp/pll_in200_out100.plg | 14 + .../syntmp/pll_in200_out100_srr.htm | 378 + .../syntmp/pll_in200_out100_toc.htm | 44 + .../syn_results/syntmp/run_option.xml | 22 + .../syn_results/syntmp/statusReport.html | 110 + .../syn_results/synwork/.cckTransfer | Bin 0 -> 39 bytes .../syn_results/synwork/_mh_info | 1 + .../syn_results/synwork/layer0.fdep | 28 + .../syn_results/synwork/layer0.fdeporig | 24 + .../syn_results/synwork/layer0.srs | Bin 0 -> 6473 bytes .../syn_results/synwork/layer0.tlg | 11 + .../synwork/pll_in200_out100_comp.fdep | 21 + .../synwork/pll_in200_out100_comp.srs | Bin 0 -> 5358 bytes .../synwork/pll_in200_out100_m.srm | Bin 0 -> 6222 bytes .../synwork/pll_in200_out100_mult.srs | Bin 0 -> 5590 bytes .../pll_in200_out100_mult_srs/skeleton.srs | Bin 0 -> 574 bytes .../synwork/pll_in200_out100_prem.fse | 0 .../synwork/pll_in200_out100_prem.srd | Bin 0 -> 4925 bytes .../synwork/pll_in200_out100_s.srm | Bin 0 -> 6097 bytes .../synwork/pll_in200_out100_s.srs | Bin 0 -> 5358 bytes 159 files changed, 78537 insertions(+) create mode 100644 lattice/ecp5/FIFO/FIFO.sbx create mode 100644 lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip create mode 100644 lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip create mode 100644 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create mode 100644 lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.fse create mode 100644 lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_prem.srd create mode 100644 lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srm create mode 100644 lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_s.srs diff --git a/lattice/ecp5/FIFO/FIFO.sbx b/lattice/ecp5/FIFO/FIFO.sbx new file mode 100644 index 0000000..beca0a3 --- /dev/null +++ b/lattice/ecp5/FIFO/FIFO.sbx @@ -0,0 +1,2011 @@ + + + + LATTICE + LOCAL + FIFO + 1.0 + + + Diamond_Synthesis + synthesis + + + Diamond_Simulation + simulation + + + + + + + + FIFO_36x128_OutReg_Clock + FIFO_36x128_OutReg_Clock + + in + + + + FIFO_36x128_OutReg.Clock + + + + + FIFO_36x128_OutReg_Empty + FIFO_36x128_OutReg_Empty + + out + + + + FIFO_36x128_OutReg.Empty + + + + + FIFO_36x128_OutReg_Full + FIFO_36x128_OutReg_Full + + out + + + + FIFO_36x128_OutReg.Full + + + + + FIFO_36x128_OutReg_RdEn + FIFO_36x128_OutReg_RdEn + + in + + + + FIFO_36x128_OutReg.RdEn + + + + + FIFO_36x128_OutReg_Reset + FIFO_36x128_OutReg_Reset + + in + + + + FIFO_36x128_OutReg.Reset + + + + + FIFO_36x128_OutReg_WrEn + FIFO_36x128_OutReg_WrEn + + in + + + + FIFO_36x128_OutReg.WrEn + + + + + FIFO_DC_36x128_DynThr_OutReg_AlmostFull + FIFO_DC_36x128_DynThr_OutReg_AlmostFull + + out + + + + FIFO_DC_36x128_DynThr_OutReg.AlmostFull + + + + + FIFO_DC_36x128_DynThr_OutReg_Empty + FIFO_DC_36x128_DynThr_OutReg_Empty + + out + + + + FIFO_DC_36x128_DynThr_OutReg.Empty + + + + + FIFO_DC_36x128_DynThr_OutReg_Full + FIFO_DC_36x128_DynThr_OutReg_Full + + out + + + + FIFO_DC_36x128_DynThr_OutReg.Full + + + + + FIFO_DC_36x128_DynThr_OutReg_RPReset + FIFO_DC_36x128_DynThr_OutReg_RPReset + + in + + + + FIFO_DC_36x128_DynThr_OutReg.RPReset + + + + + FIFO_DC_36x128_DynThr_OutReg_RdClock + FIFO_DC_36x128_DynThr_OutReg_RdClock + + in + + + + FIFO_DC_36x128_DynThr_OutReg.RdClock + + + + + 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z+O3_b=kQ`2V(NL?rJbo4uxpN#y-2&Wv+Pf_Gdok8vFDuBZlN97S@sg`#?I8sv=cj1 zuh1^+O#PX5U}x%8+I^j=*J$T;re3FA*O_{Qc3fwwM7yms^(O7K&eU79%Q{nkp&izl gdRt(3b*A2-ozP)>Su$%h-0;4C~qyPW_ literal 0 HcmV?d00001 diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd new file mode 100644 index 0000000..51a1398 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd @@ -0,0 +1,1053 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc + +-- Wed Mar 18 14:32:11 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_18x1k_oreg is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(9 downto 0); + Q: out std_logic_vector(17 downto 0); + WCNT: out std_logic_vector(10 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_18x1k_oreg; + +architecture Structure of fifo_18x1k_oreg is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal rptr_10: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal co5_1: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal co5_2: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal rptr_6: std_logic; + signal rptr_5: std_logic; + signal wcount_6: std_logic; + signal wcount_5: std_logic; + signal co2_5: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal rptr_8: std_logic; + signal rptr_7: std_logic; + signal wcount_8: std_logic; + signal wcount_7: std_logic; + signal co3_5: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal rptr_9: std_logic; + signal wcnt_sub_msb: std_logic; + signal wcount_9: std_logic; + signal co4_5: std_logic; + signal co5_3d: std_logic; + signal co5_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_6: std_logic; + signal wcnt_reg_10: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x1k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, + ADB10=>rptr_6, ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, + ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), + DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), + DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), + DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), + DOB0=>Q(0)); + + FF_68: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_67: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_66: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_65: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_64: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_63: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_62: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_61: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_60: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_59: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_58: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_57: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_56: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_55: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_54: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_53: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_52: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_51: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_50: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_49: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_48: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_47: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_46: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_45: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_44: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_43: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_42: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_41: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_40: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_39: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_38: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_37: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_36: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_35: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_34: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_33: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_32: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_31: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_30: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_29: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_28: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_27: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_26: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_25: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_24: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_23: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_22: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_21: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_20: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_19: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_18: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_17: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_16: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_15: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_14: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_13: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_12: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>open, COUT=>co5); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>open, + COUT=>co5_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>open, + COUT=>co5_2); + + precin_inst234: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcnt_sub_msb, B0=>rptr_9, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, + COUT=>co5_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>co5_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst new file mode 100644 index 0000000..4b60fa4 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:42:54 + diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn new file mode 100644 index 0000000..dbbee06 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn @@ -0,0 +1,2679 @@ +(edif fifo_18x256_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 42 55) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + 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(portRef (member Data 12)) + (portRef DIA5 (instanceRef pdp_ram_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 13)) + (portRef DIA4 (instanceRef pdp_ram_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 14)) + (portRef DIA3 (instanceRef pdp_ram_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 15)) + (portRef DIA2 (instanceRef pdp_ram_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 16)) + (portRef DIA1 (instanceRef pdp_ram_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 17)) + (portRef DIA0 (instanceRef pdp_ram_0_0_0)))))))) + (design fifo_18x256_oreg + (cellRef fifo_18x256_oreg + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc new file mode 100644 index 0000000..a889eae --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_18x256_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:42:54 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=256 +Width=18 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 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/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc + +-- Wed Mar 18 14:42:55 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_18x256_oreg is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(7 downto 0); + Q: out std_logic_vector(17 downto 0); + WCNT: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_18x256_oreg; + +architecture Structure of fifo_18x256_oreg is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal rptr_8: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal co4: std_logic; + signal co3: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal co4_1: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal co4_2: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal rptr_6: std_logic; + signal rptr_5: std_logic; + signal wcount_6: std_logic; + signal wcount_5: std_logic; + signal co2_5: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal rptr_7: std_logic; + signal wcnt_sub_msb: std_logic; + signal wcount_7: std_logic; + signal co3_5: std_logic; + signal co4_3d: std_logic; + signal co4_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal wcnt_reg_8: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x256_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_8, B=>rptr_8, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo, + ADA11=>wptr_7, ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, + ADA7=>wptr_3, ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, + ADA3=>scuba_vlo, ADA2=>scuba_vlo, ADA1=>scuba_vhi, + ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, + WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>scuba_vlo, + CSA0=>scuba_vlo, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>scuba_vlo, + ADB12=>scuba_vlo, ADB11=>rptr_7, ADB10=>rptr_6, ADB9=>rptr_5, + ADB8=>rptr_4, ADB7=>rptr_3, ADB6=>rptr_2, ADB5=>rptr_1, + ADB4=>rptr_0, ADB3=>scuba_vlo, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), + DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), + DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), + DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), + DOB0=>Q(0)); + + FF_56: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_55: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_54: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_53: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_52: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_51: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_50: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_49: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_48: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_47: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_46: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_45: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_44: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_43: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_42: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_41: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_40: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_39: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_38: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_37: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_36: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_35: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_34: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_33: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_32: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_31: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_30: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_29: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_28: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_27: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_26: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_25: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_24: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_23: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_22: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_21: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_20: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_19: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_18: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_17: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_16: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_15: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_14: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_13: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_12: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_11: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_10: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>open, COUT=>co4); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>open, + COUT=>co4_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>open, + COUT=>co4_2); + + precin_inst207: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcnt_sub_msb, B0=>rptr_7, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, + COUT=>co4_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>co4_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst new file mode 100644 index 0000000..d7afd32 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:43:13 + diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn new file mode 100644 index 0000000..d8b4bab --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn @@ -0,0 +1,2742 @@ +(edif fifo_18x512_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 43 18) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI35 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI0 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port CER + (direction INPUT)) + (port OCER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO35 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO0 + (direction OUTPUT))))) + (cell fifo_18x512_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(17:0)") 18) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(8:0)") 9) + (direction INPUT)) + (port (array (rename Q "Q(17:0)") 18) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(9:0)") 10) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_18x512_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b001")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE + (string "OUTREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string "36"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef 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Configuration + diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc new file mode 100644 index 0000000..a92d8d4 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_18x512_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:43:13 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=18 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd new file mode 100644 index 0000000000000000000000000000000000000000..ecd1e9a799e70c1158261bf43a5959a0c06fd15e GIT binary patch literal 113968 zcmbq+2bdI9_WdhRFk-7~Mr{=k6IKsV*U&^AB(yLD1)OHcBG3*&7ZF=UQA}+D%&o3D z^_q9a)z+z=R@cxlVAgHpx~^jTQ!%do&wck+)$5ub|MPv+eysJ*yYIex&v~y>SG~y= zilr(Q>8td%y=oX>W6zp7XXb+1$bhr^MyhHT)X$iu)N{v^MTdn``zCCAo>GlnLS#69 z*7Ul?bIzE4bU3_ZM*YG$3+9K1%$YiG!Tjmrp8fh9Q8#DNA>rP=`t-7Uk>iG=qSRJdX~YX*)vVJQA@@QG+KJwz>}!f()Uvw@EvI%aJ3=uxn~K4n;IH-kqG z0giAxTh#ryZIhcj>c~L>b`T%JM%DC?RKYRW=%_=|G{NarLpJ}aRL9d)!|w^|VA!zQ z-bb-pu-Ka3hB+lNtFN85sJ^y03}@@|Szh@R?dGg$^B2`tp}N*DLLLoG;1<&sEEb!Q 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zY$SD&q-!K~v7~AwwOrCPl3F1t8cD5`^o*pCw(!{)2|VOxT1J*tl9G|sYDvdPYK^2~ zBz1|TVI;LyQZSObRMIb!x=d0plDb^dE|R)JQZACZQZd~k%Tlpfk<@jPR*}><6;mp*T#pw)BSPIEsT4_mOVTKkx=~UnlDbLKCz85ZQYVtS zMbajcS|=$JN!=>x5=q@AsS-)uE@=`;-61IwN!=;w5lJB#;8@esZ%bN4Vs}YOL{fK4 zIz&?6kyMDJzKbWXruX+q3PfV}s=|%{33Z>OJ|uO&q&+0{JxO^;YQ3a8B=vx#IwbXd zNpnbQgQPel^#e(7NGd6*4M{yHX$?tjl$3^~ekkb-No~Sbsu&6Nkfbpr^{}KcB(+)6 z7n0f{sS8PMm9&MVwn@rDQjbWwLQ;=PszOqaNt!}Zk4uU|QcozRCuB)UYC=*!lC*@R zwo6JvQtgtCkW^Yy5t7PC8bVT8NkK@eL(&hD>Xg)jq;isWkW^k$4w5QJxSvNdkkoUM zK9JN7NgYV)c}W{c>IF#|Nb2X3E|AnOBvl}(UrL%lQadF@AgLE6Js>G0{Cm_OpWrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>scuba_vlo, DI34=>scuba_vlo, DI33=>scuba_vlo, + DI32=>scuba_vlo, DI31=>scuba_vlo, DI30=>scuba_vlo, + DI29=>scuba_vlo, DI28=>scuba_vlo, DI27=>scuba_vlo, + DI26=>scuba_vlo, DI25=>scuba_vlo, DI24=>scuba_vlo, + DI23=>scuba_vlo, DI22=>scuba_vlo, DI21=>scuba_vlo, + DI20=>scuba_vlo, DI19=>scuba_vlo, DI18=>scuba_vlo, + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>wptr_8, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5, + ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1, + ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>rptr_8, + ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4, + ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, + ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, + ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi, + OCER=>scuba_vhi, CLKR=>Clock, CSR2=>scuba_vlo, + CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17), + DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), + DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), + DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), + DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>open, + DO16=>open, DO15=>open, DO14=>open, DO13=>open, DO12=>open, + DO11=>open, DO10=>open, DO9=>open, DO8=>open, DO7=>open, + DO6=>open, DO5=>open, DO4=>open, DO3=>open, DO2=>open, + DO1=>open, DO0=>open); + + FF_62: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_61: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_60: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_59: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_58: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_57: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_56: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_55: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_54: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_53: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_52: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_51: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_50: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_49: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_48: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_47: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_46: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_45: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_44: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_43: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_42: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_41: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_40: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_39: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_38: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_37: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_36: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_35: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_34: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_33: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_32: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_31: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_30: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_29: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_28: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_27: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_26: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_25: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_24: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_23: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_22: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_21: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_20: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_19: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_18: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_17: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_16: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_15: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_14: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_13: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_12: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_11: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_2); + + precin_inst218: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_3); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>wcnt_sub_9, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst new file mode 100644 index 0000000..0fafcfe --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:42:06 + diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn new file mode 100644 index 0000000..f9adae0 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn @@ -0,0 +1,8720 @@ +(edif fifo_36x16k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 42 8) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell MUX81 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port D2 + (direction INPUT)) + (port D3 + (direction INPUT)) + (port D4 + (direction INPUT)) + (port D5 + (direction INPUT)) + (port D6 + (direction INPUT)) + (port D7 + (direction INPUT)) + (port SD1 + (direction INPUT)) + (port SD2 + (direction INPUT)) + (port SD3 + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell fifo_36x16k_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(13:0)") 14) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(14:0)") 15) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_31 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_1_30 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_2_29 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_3_28 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_0_27 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_1_26 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_2_25 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_3_24 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_0_23 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_1_22 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_2_21 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_3_20 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_0_19 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_1_18 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_2_17 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_3_16 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_0_15 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b100")) + (property CSDECODE_A + (string "0b100")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_1_14 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b100")) + (property CSDECODE_A + (string "0b100")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_2_13 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b100")) + (property CSDECODE_A + (string "0b100")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_3_12 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b100")) + (property CSDECODE_A + (string "0b100")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_0_11 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b101")) + (property CSDECODE_A + (string "0b101")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_1_10 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b101")) + (property CSDECODE_A + (string "0b101")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_2_9 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b101")) + (property CSDECODE_A + (string "0b101")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_3_8 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b101")) + (property CSDECODE_A + (string "0b101")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_0_7 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b110")) + (property CSDECODE_A + (string "0b110")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_1_6 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b110")) + (property CSDECODE_A + (string "0b110")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_2_5 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b110")) + (property CSDECODE_A + (string "0b110")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_3_4 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b110")) + (property CSDECODE_A + (string "0b110")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_0_3 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b111")) + (property CSDECODE_A + (string "0b111")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_1_2 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b111")) + (property CSDECODE_A + (string "0b111")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_2_1 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b111")) + (property CSDECODE_A + (string "0b111")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_3_0 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x16k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b111")) + (property CSDECODE_A + (string "0b111")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_98 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_97 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_96 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_95 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_94 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_93 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_92 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_91 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_90 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_89 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_88 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_87 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_86 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_85 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_84 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_83 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_82 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_81 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_80 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_79 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_78 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_77 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_76 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_75 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_74 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_73 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_72 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_71 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_70 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_69 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_4 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_3 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_2 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance bdcnt_bctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance bdcnt_bctr_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_ci_a + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance e_cmp_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance a0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance g_cmp_ci_a + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance g_cmp_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance a1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_0 + (viewRef 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(portRef DIB11 (instanceRef pdp_ram_0_1_30)) + (portRef DIA11 (instanceRef pdp_ram_0_1_30)) + (portRef DIB10 (instanceRef pdp_ram_0_1_30)) + (portRef DIA10 (instanceRef pdp_ram_0_1_30)) + (portRef DIB9 (instanceRef pdp_ram_0_1_30)) + (portRef DIA9 (instanceRef pdp_ram_0_1_30)) + (portRef DIB8 (instanceRef pdp_ram_0_1_30)) + (portRef DIB7 (instanceRef pdp_ram_0_1_30)) + (portRef DIB6 (instanceRef pdp_ram_0_1_30)) + (portRef DIB5 (instanceRef pdp_ram_0_1_30)) + (portRef DIB4 (instanceRef pdp_ram_0_1_30)) + (portRef DIB3 (instanceRef pdp_ram_0_1_30)) + (portRef DIB2 (instanceRef pdp_ram_0_1_30)) + (portRef DIB1 (instanceRef pdp_ram_0_1_30)) + (portRef DIB0 (instanceRef pdp_ram_0_1_30)) + (portRef WEB (instanceRef pdp_ram_0_2_29)) + (portRef ADB2 (instanceRef pdp_ram_0_2_29)) + (portRef ADA2 (instanceRef pdp_ram_0_2_29)) + (portRef ADB1 (instanceRef pdp_ram_0_2_29)) + (portRef ADA1 (instanceRef pdp_ram_0_2_29)) + (portRef ADB0 (instanceRef pdp_ram_0_2_29)) + (portRef ADA0 (instanceRef pdp_ram_0_2_29)) + (portRef DIB17 (instanceRef pdp_ram_0_2_29)) + (portRef DIA17 (instanceRef pdp_ram_0_2_29)) + (portRef DIB16 (instanceRef pdp_ram_0_2_29)) + (portRef DIA16 (instanceRef pdp_ram_0_2_29)) + (portRef DIB15 (instanceRef pdp_ram_0_2_29)) + (portRef DIA15 (instanceRef pdp_ram_0_2_29)) + (portRef DIB14 (instanceRef pdp_ram_0_2_29)) + (portRef DIA14 (instanceRef pdp_ram_0_2_29)) + (portRef DIB13 (instanceRef pdp_ram_0_2_29)) + (portRef DIA13 (instanceRef pdp_ram_0_2_29)) + (portRef DIB12 (instanceRef pdp_ram_0_2_29)) + (portRef DIA12 (instanceRef pdp_ram_0_2_29)) + (portRef DIB11 (instanceRef pdp_ram_0_2_29)) + (portRef DIA11 (instanceRef pdp_ram_0_2_29)) + (portRef DIB10 (instanceRef pdp_ram_0_2_29)) + (portRef DIA10 (instanceRef pdp_ram_0_2_29)) + (portRef DIB9 (instanceRef pdp_ram_0_2_29)) + (portRef DIA9 (instanceRef pdp_ram_0_2_29)) + (portRef DIB8 (instanceRef pdp_ram_0_2_29)) + (portRef DIB7 (instanceRef pdp_ram_0_2_29)) + (portRef DIB6 (instanceRef pdp_ram_0_2_29)) + (portRef DIB5 (instanceRef pdp_ram_0_2_29)) + (portRef DIB4 (instanceRef pdp_ram_0_2_29)) + (portRef DIB3 (instanceRef pdp_ram_0_2_29)) + (portRef DIB2 (instanceRef pdp_ram_0_2_29)) + (portRef DIB1 (instanceRef pdp_ram_0_2_29)) + (portRef DIB0 (instanceRef pdp_ram_0_2_29)) + (portRef WEB (instanceRef pdp_ram_0_3_28)) + (portRef ADB2 (instanceRef pdp_ram_0_3_28)) + (portRef ADA2 (instanceRef pdp_ram_0_3_28)) + (portRef ADB1 (instanceRef pdp_ram_0_3_28)) + (portRef ADA1 (instanceRef pdp_ram_0_3_28)) + (portRef ADB0 (instanceRef pdp_ram_0_3_28)) + (portRef ADA0 (instanceRef pdp_ram_0_3_28)) + (portRef DIB17 (instanceRef pdp_ram_0_3_28)) + (portRef DIA17 (instanceRef pdp_ram_0_3_28)) + (portRef DIB16 (instanceRef pdp_ram_0_3_28)) + (portRef DIA16 (instanceRef pdp_ram_0_3_28)) + (portRef DIB15 (instanceRef pdp_ram_0_3_28)) + (portRef DIA15 (instanceRef pdp_ram_0_3_28)) + (portRef DIB14 (instanceRef pdp_ram_0_3_28)) + (portRef DIA14 (instanceRef pdp_ram_0_3_28)) + (portRef DIB13 (instanceRef pdp_ram_0_3_28)) + (portRef DIA13 (instanceRef pdp_ram_0_3_28)) + (portRef DIB12 (instanceRef pdp_ram_0_3_28)) + (portRef DIA12 (instanceRef pdp_ram_0_3_28)) + (portRef DIB11 (instanceRef pdp_ram_0_3_28)) + (portRef DIA11 (instanceRef pdp_ram_0_3_28)) + (portRef DIB10 (instanceRef pdp_ram_0_3_28)) + (portRef DIA10 (instanceRef pdp_ram_0_3_28)) + (portRef DIB9 (instanceRef pdp_ram_0_3_28)) + (portRef DIA9 (instanceRef pdp_ram_0_3_28)) + (portRef DIB8 (instanceRef pdp_ram_0_3_28)) + (portRef DIB7 (instanceRef pdp_ram_0_3_28)) + (portRef DIB6 (instanceRef pdp_ram_0_3_28)) + (portRef DIB5 (instanceRef pdp_ram_0_3_28)) + (portRef DIB4 (instanceRef pdp_ram_0_3_28)) + (portRef DIB3 (instanceRef pdp_ram_0_3_28)) + (portRef DIB2 (instanceRef pdp_ram_0_3_28)) + (portRef DIB1 (instanceRef pdp_ram_0_3_28)) + (portRef DIB0 (instanceRef pdp_ram_0_3_28)) + (portRef WEB (instanceRef pdp_ram_1_0_27)) + (portRef ADB2 (instanceRef pdp_ram_1_0_27)) + (portRef ADA2 (instanceRef pdp_ram_1_0_27)) + (portRef ADB1 (instanceRef pdp_ram_1_0_27)) + (portRef ADA1 (instanceRef pdp_ram_1_0_27)) + (portRef ADB0 (instanceRef pdp_ram_1_0_27)) + (portRef ADA0 (instanceRef pdp_ram_1_0_27)) + (portRef DIB17 (instanceRef pdp_ram_1_0_27)) + (portRef DIA17 (instanceRef pdp_ram_1_0_27)) + (portRef DIB16 (instanceRef pdp_ram_1_0_27)) + (portRef DIA16 (instanceRef pdp_ram_1_0_27)) + (portRef DIB15 (instanceRef pdp_ram_1_0_27)) + (portRef DIA15 (instanceRef pdp_ram_1_0_27)) + (portRef DIB14 (instanceRef pdp_ram_1_0_27)) + (portRef DIA14 (instanceRef pdp_ram_1_0_27)) + (portRef DIB13 (instanceRef pdp_ram_1_0_27)) + (portRef DIA13 (instanceRef pdp_ram_1_0_27)) + (portRef DIB12 (instanceRef pdp_ram_1_0_27)) + (portRef DIA12 (instanceRef pdp_ram_1_0_27)) + (portRef DIB11 (instanceRef pdp_ram_1_0_27)) + (portRef DIA11 (instanceRef pdp_ram_1_0_27)) + (portRef DIB10 (instanceRef pdp_ram_1_0_27)) + (portRef DIA10 (instanceRef pdp_ram_1_0_27)) + (portRef DIB9 (instanceRef pdp_ram_1_0_27)) + (portRef DIA9 (instanceRef pdp_ram_1_0_27)) + (portRef DIB8 (instanceRef pdp_ram_1_0_27)) + (portRef DIB7 (instanceRef pdp_ram_1_0_27)) + (portRef DIB6 (instanceRef pdp_ram_1_0_27)) + (portRef DIB5 (instanceRef pdp_ram_1_0_27)) + (portRef DIB4 (instanceRef pdp_ram_1_0_27)) + (portRef DIB3 (instanceRef pdp_ram_1_0_27)) + (portRef DIB2 (instanceRef pdp_ram_1_0_27)) + (portRef DIB1 (instanceRef pdp_ram_1_0_27)) + (portRef DIB0 (instanceRef pdp_ram_1_0_27)) + (portRef WEB (instanceRef pdp_ram_1_1_26)) + (portRef ADB2 (instanceRef pdp_ram_1_1_26)) + (portRef ADA2 (instanceRef pdp_ram_1_1_26)) + (portRef ADB1 (instanceRef pdp_ram_1_1_26)) + (portRef ADA1 (instanceRef pdp_ram_1_1_26)) + (portRef ADB0 (instanceRef pdp_ram_1_1_26)) + (portRef ADA0 (instanceRef pdp_ram_1_1_26)) + (portRef DIB17 (instanceRef pdp_ram_1_1_26)) + (portRef DIA17 (instanceRef pdp_ram_1_1_26)) + (portRef DIB16 (instanceRef pdp_ram_1_1_26)) + (portRef DIA16 (instanceRef pdp_ram_1_1_26)) + (portRef DIB15 (instanceRef pdp_ram_1_1_26)) + (portRef DIA15 (instanceRef pdp_ram_1_1_26)) + (portRef DIB14 (instanceRef pdp_ram_1_1_26)) + (portRef DIA14 (instanceRef pdp_ram_1_1_26)) + (portRef DIB13 (instanceRef pdp_ram_1_1_26)) + (portRef DIA13 (instanceRef pdp_ram_1_1_26)) + (portRef DIB12 (instanceRef pdp_ram_1_1_26)) + (portRef DIA12 (instanceRef pdp_ram_1_1_26)) + (portRef DIB11 (instanceRef pdp_ram_1_1_26)) + (portRef DIA11 (instanceRef pdp_ram_1_1_26)) + (portRef DIB10 (instanceRef pdp_ram_1_1_26)) + (portRef DIA10 (instanceRef pdp_ram_1_1_26)) + (portRef DIB9 (instanceRef pdp_ram_1_1_26)) + (portRef DIA9 (instanceRef pdp_ram_1_1_26)) + (portRef DIB8 (instanceRef pdp_ram_1_1_26)) + (portRef DIB7 (instanceRef pdp_ram_1_1_26)) + (portRef DIB6 (instanceRef pdp_ram_1_1_26)) + (portRef DIB5 (instanceRef pdp_ram_1_1_26)) + (portRef DIB4 (instanceRef pdp_ram_1_1_26)) + (portRef DIB3 (instanceRef pdp_ram_1_1_26)) + (portRef DIB2 (instanceRef pdp_ram_1_1_26)) + (portRef DIB1 (instanceRef pdp_ram_1_1_26)) + (portRef DIB0 (instanceRef pdp_ram_1_1_26)) + (portRef WEB (instanceRef pdp_ram_1_2_25)) + (portRef ADB2 (instanceRef pdp_ram_1_2_25)) + (portRef ADA2 (instanceRef pdp_ram_1_2_25)) + (portRef ADB1 (instanceRef pdp_ram_1_2_25)) + (portRef ADA1 (instanceRef pdp_ram_1_2_25)) + (portRef ADB0 (instanceRef pdp_ram_1_2_25)) + (portRef ADA0 (instanceRef pdp_ram_1_2_25)) + (portRef DIB17 (instanceRef pdp_ram_1_2_25)) + (portRef DIA17 (instanceRef pdp_ram_1_2_25)) + (portRef DIB16 (instanceRef pdp_ram_1_2_25)) + (portRef DIA16 (instanceRef pdp_ram_1_2_25)) + (portRef DIB15 (instanceRef pdp_ram_1_2_25)) + (portRef DIA15 (instanceRef pdp_ram_1_2_25)) + (portRef DIB14 (instanceRef pdp_ram_1_2_25)) + (portRef DIA14 (instanceRef pdp_ram_1_2_25)) + (portRef DIB13 (instanceRef pdp_ram_1_2_25)) + (portRef DIA13 (instanceRef pdp_ram_1_2_25)) + (portRef DIB12 (instanceRef pdp_ram_1_2_25)) + (portRef DIA12 (instanceRef pdp_ram_1_2_25)) + (portRef DIB11 (instanceRef pdp_ram_1_2_25)) + (portRef DIA11 (instanceRef pdp_ram_1_2_25)) + (portRef DIB10 (instanceRef pdp_ram_1_2_25)) + (portRef DIA10 (instanceRef pdp_ram_1_2_25)) + (portRef DIB9 (instanceRef pdp_ram_1_2_25)) + (portRef DIA9 (instanceRef pdp_ram_1_2_25)) + (portRef DIB8 (instanceRef pdp_ram_1_2_25)) + (portRef DIB7 (instanceRef pdp_ram_1_2_25)) + (portRef DIB6 (instanceRef pdp_ram_1_2_25)) + (portRef DIB5 (instanceRef pdp_ram_1_2_25)) + (portRef DIB4 (instanceRef pdp_ram_1_2_25)) + (portRef DIB3 (instanceRef pdp_ram_1_2_25)) + (portRef DIB2 (instanceRef pdp_ram_1_2_25)) + (portRef DIB1 (instanceRef pdp_ram_1_2_25)) + (portRef DIB0 (instanceRef pdp_ram_1_2_25)) + (portRef WEB (instanceRef pdp_ram_1_3_24)) + (portRef ADB2 (instanceRef pdp_ram_1_3_24)) + (portRef ADA2 (instanceRef pdp_ram_1_3_24)) + (portRef ADB1 (instanceRef pdp_ram_1_3_24)) + (portRef ADA1 (instanceRef pdp_ram_1_3_24)) + (portRef ADB0 (instanceRef pdp_ram_1_3_24)) + (portRef ADA0 (instanceRef pdp_ram_1_3_24)) + (portRef DIB17 (instanceRef pdp_ram_1_3_24)) + (portRef DIA17 (instanceRef pdp_ram_1_3_24)) + (portRef DIB16 (instanceRef pdp_ram_1_3_24)) + (portRef DIA16 (instanceRef pdp_ram_1_3_24)) + (portRef DIB15 (instanceRef pdp_ram_1_3_24)) + (portRef DIA15 (instanceRef pdp_ram_1_3_24)) + (portRef DIB14 (instanceRef pdp_ram_1_3_24)) + (portRef DIA14 (instanceRef pdp_ram_1_3_24)) + (portRef DIB13 (instanceRef pdp_ram_1_3_24)) + (portRef DIA13 (instanceRef pdp_ram_1_3_24)) + (portRef DIB12 (instanceRef pdp_ram_1_3_24)) + (portRef DIA12 (instanceRef pdp_ram_1_3_24)) + (portRef DIB11 (instanceRef pdp_ram_1_3_24)) + (portRef DIA11 (instanceRef pdp_ram_1_3_24)) + (portRef DIB10 (instanceRef pdp_ram_1_3_24)) + (portRef DIA10 (instanceRef pdp_ram_1_3_24)) + (portRef DIB9 (instanceRef pdp_ram_1_3_24)) + (portRef DIA9 (instanceRef pdp_ram_1_3_24)) + (portRef DIB8 (instanceRef pdp_ram_1_3_24)) + (portRef DIB7 (instanceRef pdp_ram_1_3_24)) + (portRef DIB6 (instanceRef pdp_ram_1_3_24)) + (portRef DIB5 (instanceRef pdp_ram_1_3_24)) + (portRef DIB4 (instanceRef pdp_ram_1_3_24)) + (portRef DIB3 (instanceRef pdp_ram_1_3_24)) + (portRef DIB2 (instanceRef pdp_ram_1_3_24)) + (portRef DIB1 (instanceRef pdp_ram_1_3_24)) + (portRef DIB0 (instanceRef pdp_ram_1_3_24)) + (portRef WEB (instanceRef pdp_ram_2_0_23)) + (portRef ADB2 (instanceRef pdp_ram_2_0_23)) + (portRef ADA2 (instanceRef pdp_ram_2_0_23)) + (portRef ADB1 (instanceRef pdp_ram_2_0_23)) + (portRef ADA1 (instanceRef pdp_ram_2_0_23)) + (portRef ADB0 (instanceRef pdp_ram_2_0_23)) + (portRef ADA0 (instanceRef pdp_ram_2_0_23)) + (portRef DIB17 (instanceRef pdp_ram_2_0_23)) + (portRef DIA17 (instanceRef pdp_ram_2_0_23)) + (portRef DIB16 (instanceRef pdp_ram_2_0_23)) + (portRef DIA16 (instanceRef pdp_ram_2_0_23)) + (portRef DIB15 (instanceRef pdp_ram_2_0_23)) + (portRef DIA15 (instanceRef pdp_ram_2_0_23)) + (portRef DIB14 (instanceRef pdp_ram_2_0_23)) + (portRef DIA14 (instanceRef pdp_ram_2_0_23)) + (portRef DIB13 (instanceRef pdp_ram_2_0_23)) + (portRef DIA13 (instanceRef pdp_ram_2_0_23)) + (portRef DIB12 (instanceRef pdp_ram_2_0_23)) + (portRef DIA12 (instanceRef pdp_ram_2_0_23)) + (portRef DIB11 (instanceRef pdp_ram_2_0_23)) + (portRef DIA11 (instanceRef pdp_ram_2_0_23)) + (portRef DIB10 (instanceRef pdp_ram_2_0_23)) + (portRef DIA10 (instanceRef pdp_ram_2_0_23)) + (portRef DIB9 (instanceRef pdp_ram_2_0_23)) + (portRef DIA9 (instanceRef pdp_ram_2_0_23)) + (portRef DIB8 (instanceRef pdp_ram_2_0_23)) + (portRef DIB7 (instanceRef pdp_ram_2_0_23)) + (portRef DIB6 (instanceRef pdp_ram_2_0_23)) + (portRef DIB5 (instanceRef pdp_ram_2_0_23)) + (portRef DIB4 (instanceRef pdp_ram_2_0_23)) + (portRef DIB3 (instanceRef pdp_ram_2_0_23)) + (portRef DIB2 (instanceRef pdp_ram_2_0_23)) + (portRef DIB1 (instanceRef pdp_ram_2_0_23)) + (portRef DIB0 (instanceRef pdp_ram_2_0_23)) + (portRef WEB (instanceRef pdp_ram_2_1_22)) + (portRef ADB2 (instanceRef pdp_ram_2_1_22)) + (portRef ADA2 (instanceRef pdp_ram_2_1_22)) + (portRef ADB1 (instanceRef pdp_ram_2_1_22)) + (portRef ADA1 (instanceRef pdp_ram_2_1_22)) + (portRef ADB0 (instanceRef pdp_ram_2_1_22)) + (portRef ADA0 (instanceRef pdp_ram_2_1_22)) + (portRef DIB17 (instanceRef pdp_ram_2_1_22)) + (portRef DIA17 (instanceRef pdp_ram_2_1_22)) + (portRef DIB16 (instanceRef pdp_ram_2_1_22)) + (portRef DIA16 (instanceRef pdp_ram_2_1_22)) + (portRef DIB15 (instanceRef pdp_ram_2_1_22)) + (portRef DIA15 (instanceRef pdp_ram_2_1_22)) + (portRef DIB14 (instanceRef pdp_ram_2_1_22)) + (portRef DIA14 (instanceRef pdp_ram_2_1_22)) + (portRef DIB13 (instanceRef pdp_ram_2_1_22)) + (portRef DIA13 (instanceRef pdp_ram_2_1_22)) + (portRef DIB12 (instanceRef pdp_ram_2_1_22)) + (portRef DIA12 (instanceRef pdp_ram_2_1_22)) + (portRef DIB11 (instanceRef pdp_ram_2_1_22)) + (portRef DIA11 (instanceRef pdp_ram_2_1_22)) + (portRef DIB10 (instanceRef pdp_ram_2_1_22)) + (portRef DIA10 (instanceRef pdp_ram_2_1_22)) + (portRef DIB9 (instanceRef pdp_ram_2_1_22)) + (portRef DIA9 (instanceRef pdp_ram_2_1_22)) + (portRef DIB8 (instanceRef pdp_ram_2_1_22)) + (portRef DIB7 (instanceRef pdp_ram_2_1_22)) + (portRef DIB6 (instanceRef pdp_ram_2_1_22)) + (portRef DIB5 (instanceRef pdp_ram_2_1_22)) + (portRef DIB4 (instanceRef pdp_ram_2_1_22)) + (portRef DIB3 (instanceRef pdp_ram_2_1_22)) + (portRef DIB2 (instanceRef pdp_ram_2_1_22)) + (portRef DIB1 (instanceRef pdp_ram_2_1_22)) + (portRef DIB0 (instanceRef pdp_ram_2_1_22)) + (portRef WEB (instanceRef pdp_ram_2_2_21)) + (portRef ADB2 (instanceRef pdp_ram_2_2_21)) + (portRef ADA2 (instanceRef pdp_ram_2_2_21)) + (portRef ADB1 (instanceRef pdp_ram_2_2_21)) + (portRef ADA1 (instanceRef pdp_ram_2_2_21)) + (portRef ADB0 (instanceRef pdp_ram_2_2_21)) + (portRef ADA0 (instanceRef pdp_ram_2_2_21)) + (portRef DIB17 (instanceRef pdp_ram_2_2_21)) + (portRef DIA17 (instanceRef pdp_ram_2_2_21)) + (portRef DIB16 (instanceRef pdp_ram_2_2_21)) + (portRef DIA16 (instanceRef pdp_ram_2_2_21)) + (portRef DIB15 (instanceRef pdp_ram_2_2_21)) + (portRef DIA15 (instanceRef pdp_ram_2_2_21)) + (portRef DIB14 (instanceRef pdp_ram_2_2_21)) + (portRef DIA14 (instanceRef pdp_ram_2_2_21)) + (portRef DIB13 (instanceRef pdp_ram_2_2_21)) + (portRef DIA13 (instanceRef pdp_ram_2_2_21)) + (portRef DIB12 (instanceRef pdp_ram_2_2_21)) + (portRef DIA12 (instanceRef pdp_ram_2_2_21)) + (portRef DIB11 (instanceRef pdp_ram_2_2_21)) + (portRef DIA11 (instanceRef pdp_ram_2_2_21)) + (portRef DIB10 (instanceRef pdp_ram_2_2_21)) + (portRef DIA10 (instanceRef pdp_ram_2_2_21)) + (portRef DIB9 (instanceRef pdp_ram_2_2_21)) + (portRef DIA9 (instanceRef pdp_ram_2_2_21)) + (portRef DIB8 (instanceRef pdp_ram_2_2_21)) + (portRef DIB7 (instanceRef pdp_ram_2_2_21)) + (portRef DIB6 (instanceRef pdp_ram_2_2_21)) + (portRef DIB5 (instanceRef pdp_ram_2_2_21)) + (portRef DIB4 (instanceRef pdp_ram_2_2_21)) + (portRef DIB3 (instanceRef pdp_ram_2_2_21)) + (portRef DIB2 (instanceRef pdp_ram_2_2_21)) + (portRef DIB1 (instanceRef pdp_ram_2_2_21)) + (portRef DIB0 (instanceRef pdp_ram_2_2_21)) + (portRef WEB (instanceRef pdp_ram_2_3_20)) + (portRef ADB2 (instanceRef pdp_ram_2_3_20)) + (portRef ADA2 (instanceRef pdp_ram_2_3_20)) + (portRef ADB1 (instanceRef pdp_ram_2_3_20)) + (portRef ADA1 (instanceRef pdp_ram_2_3_20)) + (portRef ADB0 (instanceRef pdp_ram_2_3_20)) + (portRef ADA0 (instanceRef pdp_ram_2_3_20)) + (portRef DIB17 (instanceRef pdp_ram_2_3_20)) + (portRef DIA17 (instanceRef pdp_ram_2_3_20)) + (portRef DIB16 (instanceRef pdp_ram_2_3_20)) + (portRef DIA16 (instanceRef pdp_ram_2_3_20)) + (portRef DIB15 (instanceRef pdp_ram_2_3_20)) + (portRef DIA15 (instanceRef pdp_ram_2_3_20)) + (portRef DIB14 (instanceRef pdp_ram_2_3_20)) + (portRef DIA14 (instanceRef pdp_ram_2_3_20)) + (portRef DIB13 (instanceRef pdp_ram_2_3_20)) + (portRef DIA13 (instanceRef pdp_ram_2_3_20)) + (portRef DIB12 (instanceRef pdp_ram_2_3_20)) + (portRef DIA12 (instanceRef pdp_ram_2_3_20)) + (portRef DIB11 (instanceRef pdp_ram_2_3_20)) + (portRef DIA11 (instanceRef pdp_ram_2_3_20)) + (portRef DIB10 (instanceRef pdp_ram_2_3_20)) + (portRef DIA10 (instanceRef pdp_ram_2_3_20)) + (portRef DIB9 (instanceRef pdp_ram_2_3_20)) + (portRef DIA9 (instanceRef pdp_ram_2_3_20)) + (portRef DIB8 (instanceRef pdp_ram_2_3_20)) + (portRef DIB7 (instanceRef pdp_ram_2_3_20)) + (portRef DIB6 (instanceRef pdp_ram_2_3_20)) + (portRef DIB5 (instanceRef pdp_ram_2_3_20)) + (portRef DIB4 (instanceRef pdp_ram_2_3_20)) + (portRef DIB3 (instanceRef pdp_ram_2_3_20)) + (portRef DIB2 (instanceRef pdp_ram_2_3_20)) + (portRef DIB1 (instanceRef pdp_ram_2_3_20)) + (portRef DIB0 (instanceRef pdp_ram_2_3_20)) + (portRef WEB (instanceRef pdp_ram_3_0_19)) + (portRef ADB2 (instanceRef pdp_ram_3_0_19)) + (portRef ADA2 (instanceRef pdp_ram_3_0_19)) + (portRef ADB1 (instanceRef pdp_ram_3_0_19)) + (portRef ADA1 (instanceRef pdp_ram_3_0_19)) + (portRef ADB0 (instanceRef pdp_ram_3_0_19)) + (portRef ADA0 (instanceRef pdp_ram_3_0_19)) + (portRef DIB17 (instanceRef pdp_ram_3_0_19)) + (portRef DIA17 (instanceRef pdp_ram_3_0_19)) + (portRef DIB16 (instanceRef pdp_ram_3_0_19)) + (portRef DIA16 (instanceRef pdp_ram_3_0_19)) + (portRef DIB15 (instanceRef pdp_ram_3_0_19)) + (portRef DIA15 (instanceRef pdp_ram_3_0_19)) + (portRef DIB14 (instanceRef pdp_ram_3_0_19)) + (portRef DIA14 (instanceRef pdp_ram_3_0_19)) + (portRef DIB13 (instanceRef pdp_ram_3_0_19)) + (portRef DIA13 (instanceRef pdp_ram_3_0_19)) + (portRef DIB12 (instanceRef pdp_ram_3_0_19)) + (portRef DIA12 (instanceRef pdp_ram_3_0_19)) + (portRef DIB11 (instanceRef pdp_ram_3_0_19)) + (portRef DIA11 (instanceRef pdp_ram_3_0_19)) + (portRef DIB10 (instanceRef pdp_ram_3_0_19)) + (portRef DIA10 (instanceRef pdp_ram_3_0_19)) + (portRef DIB9 (instanceRef pdp_ram_3_0_19)) + (portRef DIA9 (instanceRef pdp_ram_3_0_19)) + (portRef DIB8 (instanceRef pdp_ram_3_0_19)) + (portRef DIB7 (instanceRef pdp_ram_3_0_19)) + (portRef DIB6 (instanceRef pdp_ram_3_0_19)) + (portRef DIB5 (instanceRef pdp_ram_3_0_19)) + (portRef DIB4 (instanceRef pdp_ram_3_0_19)) + (portRef DIB3 (instanceRef pdp_ram_3_0_19)) + (portRef DIB2 (instanceRef pdp_ram_3_0_19)) + (portRef DIB1 (instanceRef pdp_ram_3_0_19)) + (portRef DIB0 (instanceRef pdp_ram_3_0_19)) + (portRef WEB (instanceRef pdp_ram_3_1_18)) + (portRef ADB2 (instanceRef pdp_ram_3_1_18)) + (portRef ADA2 (instanceRef pdp_ram_3_1_18)) + (portRef ADB1 (instanceRef pdp_ram_3_1_18)) + (portRef ADA1 (instanceRef pdp_ram_3_1_18)) + (portRef ADB0 (instanceRef pdp_ram_3_1_18)) + (portRef ADA0 (instanceRef pdp_ram_3_1_18)) + (portRef DIB17 (instanceRef pdp_ram_3_1_18)) + (portRef DIA17 (instanceRef pdp_ram_3_1_18)) + (portRef DIB16 (instanceRef pdp_ram_3_1_18)) + (portRef DIA16 (instanceRef pdp_ram_3_1_18)) + (portRef DIB15 (instanceRef pdp_ram_3_1_18)) + (portRef DIA15 (instanceRef pdp_ram_3_1_18)) + (portRef DIB14 (instanceRef pdp_ram_3_1_18)) + (portRef DIA14 (instanceRef pdp_ram_3_1_18)) + (portRef DIB13 (instanceRef pdp_ram_3_1_18)) + (portRef DIA13 (instanceRef pdp_ram_3_1_18)) + (portRef DIB12 (instanceRef pdp_ram_3_1_18)) + (portRef DIA12 (instanceRef pdp_ram_3_1_18)) + (portRef DIB11 (instanceRef pdp_ram_3_1_18)) + (portRef DIA11 (instanceRef pdp_ram_3_1_18)) + (portRef DIB10 (instanceRef pdp_ram_3_1_18)) + (portRef DIA10 (instanceRef pdp_ram_3_1_18)) + (portRef DIB9 (instanceRef pdp_ram_3_1_18)) + (portRef DIA9 (instanceRef pdp_ram_3_1_18)) + (portRef DIB8 (instanceRef pdp_ram_3_1_18)) + (portRef DIB7 (instanceRef pdp_ram_3_1_18)) + (portRef DIB6 (instanceRef pdp_ram_3_1_18)) + (portRef DIB5 (instanceRef pdp_ram_3_1_18)) + (portRef DIB4 (instanceRef pdp_ram_3_1_18)) + (portRef DIB3 (instanceRef pdp_ram_3_1_18)) + (portRef DIB2 (instanceRef pdp_ram_3_1_18)) + (portRef DIB1 (instanceRef pdp_ram_3_1_18)) + (portRef DIB0 (instanceRef pdp_ram_3_1_18)) + (portRef WEB (instanceRef pdp_ram_3_2_17)) + (portRef ADB2 (instanceRef pdp_ram_3_2_17)) + (portRef ADA2 (instanceRef pdp_ram_3_2_17)) + (portRef ADB1 (instanceRef pdp_ram_3_2_17)) + (portRef ADA1 (instanceRef pdp_ram_3_2_17)) + (portRef ADB0 (instanceRef pdp_ram_3_2_17)) + (portRef ADA0 (instanceRef pdp_ram_3_2_17)) + (portRef DIB17 (instanceRef pdp_ram_3_2_17)) + (portRef DIA17 (instanceRef pdp_ram_3_2_17)) + (portRef DIB16 (instanceRef pdp_ram_3_2_17)) + (portRef DIA16 (instanceRef pdp_ram_3_2_17)) + (portRef DIB15 (instanceRef pdp_ram_3_2_17)) + (portRef DIA15 (instanceRef pdp_ram_3_2_17)) + (portRef DIB14 (instanceRef pdp_ram_3_2_17)) + (portRef DIA14 (instanceRef pdp_ram_3_2_17)) + (portRef DIB13 (instanceRef pdp_ram_3_2_17)) + (portRef DIA13 (instanceRef pdp_ram_3_2_17)) + (portRef DIB12 (instanceRef pdp_ram_3_2_17)) + (portRef DIA12 (instanceRef pdp_ram_3_2_17)) + (portRef DIB11 (instanceRef pdp_ram_3_2_17)) + (portRef DIA11 (instanceRef pdp_ram_3_2_17)) + (portRef DIB10 (instanceRef pdp_ram_3_2_17)) + (portRef DIA10 (instanceRef pdp_ram_3_2_17)) + (portRef DIB9 (instanceRef pdp_ram_3_2_17)) + (portRef DIA9 (instanceRef pdp_ram_3_2_17)) + (portRef DIB8 (instanceRef pdp_ram_3_2_17)) + (portRef DIB7 (instanceRef pdp_ram_3_2_17)) + (portRef DIB6 (instanceRef pdp_ram_3_2_17)) + (portRef DIB5 (instanceRef pdp_ram_3_2_17)) + (portRef DIB4 (instanceRef pdp_ram_3_2_17)) + (portRef DIB3 (instanceRef pdp_ram_3_2_17)) + (portRef DIB2 (instanceRef pdp_ram_3_2_17)) + (portRef DIB1 (instanceRef pdp_ram_3_2_17)) + (portRef DIB0 (instanceRef pdp_ram_3_2_17)) + (portRef WEB (instanceRef pdp_ram_3_3_16)) + (portRef ADB2 (instanceRef pdp_ram_3_3_16)) + (portRef ADA2 (instanceRef pdp_ram_3_3_16)) + (portRef ADB1 (instanceRef pdp_ram_3_3_16)) + (portRef ADA1 (instanceRef pdp_ram_3_3_16)) + (portRef ADB0 (instanceRef pdp_ram_3_3_16)) + (portRef ADA0 (instanceRef pdp_ram_3_3_16)) + (portRef DIB17 (instanceRef pdp_ram_3_3_16)) + (portRef DIA17 (instanceRef pdp_ram_3_3_16)) + (portRef DIB16 (instanceRef pdp_ram_3_3_16)) + (portRef DIA16 (instanceRef pdp_ram_3_3_16)) + (portRef DIB15 (instanceRef pdp_ram_3_3_16)) + (portRef DIA15 (instanceRef pdp_ram_3_3_16)) + (portRef DIB14 (instanceRef pdp_ram_3_3_16)) + (portRef DIA14 (instanceRef pdp_ram_3_3_16)) + (portRef DIB13 (instanceRef pdp_ram_3_3_16)) + (portRef DIA13 (instanceRef pdp_ram_3_3_16)) + (portRef DIB12 (instanceRef pdp_ram_3_3_16)) + (portRef DIA12 (instanceRef pdp_ram_3_3_16)) + (portRef DIB11 (instanceRef pdp_ram_3_3_16)) + (portRef DIA11 (instanceRef pdp_ram_3_3_16)) + (portRef DIB10 (instanceRef pdp_ram_3_3_16)) + (portRef DIA10 (instanceRef pdp_ram_3_3_16)) + (portRef DIB9 (instanceRef pdp_ram_3_3_16)) + (portRef DIA9 (instanceRef pdp_ram_3_3_16)) + (portRef DIB8 (instanceRef pdp_ram_3_3_16)) + (portRef DIB7 (instanceRef pdp_ram_3_3_16)) + (portRef DIB6 (instanceRef pdp_ram_3_3_16)) + (portRef DIB5 (instanceRef pdp_ram_3_3_16)) + (portRef DIB4 (instanceRef pdp_ram_3_3_16)) + (portRef DIB3 (instanceRef pdp_ram_3_3_16)) + (portRef DIB2 (instanceRef pdp_ram_3_3_16)) + (portRef DIB1 (instanceRef pdp_ram_3_3_16)) + (portRef DIB0 (instanceRef pdp_ram_3_3_16)) + (portRef WEB (instanceRef pdp_ram_4_0_15)) + (portRef ADB2 (instanceRef pdp_ram_4_0_15)) + (portRef ADA2 (instanceRef pdp_ram_4_0_15)) + (portRef ADB1 (instanceRef pdp_ram_4_0_15)) + (portRef ADA1 (instanceRef pdp_ram_4_0_15)) + (portRef ADB0 (instanceRef pdp_ram_4_0_15)) + (portRef ADA0 (instanceRef pdp_ram_4_0_15)) + (portRef DIB17 (instanceRef pdp_ram_4_0_15)) + (portRef DIA17 (instanceRef pdp_ram_4_0_15)) + (portRef DIB16 (instanceRef pdp_ram_4_0_15)) + (portRef DIA16 (instanceRef pdp_ram_4_0_15)) + (portRef DIB15 (instanceRef pdp_ram_4_0_15)) + (portRef DIA15 (instanceRef pdp_ram_4_0_15)) + (portRef DIB14 (instanceRef pdp_ram_4_0_15)) + (portRef DIA14 (instanceRef pdp_ram_4_0_15)) + (portRef DIB13 (instanceRef pdp_ram_4_0_15)) + (portRef DIA13 (instanceRef pdp_ram_4_0_15)) + (portRef DIB12 (instanceRef pdp_ram_4_0_15)) + (portRef DIA12 (instanceRef pdp_ram_4_0_15)) + (portRef DIB11 (instanceRef pdp_ram_4_0_15)) + (portRef DIA11 (instanceRef pdp_ram_4_0_15)) + (portRef DIB10 (instanceRef pdp_ram_4_0_15)) + (portRef DIA10 (instanceRef pdp_ram_4_0_15)) + (portRef DIB9 (instanceRef pdp_ram_4_0_15)) + (portRef DIA9 (instanceRef pdp_ram_4_0_15)) + (portRef DIB8 (instanceRef pdp_ram_4_0_15)) + (portRef DIB7 (instanceRef pdp_ram_4_0_15)) + (portRef DIB6 (instanceRef pdp_ram_4_0_15)) + (portRef DIB5 (instanceRef pdp_ram_4_0_15)) + (portRef DIB4 (instanceRef pdp_ram_4_0_15)) + (portRef DIB3 (instanceRef pdp_ram_4_0_15)) + (portRef DIB2 (instanceRef pdp_ram_4_0_15)) + (portRef DIB1 (instanceRef pdp_ram_4_0_15)) + (portRef DIB0 (instanceRef pdp_ram_4_0_15)) + (portRef WEB (instanceRef pdp_ram_4_1_14)) + (portRef ADB2 (instanceRef pdp_ram_4_1_14)) + (portRef ADA2 (instanceRef pdp_ram_4_1_14)) + (portRef ADB1 (instanceRef pdp_ram_4_1_14)) + (portRef ADA1 (instanceRef pdp_ram_4_1_14)) + (portRef ADB0 (instanceRef pdp_ram_4_1_14)) + (portRef ADA0 (instanceRef pdp_ram_4_1_14)) + (portRef DIB17 (instanceRef pdp_ram_4_1_14)) + (portRef DIA17 (instanceRef pdp_ram_4_1_14)) + (portRef DIB16 (instanceRef pdp_ram_4_1_14)) + (portRef DIA16 (instanceRef pdp_ram_4_1_14)) + (portRef DIB15 (instanceRef pdp_ram_4_1_14)) + (portRef DIA15 (instanceRef pdp_ram_4_1_14)) + (portRef DIB14 (instanceRef pdp_ram_4_1_14)) + (portRef DIA14 (instanceRef pdp_ram_4_1_14)) + (portRef DIB13 (instanceRef pdp_ram_4_1_14)) + (portRef DIA13 (instanceRef pdp_ram_4_1_14)) + (portRef DIB12 (instanceRef pdp_ram_4_1_14)) + (portRef DIA12 (instanceRef pdp_ram_4_1_14)) + (portRef DIB11 (instanceRef pdp_ram_4_1_14)) + (portRef DIA11 (instanceRef pdp_ram_4_1_14)) + (portRef DIB10 (instanceRef pdp_ram_4_1_14)) + (portRef DIA10 (instanceRef pdp_ram_4_1_14)) + (portRef DIB9 (instanceRef pdp_ram_4_1_14)) + (portRef DIA9 (instanceRef pdp_ram_4_1_14)) + (portRef DIB8 (instanceRef pdp_ram_4_1_14)) + (portRef DIB7 (instanceRef pdp_ram_4_1_14)) + (portRef DIB6 (instanceRef pdp_ram_4_1_14)) + (portRef DIB5 (instanceRef pdp_ram_4_1_14)) + (portRef DIB4 (instanceRef pdp_ram_4_1_14)) + (portRef DIB3 (instanceRef pdp_ram_4_1_14)) + (portRef DIB2 (instanceRef pdp_ram_4_1_14)) + (portRef DIB1 (instanceRef pdp_ram_4_1_14)) + (portRef DIB0 (instanceRef pdp_ram_4_1_14)) + (portRef WEB (instanceRef pdp_ram_4_2_13)) + (portRef ADB2 (instanceRef pdp_ram_4_2_13)) + (portRef ADA2 (instanceRef pdp_ram_4_2_13)) + (portRef ADB1 (instanceRef pdp_ram_4_2_13)) + (portRef ADA1 (instanceRef pdp_ram_4_2_13)) + (portRef ADB0 (instanceRef pdp_ram_4_2_13)) + (portRef ADA0 (instanceRef pdp_ram_4_2_13)) + (portRef DIB17 (instanceRef pdp_ram_4_2_13)) + (portRef DIA17 (instanceRef pdp_ram_4_2_13)) + (portRef DIB16 (instanceRef pdp_ram_4_2_13)) + (portRef DIA16 (instanceRef pdp_ram_4_2_13)) + (portRef DIB15 (instanceRef pdp_ram_4_2_13)) + (portRef DIA15 (instanceRef pdp_ram_4_2_13)) + (portRef DIB14 (instanceRef pdp_ram_4_2_13)) + (portRef DIA14 (instanceRef pdp_ram_4_2_13)) + (portRef DIB13 (instanceRef pdp_ram_4_2_13)) + (portRef DIA13 (instanceRef pdp_ram_4_2_13)) + (portRef DIB12 (instanceRef pdp_ram_4_2_13)) + (portRef DIA12 (instanceRef pdp_ram_4_2_13)) + (portRef DIB11 (instanceRef pdp_ram_4_2_13)) + (portRef DIA11 (instanceRef pdp_ram_4_2_13)) + (portRef DIB10 (instanceRef pdp_ram_4_2_13)) + (portRef DIA10 (instanceRef pdp_ram_4_2_13)) + (portRef DIB9 (instanceRef pdp_ram_4_2_13)) + (portRef DIA9 (instanceRef pdp_ram_4_2_13)) + (portRef DIB8 (instanceRef pdp_ram_4_2_13)) + (portRef DIB7 (instanceRef pdp_ram_4_2_13)) + (portRef DIB6 (instanceRef pdp_ram_4_2_13)) + (portRef DIB5 (instanceRef pdp_ram_4_2_13)) + (portRef DIB4 (instanceRef pdp_ram_4_2_13)) + (portRef DIB3 (instanceRef pdp_ram_4_2_13)) + (portRef DIB2 (instanceRef pdp_ram_4_2_13)) + (portRef DIB1 (instanceRef pdp_ram_4_2_13)) + (portRef DIB0 (instanceRef pdp_ram_4_2_13)) + (portRef WEB (instanceRef pdp_ram_4_3_12)) + (portRef ADB2 (instanceRef pdp_ram_4_3_12)) + (portRef ADA2 (instanceRef pdp_ram_4_3_12)) + (portRef ADB1 (instanceRef pdp_ram_4_3_12)) + (portRef ADA1 (instanceRef pdp_ram_4_3_12)) + (portRef ADB0 (instanceRef pdp_ram_4_3_12)) + (portRef ADA0 (instanceRef pdp_ram_4_3_12)) + (portRef DIB17 (instanceRef pdp_ram_4_3_12)) + (portRef DIA17 (instanceRef pdp_ram_4_3_12)) + (portRef DIB16 (instanceRef pdp_ram_4_3_12)) + (portRef DIA16 (instanceRef pdp_ram_4_3_12)) + (portRef DIB15 (instanceRef pdp_ram_4_3_12)) + (portRef DIA15 (instanceRef pdp_ram_4_3_12)) + (portRef DIB14 (instanceRef pdp_ram_4_3_12)) + (portRef DIA14 (instanceRef pdp_ram_4_3_12)) + (portRef DIB13 (instanceRef pdp_ram_4_3_12)) + (portRef DIA13 (instanceRef pdp_ram_4_3_12)) + (portRef DIB12 (instanceRef pdp_ram_4_3_12)) + (portRef DIA12 (instanceRef pdp_ram_4_3_12)) + (portRef DIB11 (instanceRef pdp_ram_4_3_12)) + (portRef DIA11 (instanceRef pdp_ram_4_3_12)) + (portRef DIB10 (instanceRef pdp_ram_4_3_12)) + (portRef DIA10 (instanceRef pdp_ram_4_3_12)) + (portRef DIB9 (instanceRef pdp_ram_4_3_12)) + (portRef DIA9 (instanceRef pdp_ram_4_3_12)) + (portRef DIB8 (instanceRef pdp_ram_4_3_12)) + (portRef DIB7 (instanceRef pdp_ram_4_3_12)) + (portRef DIB6 (instanceRef pdp_ram_4_3_12)) + (portRef DIB5 (instanceRef pdp_ram_4_3_12)) + (portRef DIB4 (instanceRef pdp_ram_4_3_12)) + (portRef DIB3 (instanceRef pdp_ram_4_3_12)) + (portRef DIB2 (instanceRef pdp_ram_4_3_12)) + (portRef DIB1 (instanceRef pdp_ram_4_3_12)) + (portRef DIB0 (instanceRef pdp_ram_4_3_12)) + (portRef WEB (instanceRef pdp_ram_5_0_11)) + (portRef ADB2 (instanceRef pdp_ram_5_0_11)) + (portRef ADA2 (instanceRef pdp_ram_5_0_11)) + (portRef ADB1 (instanceRef pdp_ram_5_0_11)) + (portRef ADA1 (instanceRef pdp_ram_5_0_11)) + (portRef ADB0 (instanceRef pdp_ram_5_0_11)) + (portRef ADA0 (instanceRef pdp_ram_5_0_11)) + (portRef DIB17 (instanceRef pdp_ram_5_0_11)) + (portRef DIA17 (instanceRef pdp_ram_5_0_11)) + (portRef DIB16 (instanceRef pdp_ram_5_0_11)) + (portRef DIA16 (instanceRef pdp_ram_5_0_11)) + (portRef DIB15 (instanceRef pdp_ram_5_0_11)) + (portRef DIA15 (instanceRef pdp_ram_5_0_11)) + (portRef DIB14 (instanceRef pdp_ram_5_0_11)) + (portRef DIA14 (instanceRef pdp_ram_5_0_11)) + (portRef DIB13 (instanceRef pdp_ram_5_0_11)) + (portRef DIA13 (instanceRef pdp_ram_5_0_11)) + (portRef DIB12 (instanceRef pdp_ram_5_0_11)) + (portRef DIA12 (instanceRef pdp_ram_5_0_11)) + (portRef DIB11 (instanceRef pdp_ram_5_0_11)) + (portRef DIA11 (instanceRef pdp_ram_5_0_11)) + (portRef DIB10 (instanceRef pdp_ram_5_0_11)) + (portRef DIA10 (instanceRef pdp_ram_5_0_11)) + (portRef DIB9 (instanceRef pdp_ram_5_0_11)) + (portRef DIA9 (instanceRef pdp_ram_5_0_11)) + (portRef DIB8 (instanceRef pdp_ram_5_0_11)) + (portRef DIB7 (instanceRef pdp_ram_5_0_11)) + (portRef DIB6 (instanceRef pdp_ram_5_0_11)) + (portRef DIB5 (instanceRef pdp_ram_5_0_11)) + (portRef DIB4 (instanceRef pdp_ram_5_0_11)) + (portRef DIB3 (instanceRef pdp_ram_5_0_11)) + (portRef DIB2 (instanceRef pdp_ram_5_0_11)) + (portRef DIB1 (instanceRef pdp_ram_5_0_11)) + (portRef DIB0 (instanceRef pdp_ram_5_0_11)) + (portRef WEB (instanceRef pdp_ram_5_1_10)) + (portRef ADB2 (instanceRef pdp_ram_5_1_10)) + (portRef ADA2 (instanceRef pdp_ram_5_1_10)) + (portRef ADB1 (instanceRef pdp_ram_5_1_10)) + (portRef ADA1 (instanceRef pdp_ram_5_1_10)) + (portRef ADB0 (instanceRef pdp_ram_5_1_10)) + (portRef ADA0 (instanceRef pdp_ram_5_1_10)) + (portRef DIB17 (instanceRef pdp_ram_5_1_10)) + (portRef DIA17 (instanceRef pdp_ram_5_1_10)) + (portRef DIB16 (instanceRef pdp_ram_5_1_10)) + (portRef DIA16 (instanceRef pdp_ram_5_1_10)) + (portRef DIB15 (instanceRef pdp_ram_5_1_10)) + (portRef DIA15 (instanceRef pdp_ram_5_1_10)) + (portRef DIB14 (instanceRef pdp_ram_5_1_10)) + (portRef DIA14 (instanceRef pdp_ram_5_1_10)) + (portRef DIB13 (instanceRef pdp_ram_5_1_10)) + (portRef DIA13 (instanceRef pdp_ram_5_1_10)) + (portRef DIB12 (instanceRef pdp_ram_5_1_10)) + (portRef DIA12 (instanceRef pdp_ram_5_1_10)) + (portRef DIB11 (instanceRef pdp_ram_5_1_10)) + (portRef DIA11 (instanceRef pdp_ram_5_1_10)) + (portRef DIB10 (instanceRef pdp_ram_5_1_10)) + (portRef DIA10 (instanceRef pdp_ram_5_1_10)) + (portRef DIB9 (instanceRef pdp_ram_5_1_10)) + (portRef DIA9 (instanceRef pdp_ram_5_1_10)) + (portRef DIB8 (instanceRef pdp_ram_5_1_10)) + (portRef DIB7 (instanceRef pdp_ram_5_1_10)) + (portRef DIB6 (instanceRef pdp_ram_5_1_10)) + (portRef DIB5 (instanceRef pdp_ram_5_1_10)) + (portRef DIB4 (instanceRef pdp_ram_5_1_10)) + (portRef DIB3 (instanceRef pdp_ram_5_1_10)) + (portRef DIB2 (instanceRef pdp_ram_5_1_10)) + (portRef DIB1 (instanceRef pdp_ram_5_1_10)) + (portRef DIB0 (instanceRef pdp_ram_5_1_10)) + (portRef WEB (instanceRef pdp_ram_5_2_9)) + (portRef ADB2 (instanceRef pdp_ram_5_2_9)) + (portRef ADA2 (instanceRef pdp_ram_5_2_9)) + (portRef ADB1 (instanceRef pdp_ram_5_2_9)) + (portRef ADA1 (instanceRef pdp_ram_5_2_9)) + (portRef ADB0 (instanceRef pdp_ram_5_2_9)) + (portRef ADA0 (instanceRef pdp_ram_5_2_9)) + (portRef DIB17 (instanceRef pdp_ram_5_2_9)) + (portRef DIA17 (instanceRef pdp_ram_5_2_9)) + (portRef DIB16 (instanceRef pdp_ram_5_2_9)) + (portRef DIA16 (instanceRef pdp_ram_5_2_9)) + (portRef DIB15 (instanceRef pdp_ram_5_2_9)) + (portRef DIA15 (instanceRef pdp_ram_5_2_9)) + (portRef DIB14 (instanceRef pdp_ram_5_2_9)) + (portRef DIA14 (instanceRef pdp_ram_5_2_9)) + (portRef DIB13 (instanceRef pdp_ram_5_2_9)) + (portRef DIA13 (instanceRef pdp_ram_5_2_9)) + (portRef DIB12 (instanceRef pdp_ram_5_2_9)) + (portRef DIA12 (instanceRef pdp_ram_5_2_9)) + (portRef DIB11 (instanceRef pdp_ram_5_2_9)) + (portRef DIA11 (instanceRef pdp_ram_5_2_9)) + (portRef DIB10 (instanceRef pdp_ram_5_2_9)) + (portRef DIA10 (instanceRef pdp_ram_5_2_9)) + (portRef DIB9 (instanceRef pdp_ram_5_2_9)) + (portRef DIA9 (instanceRef pdp_ram_5_2_9)) + (portRef DIB8 (instanceRef pdp_ram_5_2_9)) + (portRef DIB7 (instanceRef pdp_ram_5_2_9)) + (portRef DIB6 (instanceRef pdp_ram_5_2_9)) + (portRef DIB5 (instanceRef pdp_ram_5_2_9)) + (portRef DIB4 (instanceRef pdp_ram_5_2_9)) + (portRef DIB3 (instanceRef pdp_ram_5_2_9)) + (portRef DIB2 (instanceRef pdp_ram_5_2_9)) + (portRef DIB1 (instanceRef pdp_ram_5_2_9)) + (portRef DIB0 (instanceRef pdp_ram_5_2_9)) + (portRef WEB (instanceRef pdp_ram_5_3_8)) + (portRef ADB2 (instanceRef pdp_ram_5_3_8)) + (portRef ADA2 (instanceRef pdp_ram_5_3_8)) + (portRef ADB1 (instanceRef pdp_ram_5_3_8)) + (portRef ADA1 (instanceRef pdp_ram_5_3_8)) + (portRef ADB0 (instanceRef pdp_ram_5_3_8)) + (portRef ADA0 (instanceRef pdp_ram_5_3_8)) + (portRef DIB17 (instanceRef pdp_ram_5_3_8)) + (portRef DIA17 (instanceRef pdp_ram_5_3_8)) + (portRef DIB16 (instanceRef pdp_ram_5_3_8)) + (portRef DIA16 (instanceRef pdp_ram_5_3_8)) + (portRef DIB15 (instanceRef pdp_ram_5_3_8)) + (portRef DIA15 (instanceRef pdp_ram_5_3_8)) + (portRef DIB14 (instanceRef pdp_ram_5_3_8)) + (portRef DIA14 (instanceRef pdp_ram_5_3_8)) + (portRef DIB13 (instanceRef pdp_ram_5_3_8)) + (portRef DIA13 (instanceRef pdp_ram_5_3_8)) + (portRef DIB12 (instanceRef pdp_ram_5_3_8)) + (portRef DIA12 (instanceRef pdp_ram_5_3_8)) + (portRef DIB11 (instanceRef pdp_ram_5_3_8)) + (portRef DIA11 (instanceRef pdp_ram_5_3_8)) + (portRef DIB10 (instanceRef pdp_ram_5_3_8)) + (portRef DIA10 (instanceRef pdp_ram_5_3_8)) + (portRef DIB9 (instanceRef pdp_ram_5_3_8)) + (portRef DIA9 (instanceRef pdp_ram_5_3_8)) + (portRef DIB8 (instanceRef pdp_ram_5_3_8)) + (portRef DIB7 (instanceRef pdp_ram_5_3_8)) + (portRef DIB6 (instanceRef pdp_ram_5_3_8)) + (portRef DIB5 (instanceRef pdp_ram_5_3_8)) + (portRef DIB4 (instanceRef pdp_ram_5_3_8)) + (portRef DIB3 (instanceRef pdp_ram_5_3_8)) + (portRef DIB2 (instanceRef pdp_ram_5_3_8)) + (portRef DIB1 (instanceRef pdp_ram_5_3_8)) + (portRef DIB0 (instanceRef pdp_ram_5_3_8)) + (portRef WEB (instanceRef pdp_ram_6_0_7)) + (portRef ADB2 (instanceRef pdp_ram_6_0_7)) + (portRef ADA2 (instanceRef pdp_ram_6_0_7)) + (portRef ADB1 (instanceRef pdp_ram_6_0_7)) + (portRef ADA1 (instanceRef pdp_ram_6_0_7)) + (portRef ADB0 (instanceRef pdp_ram_6_0_7)) + (portRef ADA0 (instanceRef pdp_ram_6_0_7)) + (portRef DIB17 (instanceRef pdp_ram_6_0_7)) + (portRef DIA17 (instanceRef pdp_ram_6_0_7)) + (portRef DIB16 (instanceRef pdp_ram_6_0_7)) + (portRef DIA16 (instanceRef pdp_ram_6_0_7)) + (portRef DIB15 (instanceRef pdp_ram_6_0_7)) + (portRef DIA15 (instanceRef pdp_ram_6_0_7)) + (portRef DIB14 (instanceRef pdp_ram_6_0_7)) + (portRef DIA14 (instanceRef pdp_ram_6_0_7)) + (portRef DIB13 (instanceRef pdp_ram_6_0_7)) + (portRef DIA13 (instanceRef pdp_ram_6_0_7)) + (portRef DIB12 (instanceRef pdp_ram_6_0_7)) + (portRef DIA12 (instanceRef pdp_ram_6_0_7)) + (portRef DIB11 (instanceRef pdp_ram_6_0_7)) + (portRef DIA11 (instanceRef pdp_ram_6_0_7)) + (portRef DIB10 (instanceRef pdp_ram_6_0_7)) + (portRef DIA10 (instanceRef pdp_ram_6_0_7)) + (portRef DIB9 (instanceRef pdp_ram_6_0_7)) + (portRef DIA9 (instanceRef pdp_ram_6_0_7)) + (portRef DIB8 (instanceRef pdp_ram_6_0_7)) + (portRef DIB7 (instanceRef pdp_ram_6_0_7)) + (portRef DIB6 (instanceRef pdp_ram_6_0_7)) + (portRef DIB5 (instanceRef pdp_ram_6_0_7)) + (portRef DIB4 (instanceRef pdp_ram_6_0_7)) + (portRef DIB3 (instanceRef pdp_ram_6_0_7)) + (portRef DIB2 (instanceRef pdp_ram_6_0_7)) + (portRef DIB1 (instanceRef pdp_ram_6_0_7)) + (portRef DIB0 (instanceRef pdp_ram_6_0_7)) + (portRef WEB (instanceRef pdp_ram_6_1_6)) + (portRef ADB2 (instanceRef pdp_ram_6_1_6)) + (portRef ADA2 (instanceRef pdp_ram_6_1_6)) + (portRef ADB1 (instanceRef pdp_ram_6_1_6)) + (portRef ADA1 (instanceRef pdp_ram_6_1_6)) + (portRef ADB0 (instanceRef pdp_ram_6_1_6)) + (portRef ADA0 (instanceRef pdp_ram_6_1_6)) + (portRef DIB17 (instanceRef pdp_ram_6_1_6)) + (portRef DIA17 (instanceRef pdp_ram_6_1_6)) + (portRef DIB16 (instanceRef pdp_ram_6_1_6)) + (portRef DIA16 (instanceRef pdp_ram_6_1_6)) + (portRef DIB15 (instanceRef pdp_ram_6_1_6)) + (portRef DIA15 (instanceRef pdp_ram_6_1_6)) + (portRef DIB14 (instanceRef pdp_ram_6_1_6)) + (portRef DIA14 (instanceRef pdp_ram_6_1_6)) + (portRef DIB13 (instanceRef pdp_ram_6_1_6)) + (portRef DIA13 (instanceRef pdp_ram_6_1_6)) + (portRef DIB12 (instanceRef pdp_ram_6_1_6)) + (portRef DIA12 (instanceRef pdp_ram_6_1_6)) + (portRef DIB11 (instanceRef pdp_ram_6_1_6)) + (portRef DIA11 (instanceRef pdp_ram_6_1_6)) + (portRef DIB10 (instanceRef pdp_ram_6_1_6)) + (portRef DIA10 (instanceRef pdp_ram_6_1_6)) + (portRef DIB9 (instanceRef pdp_ram_6_1_6)) + (portRef DIA9 (instanceRef pdp_ram_6_1_6)) + (portRef DIB8 (instanceRef pdp_ram_6_1_6)) + (portRef DIB7 (instanceRef pdp_ram_6_1_6)) + (portRef DIB6 (instanceRef pdp_ram_6_1_6)) + (portRef DIB5 (instanceRef pdp_ram_6_1_6)) + (portRef DIB4 (instanceRef pdp_ram_6_1_6)) + (portRef DIB3 (instanceRef pdp_ram_6_1_6)) + (portRef DIB2 (instanceRef pdp_ram_6_1_6)) + (portRef DIB1 (instanceRef pdp_ram_6_1_6)) + (portRef DIB0 (instanceRef pdp_ram_6_1_6)) + (portRef WEB (instanceRef pdp_ram_6_2_5)) + (portRef ADB2 (instanceRef pdp_ram_6_2_5)) + (portRef ADA2 (instanceRef pdp_ram_6_2_5)) + (portRef ADB1 (instanceRef pdp_ram_6_2_5)) + (portRef ADA1 (instanceRef pdp_ram_6_2_5)) + (portRef ADB0 (instanceRef pdp_ram_6_2_5)) + (portRef ADA0 (instanceRef pdp_ram_6_2_5)) + (portRef DIB17 (instanceRef pdp_ram_6_2_5)) + (portRef DIA17 (instanceRef pdp_ram_6_2_5)) + (portRef DIB16 (instanceRef pdp_ram_6_2_5)) + (portRef DIA16 (instanceRef pdp_ram_6_2_5)) + (portRef DIB15 (instanceRef pdp_ram_6_2_5)) + (portRef DIA15 (instanceRef pdp_ram_6_2_5)) + (portRef DIB14 (instanceRef pdp_ram_6_2_5)) + (portRef DIA14 (instanceRef pdp_ram_6_2_5)) + (portRef DIB13 (instanceRef pdp_ram_6_2_5)) + (portRef DIA13 (instanceRef pdp_ram_6_2_5)) + (portRef DIB12 (instanceRef pdp_ram_6_2_5)) + (portRef DIA12 (instanceRef pdp_ram_6_2_5)) + (portRef DIB11 (instanceRef pdp_ram_6_2_5)) + (portRef DIA11 (instanceRef pdp_ram_6_2_5)) + (portRef DIB10 (instanceRef pdp_ram_6_2_5)) + (portRef DIA10 (instanceRef pdp_ram_6_2_5)) + (portRef DIB9 (instanceRef pdp_ram_6_2_5)) + (portRef DIA9 (instanceRef pdp_ram_6_2_5)) + (portRef DIB8 (instanceRef pdp_ram_6_2_5)) + (portRef DIB7 (instanceRef pdp_ram_6_2_5)) + (portRef DIB6 (instanceRef pdp_ram_6_2_5)) + (portRef DIB5 (instanceRef pdp_ram_6_2_5)) + (portRef DIB4 (instanceRef pdp_ram_6_2_5)) + (portRef DIB3 (instanceRef pdp_ram_6_2_5)) + (portRef DIB2 (instanceRef pdp_ram_6_2_5)) + (portRef DIB1 (instanceRef pdp_ram_6_2_5)) + (portRef DIB0 (instanceRef pdp_ram_6_2_5)) + (portRef WEB (instanceRef pdp_ram_6_3_4)) + (portRef ADB2 (instanceRef pdp_ram_6_3_4)) + (portRef ADA2 (instanceRef pdp_ram_6_3_4)) + (portRef ADB1 (instanceRef pdp_ram_6_3_4)) + (portRef ADA1 (instanceRef pdp_ram_6_3_4)) + (portRef ADB0 (instanceRef pdp_ram_6_3_4)) + (portRef ADA0 (instanceRef pdp_ram_6_3_4)) + (portRef DIB17 (instanceRef pdp_ram_6_3_4)) + (portRef DIA17 (instanceRef pdp_ram_6_3_4)) + (portRef DIB16 (instanceRef pdp_ram_6_3_4)) + (portRef DIA16 (instanceRef pdp_ram_6_3_4)) + (portRef DIB15 (instanceRef pdp_ram_6_3_4)) + (portRef DIA15 (instanceRef pdp_ram_6_3_4)) + (portRef DIB14 (instanceRef pdp_ram_6_3_4)) + (portRef DIA14 (instanceRef pdp_ram_6_3_4)) + (portRef DIB13 (instanceRef pdp_ram_6_3_4)) + (portRef DIA13 (instanceRef pdp_ram_6_3_4)) + (portRef DIB12 (instanceRef pdp_ram_6_3_4)) + (portRef DIA12 (instanceRef pdp_ram_6_3_4)) + (portRef DIB11 (instanceRef pdp_ram_6_3_4)) + (portRef DIA11 (instanceRef pdp_ram_6_3_4)) + (portRef DIB10 (instanceRef pdp_ram_6_3_4)) + (portRef DIA10 (instanceRef pdp_ram_6_3_4)) + (portRef DIB9 (instanceRef pdp_ram_6_3_4)) + (portRef DIA9 (instanceRef pdp_ram_6_3_4)) + (portRef DIB8 (instanceRef pdp_ram_6_3_4)) + (portRef DIB7 (instanceRef pdp_ram_6_3_4)) + (portRef DIB6 (instanceRef pdp_ram_6_3_4)) + (portRef DIB5 (instanceRef pdp_ram_6_3_4)) + (portRef DIB4 (instanceRef pdp_ram_6_3_4)) + (portRef DIB3 (instanceRef pdp_ram_6_3_4)) + (portRef DIB2 (instanceRef pdp_ram_6_3_4)) + (portRef DIB1 (instanceRef pdp_ram_6_3_4)) + (portRef DIB0 (instanceRef pdp_ram_6_3_4)) + (portRef WEB (instanceRef pdp_ram_7_0_3)) + (portRef ADB2 (instanceRef pdp_ram_7_0_3)) + (portRef ADA2 (instanceRef pdp_ram_7_0_3)) + (portRef ADB1 (instanceRef pdp_ram_7_0_3)) + (portRef ADA1 (instanceRef pdp_ram_7_0_3)) + (portRef ADB0 (instanceRef pdp_ram_7_0_3)) + (portRef ADA0 (instanceRef pdp_ram_7_0_3)) + (portRef DIB17 (instanceRef pdp_ram_7_0_3)) + (portRef DIA17 (instanceRef pdp_ram_7_0_3)) + (portRef DIB16 (instanceRef pdp_ram_7_0_3)) + (portRef DIA16 (instanceRef pdp_ram_7_0_3)) + (portRef DIB15 (instanceRef pdp_ram_7_0_3)) + (portRef DIA15 (instanceRef pdp_ram_7_0_3)) + (portRef DIB14 (instanceRef pdp_ram_7_0_3)) + (portRef DIA14 (instanceRef pdp_ram_7_0_3)) + (portRef DIB13 (instanceRef pdp_ram_7_0_3)) + (portRef DIA13 (instanceRef pdp_ram_7_0_3)) + (portRef DIB12 (instanceRef pdp_ram_7_0_3)) + (portRef DIA12 (instanceRef pdp_ram_7_0_3)) + (portRef DIB11 (instanceRef pdp_ram_7_0_3)) + (portRef DIA11 (instanceRef pdp_ram_7_0_3)) + (portRef DIB10 (instanceRef pdp_ram_7_0_3)) + (portRef DIA10 (instanceRef pdp_ram_7_0_3)) + (portRef DIB9 (instanceRef pdp_ram_7_0_3)) + (portRef DIA9 (instanceRef pdp_ram_7_0_3)) + (portRef DIB8 (instanceRef pdp_ram_7_0_3)) + (portRef DIB7 (instanceRef pdp_ram_7_0_3)) + (portRef DIB6 (instanceRef pdp_ram_7_0_3)) + (portRef DIB5 (instanceRef pdp_ram_7_0_3)) + (portRef DIB4 (instanceRef pdp_ram_7_0_3)) + (portRef DIB3 (instanceRef pdp_ram_7_0_3)) + (portRef DIB2 (instanceRef pdp_ram_7_0_3)) + (portRef DIB1 (instanceRef pdp_ram_7_0_3)) + (portRef DIB0 (instanceRef pdp_ram_7_0_3)) + (portRef WEB (instanceRef pdp_ram_7_1_2)) + (portRef ADB2 (instanceRef pdp_ram_7_1_2)) + (portRef ADA2 (instanceRef pdp_ram_7_1_2)) + (portRef ADB1 (instanceRef pdp_ram_7_1_2)) + (portRef ADA1 (instanceRef pdp_ram_7_1_2)) + (portRef ADB0 (instanceRef pdp_ram_7_1_2)) + (portRef ADA0 (instanceRef pdp_ram_7_1_2)) + (portRef DIB17 (instanceRef pdp_ram_7_1_2)) + (portRef DIA17 (instanceRef pdp_ram_7_1_2)) + (portRef DIB16 (instanceRef pdp_ram_7_1_2)) + (portRef DIA16 (instanceRef pdp_ram_7_1_2)) + (portRef DIB15 (instanceRef pdp_ram_7_1_2)) + (portRef DIA15 (instanceRef pdp_ram_7_1_2)) + (portRef DIB14 (instanceRef pdp_ram_7_1_2)) + (portRef DIA14 (instanceRef pdp_ram_7_1_2)) + (portRef DIB13 (instanceRef pdp_ram_7_1_2)) + (portRef DIA13 (instanceRef pdp_ram_7_1_2)) + (portRef DIB12 (instanceRef pdp_ram_7_1_2)) + (portRef DIA12 (instanceRef pdp_ram_7_1_2)) + (portRef DIB11 (instanceRef pdp_ram_7_1_2)) + (portRef DIA11 (instanceRef pdp_ram_7_1_2)) + (portRef DIB10 (instanceRef pdp_ram_7_1_2)) + (portRef DIA10 (instanceRef pdp_ram_7_1_2)) + (portRef DIB9 (instanceRef pdp_ram_7_1_2)) + (portRef DIA9 (instanceRef pdp_ram_7_1_2)) + (portRef DIB8 (instanceRef pdp_ram_7_1_2)) + (portRef DIB7 (instanceRef pdp_ram_7_1_2)) + (portRef DIB6 (instanceRef pdp_ram_7_1_2)) + (portRef DIB5 (instanceRef pdp_ram_7_1_2)) + (portRef DIB4 (instanceRef pdp_ram_7_1_2)) + (portRef DIB3 (instanceRef pdp_ram_7_1_2)) + (portRef DIB2 (instanceRef pdp_ram_7_1_2)) + (portRef DIB1 (instanceRef pdp_ram_7_1_2)) + (portRef DIB0 (instanceRef pdp_ram_7_1_2)) + (portRef WEB (instanceRef pdp_ram_7_2_1)) + (portRef ADB2 (instanceRef pdp_ram_7_2_1)) + (portRef ADA2 (instanceRef pdp_ram_7_2_1)) + (portRef ADB1 (instanceRef pdp_ram_7_2_1)) + (portRef ADA1 (instanceRef pdp_ram_7_2_1)) + (portRef ADB0 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(portRef DIA1 (instanceRef pdp_ram_7_0_3)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DIA0 (instanceRef pdp_ram_0_0_31)) + (portRef DIA0 (instanceRef pdp_ram_1_0_27)) + (portRef DIA0 (instanceRef pdp_ram_2_0_23)) + (portRef DIA0 (instanceRef pdp_ram_3_0_19)) + (portRef DIA0 (instanceRef pdp_ram_4_0_15)) + (portRef DIA0 (instanceRef pdp_ram_5_0_11)) + (portRef DIA0 (instanceRef pdp_ram_6_0_7)) + (portRef DIA0 (instanceRef pdp_ram_7_0_3)))))))) + (design fifo_36x16k_oreg + (cellRef fifo_36x16k_oreg + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc new file mode 100644 index 0000000..0b5cbed --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x16k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:42:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=16384 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode 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z0!^nf0hQ-M)0tsX=RwmDmDKsrG)y8j6q+uMlDYtzMk%C*LDN_!pmI1g@tH#92xyuV zA@4$Hx-~%RB5110lDZh0?h28*1e)#(lDZU{=J-e{(DYb@)Me1bXVR4;q3O9Sd843d zkw$7XG)01>E{CS2K2l?#>8%KDU0I4gX>A!wbW1%Ugks1e0jX_f5p()`bH36E^ Gk^cuGae#0D literal 0 HcmV?d00001 diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd new file mode 100644 index 0000000..ab8fb13 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd @@ -0,0 +1,3166 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc + +-- Wed Mar 18 14:42:08 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_36x16k_oreg is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(13 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(14 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_36x16k_oreg; + +architecture Structure of fifo_36x16k_oreg is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal rptr_14: std_logic; + signal rptr_11_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_13_ff: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal ifcount_11: std_logic; + signal co4: std_logic; + signal ifcount_12: std_logic; + signal ifcount_13: std_logic; + signal co5: std_logic; + signal ifcount_14: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal co5_1: std_logic; + signal co6_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; + signal co5_2: std_logic; + signal fcount_12: std_logic; + signal fcount_13: std_logic; + signal co6_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_14: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4_3: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5_3: std_logic; + signal iwcount_14: std_logic; + signal co7_1: std_logic; + signal co6_3: std_logic; + signal wcount_14: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_4: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal ircount_14: std_logic; + signal co7_2: std_logic; + signal co6_4: std_logic; + signal rcount_14: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal mdout1_7_9: std_logic; + signal mdout1_6_9: std_logic; + signal mdout1_5_9: std_logic; + signal mdout1_4_9: std_logic; + signal mdout1_3_9: std_logic; + signal mdout1_2_9: std_logic; + signal mdout1_1_9: std_logic; + signal mdout1_0_9: std_logic; + signal mdout1_7_10: std_logic; + signal mdout1_6_10: std_logic; + signal mdout1_5_10: std_logic; + signal mdout1_4_10: std_logic; + signal mdout1_3_10: std_logic; + signal mdout1_2_10: std_logic; + signal mdout1_1_10: std_logic; + signal mdout1_0_10: std_logic; + signal mdout1_7_11: std_logic; + signal mdout1_6_11: std_logic; + signal mdout1_5_11: std_logic; + signal mdout1_4_11: std_logic; + signal mdout1_3_11: std_logic; + signal mdout1_2_11: std_logic; + signal mdout1_1_11: std_logic; + signal mdout1_0_11: std_logic; + signal mdout1_7_12: std_logic; + signal mdout1_6_12: std_logic; + signal mdout1_5_12: std_logic; + signal mdout1_4_12: std_logic; + signal mdout1_3_12: std_logic; + signal mdout1_2_12: std_logic; + signal mdout1_1_12: std_logic; + signal mdout1_0_12: std_logic; + signal mdout1_7_13: std_logic; + signal mdout1_6_13: std_logic; + signal mdout1_5_13: std_logic; + signal mdout1_4_13: std_logic; + signal mdout1_3_13: std_logic; + signal mdout1_2_13: std_logic; + signal mdout1_1_13: std_logic; + signal mdout1_0_13: std_logic; + signal mdout1_7_14: std_logic; + signal mdout1_6_14: std_logic; + signal mdout1_5_14: std_logic; + signal mdout1_4_14: std_logic; + signal mdout1_3_14: std_logic; + signal mdout1_2_14: std_logic; + signal mdout1_1_14: std_logic; + signal mdout1_0_14: std_logic; + signal mdout1_7_15: std_logic; + signal mdout1_6_15: std_logic; + signal mdout1_5_15: std_logic; + signal mdout1_4_15: std_logic; + signal mdout1_3_15: std_logic; + signal mdout1_2_15: std_logic; + signal mdout1_1_15: std_logic; + signal mdout1_0_15: std_logic; + signal mdout1_7_16: std_logic; + signal mdout1_6_16: std_logic; + signal mdout1_5_16: std_logic; + signal mdout1_4_16: std_logic; + signal mdout1_3_16: std_logic; + signal mdout1_2_16: std_logic; + signal mdout1_1_16: std_logic; + signal mdout1_0_16: std_logic; + signal mdout1_7_17: std_logic; + signal mdout1_6_17: std_logic; + signal mdout1_5_17: std_logic; + signal mdout1_4_17: std_logic; + signal mdout1_3_17: std_logic; + signal mdout1_2_17: std_logic; + signal mdout1_1_17: std_logic; + signal mdout1_0_17: std_logic; + signal mdout1_7_18: std_logic; + signal mdout1_6_18: std_logic; + signal mdout1_5_18: std_logic; + signal mdout1_4_18: std_logic; + signal mdout1_3_18: std_logic; + signal mdout1_2_18: std_logic; + signal mdout1_1_18: std_logic; + signal mdout1_0_18: std_logic; + signal mdout1_7_19: std_logic; + signal mdout1_6_19: std_logic; + signal mdout1_5_19: std_logic; + signal mdout1_4_19: std_logic; + signal mdout1_3_19: std_logic; + signal mdout1_2_19: std_logic; + signal mdout1_1_19: std_logic; + signal mdout1_0_19: std_logic; + signal mdout1_7_20: std_logic; + signal mdout1_6_20: std_logic; + signal mdout1_5_20: std_logic; + signal mdout1_4_20: std_logic; + signal mdout1_3_20: std_logic; + signal mdout1_2_20: std_logic; + signal mdout1_1_20: std_logic; + signal mdout1_0_20: std_logic; + signal mdout1_7_21: std_logic; + signal mdout1_6_21: std_logic; + signal mdout1_5_21: std_logic; + signal mdout1_4_21: std_logic; + signal mdout1_3_21: std_logic; + signal mdout1_2_21: std_logic; + signal mdout1_1_21: std_logic; + signal mdout1_0_21: std_logic; + signal mdout1_7_22: std_logic; + signal mdout1_6_22: std_logic; + signal mdout1_5_22: std_logic; + signal mdout1_4_22: std_logic; + signal mdout1_3_22: std_logic; + signal mdout1_2_22: std_logic; + signal mdout1_1_22: std_logic; + signal mdout1_0_22: std_logic; + signal mdout1_7_23: std_logic; + signal mdout1_6_23: std_logic; + signal mdout1_5_23: std_logic; + signal mdout1_4_23: std_logic; + signal mdout1_3_23: std_logic; + signal mdout1_2_23: std_logic; + signal mdout1_1_23: std_logic; + signal mdout1_0_23: std_logic; + signal mdout1_7_24: std_logic; + signal mdout1_6_24: std_logic; + signal mdout1_5_24: std_logic; + signal mdout1_4_24: std_logic; + signal mdout1_3_24: std_logic; + signal mdout1_2_24: std_logic; + signal mdout1_1_24: std_logic; + signal mdout1_0_24: std_logic; + signal mdout1_7_25: std_logic; + signal mdout1_6_25: std_logic; + signal mdout1_5_25: std_logic; + signal mdout1_4_25: std_logic; + signal mdout1_3_25: std_logic; + signal mdout1_2_25: std_logic; + signal mdout1_1_25: std_logic; + signal mdout1_0_25: std_logic; + signal mdout1_7_26: std_logic; + signal mdout1_6_26: std_logic; + signal mdout1_5_26: std_logic; + signal mdout1_4_26: std_logic; + signal mdout1_3_26: std_logic; + signal mdout1_2_26: std_logic; + signal mdout1_1_26: std_logic; + signal mdout1_0_26: std_logic; + signal mdout1_7_27: std_logic; + signal mdout1_6_27: std_logic; + signal mdout1_5_27: std_logic; + signal mdout1_4_27: std_logic; + signal mdout1_3_27: std_logic; + signal mdout1_2_27: std_logic; + signal mdout1_1_27: std_logic; + signal mdout1_0_27: std_logic; + signal mdout1_7_28: std_logic; + signal mdout1_6_28: std_logic; + signal mdout1_5_28: std_logic; + signal mdout1_4_28: std_logic; + signal mdout1_3_28: std_logic; + signal mdout1_2_28: std_logic; + signal mdout1_1_28: std_logic; + signal mdout1_0_28: std_logic; + signal mdout1_7_29: std_logic; + signal mdout1_6_29: std_logic; + signal mdout1_5_29: std_logic; + signal mdout1_4_29: std_logic; + signal mdout1_3_29: std_logic; + signal mdout1_2_29: std_logic; + signal mdout1_1_29: std_logic; + signal mdout1_0_29: std_logic; + signal mdout1_7_30: std_logic; + signal mdout1_6_30: std_logic; + signal mdout1_5_30: std_logic; + signal mdout1_4_30: std_logic; + signal mdout1_3_30: std_logic; + signal mdout1_2_30: std_logic; + signal mdout1_1_30: std_logic; + signal mdout1_0_30: std_logic; + signal mdout1_7_31: std_logic; + signal mdout1_6_31: std_logic; + signal mdout1_5_31: std_logic; + signal mdout1_4_31: std_logic; + signal mdout1_3_31: std_logic; + signal mdout1_2_31: std_logic; + signal mdout1_1_31: std_logic; + signal mdout1_0_31: std_logic; + signal mdout1_7_32: std_logic; + signal mdout1_6_32: std_logic; + signal mdout1_5_32: std_logic; + signal mdout1_4_32: std_logic; + signal mdout1_3_32: std_logic; + signal mdout1_2_32: std_logic; + signal mdout1_1_32: std_logic; + signal mdout1_0_32: std_logic; + signal mdout1_7_33: std_logic; + signal mdout1_6_33: std_logic; + signal mdout1_5_33: std_logic; + signal mdout1_4_33: std_logic; + signal mdout1_3_33: std_logic; + signal mdout1_2_33: std_logic; + signal mdout1_1_33: std_logic; + signal mdout1_0_33: std_logic; + signal mdout1_7_34: std_logic; + signal mdout1_6_34: std_logic; + signal mdout1_5_34: std_logic; + signal mdout1_4_34: std_logic; + signal mdout1_3_34: std_logic; + signal mdout1_2_34: std_logic; + signal mdout1_1_34: std_logic; + signal mdout1_0_34: std_logic; + signal rptr_13_ff2: std_logic; + signal rptr_12_ff2: std_logic; + signal rptr_11_ff2: std_logic; + signal mdout1_7_35: std_logic; + signal mdout1_6_35: std_logic; + signal mdout1_5_35: std_logic; + signal mdout1_4_35: std_logic; + signal mdout1_3_35: std_logic; + signal mdout1_2_35: std_logic; + signal mdout1_1_35: std_logic; + signal mdout1_0_35: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal rptr_6: std_logic; + signal rptr_5: std_logic; + signal wcount_6: std_logic; + signal wcount_5: std_logic; + signal co2_5: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal rptr_8: std_logic; + signal rptr_7: std_logic; + signal wcount_8: std_logic; + signal wcount_7: std_logic; + signal co3_5: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal rptr_10: std_logic; + signal rptr_9: std_logic; + signal wcount_10: std_logic; + signal wcount_9: std_logic; + signal co4_5: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal wcount_12: std_logic; + signal wcount_11: std_logic; + signal co5_5: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_14: std_logic; + signal rptr_13: std_logic; + signal wcnt_sub_msb: std_logic; + signal wcount_13: std_logic; + signal co6_5: std_logic; + signal co7_3d: std_logic; + signal co7_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_6: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_6: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal co6_6: std_logic; + signal wcnt_reg_14: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_0_27 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_27 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_1_26 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_26 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_2_25 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_25 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_3_24 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_24 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_0_23 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_23 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_1_22 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_22 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_2_21 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_21 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_3_20 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_20 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_0_19 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_19 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_1_18 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_18 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_2_17 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_17 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_3_16 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_16 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_0_15 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_15 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_1_14 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_1_14 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_2_13 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_2_13 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_3_12 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_3_12 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_0_11 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_11 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_1_10 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_1_10 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_2_9 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_2_9 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_3_8 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_3_8 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_0_7 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_7 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_1_6 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_1_6 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_2_5 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_2_5 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_3_4 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_3_4 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_0_3 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_3 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_1_2 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_1_2 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_2_1 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_2_1 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_3_0 : label is "fifo_36x16k_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_3_0 : label is ""; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_14, B=>rptr_14, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_31: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, + DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, + DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, DOB0=>mdout1_0_0); + + pdp_ram_0_1_30: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, + DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, + DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, + DOB1=>mdout1_0_10, DOB0=>mdout1_0_9); + + pdp_ram_0_2_29: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, + DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, + DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, + DOB1=>mdout1_0_19, DOB0=>mdout1_0_18); + + pdp_ram_0_3_28: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, + DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, + DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, + DOB1=>mdout1_0_28, DOB0=>mdout1_0_27); + + pdp_ram_1_0_27: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, + DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, + DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, DOB0=>mdout1_1_0); + + pdp_ram_1_1_26: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, + DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, + DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, + DOB1=>mdout1_1_10, DOB0=>mdout1_1_9); + + pdp_ram_1_2_25: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, + DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, + DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, + DOB1=>mdout1_1_19, DOB0=>mdout1_1_18); + + pdp_ram_1_3_24: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, + DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, + DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, + DOB1=>mdout1_1_28, DOB0=>mdout1_1_27); + + pdp_ram_2_0_23: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_2_8, DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, + DOB5=>mdout1_2_5, DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, + DOB2=>mdout1_2_2, DOB1=>mdout1_2_1, DOB0=>mdout1_2_0); + + pdp_ram_2_1_22: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, + DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, + DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, + DOB1=>mdout1_2_10, DOB0=>mdout1_2_9); + + pdp_ram_2_2_21: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, + DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, + DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, + DOB1=>mdout1_2_19, DOB0=>mdout1_2_18); + + pdp_ram_2_3_20: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, + DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, + DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, + DOB1=>mdout1_2_28, DOB0=>mdout1_2_27); + + pdp_ram_3_0_19: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_3_8, DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, + DOB5=>mdout1_3_5, DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, + DOB2=>mdout1_3_2, DOB1=>mdout1_3_1, DOB0=>mdout1_3_0); + + pdp_ram_3_1_18: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, + DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, + DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, + DOB1=>mdout1_3_10, DOB0=>mdout1_3_9); + + pdp_ram_3_2_17: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, + DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, + DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, + DOB1=>mdout1_3_19, DOB0=>mdout1_3_18); + + pdp_ram_3_3_16: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, + DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, + DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, + DOB1=>mdout1_3_28, DOB0=>mdout1_3_27); + + pdp_ram_4_0_15: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_4_8, DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, + DOB5=>mdout1_4_5, DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, + DOB2=>mdout1_4_2, DOB1=>mdout1_4_1, DOB0=>mdout1_4_0); + + pdp_ram_4_1_14: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_17, + DOB7=>mdout1_4_16, DOB6=>mdout1_4_15, DOB5=>mdout1_4_14, + DOB4=>mdout1_4_13, DOB3=>mdout1_4_12, DOB2=>mdout1_4_11, + DOB1=>mdout1_4_10, DOB0=>mdout1_4_9); + + pdp_ram_4_2_13: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_26, + DOB7=>mdout1_4_25, DOB6=>mdout1_4_24, DOB5=>mdout1_4_23, + DOB4=>mdout1_4_22, DOB3=>mdout1_4_21, DOB2=>mdout1_4_20, + DOB1=>mdout1_4_19, DOB0=>mdout1_4_18); + + pdp_ram_4_3_12: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_35, + DOB7=>mdout1_4_34, DOB6=>mdout1_4_33, DOB5=>mdout1_4_32, + DOB4=>mdout1_4_31, DOB3=>mdout1_4_30, DOB2=>mdout1_4_29, + DOB1=>mdout1_4_28, DOB0=>mdout1_4_27); + + pdp_ram_5_0_11: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_5_8, DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, + DOB5=>mdout1_5_5, DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, + DOB2=>mdout1_5_2, DOB1=>mdout1_5_1, DOB0=>mdout1_5_0); + + pdp_ram_5_1_10: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_17, + DOB7=>mdout1_5_16, DOB6=>mdout1_5_15, DOB5=>mdout1_5_14, + DOB4=>mdout1_5_13, DOB3=>mdout1_5_12, DOB2=>mdout1_5_11, + DOB1=>mdout1_5_10, DOB0=>mdout1_5_9); + + pdp_ram_5_2_9: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_26, + DOB7=>mdout1_5_25, DOB6=>mdout1_5_24, DOB5=>mdout1_5_23, + DOB4=>mdout1_5_22, DOB3=>mdout1_5_21, DOB2=>mdout1_5_20, + DOB1=>mdout1_5_19, DOB0=>mdout1_5_18); + + pdp_ram_5_3_8: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_35, + DOB7=>mdout1_5_34, DOB6=>mdout1_5_33, DOB5=>mdout1_5_32, + DOB4=>mdout1_5_31, DOB3=>mdout1_5_30, DOB2=>mdout1_5_29, + DOB1=>mdout1_5_28, DOB0=>mdout1_5_27); + + pdp_ram_6_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_6_8, DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, + DOB5=>mdout1_6_5, DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, + DOB2=>mdout1_6_2, DOB1=>mdout1_6_1, DOB0=>mdout1_6_0); + + pdp_ram_6_1_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_17, + DOB7=>mdout1_6_16, DOB6=>mdout1_6_15, DOB5=>mdout1_6_14, + DOB4=>mdout1_6_13, DOB3=>mdout1_6_12, DOB2=>mdout1_6_11, + DOB1=>mdout1_6_10, DOB0=>mdout1_6_9); + + pdp_ram_6_2_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_26, + DOB7=>mdout1_6_25, DOB6=>mdout1_6_24, DOB5=>mdout1_6_23, + DOB4=>mdout1_6_22, DOB3=>mdout1_6_21, DOB2=>mdout1_6_20, + DOB1=>mdout1_6_19, DOB0=>mdout1_6_18); + + pdp_ram_6_3_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_35, + DOB7=>mdout1_6_34, DOB6=>mdout1_6_33, DOB5=>mdout1_6_32, + DOB4=>mdout1_6_31, DOB3=>mdout1_6_30, DOB2=>mdout1_6_29, + DOB1=>mdout1_6_28, DOB0=>mdout1_6_27); + + pdp_ram_7_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>wptr_13, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB2=>rptr_13, + CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>open, + DOA12=>open, DOA11=>open, DOA10=>open, DOA9=>open, + DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open, + DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>mdout1_7_8, DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, + DOB5=>mdout1_7_5, DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, + DOB2=>mdout1_7_2, DOB1=>mdout1_7_1, DOB0=>mdout1_7_0); + + pdp_ram_7_1_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_17, + DOB7=>mdout1_7_16, DOB6=>mdout1_7_15, DOB5=>mdout1_7_14, + DOB4=>mdout1_7_13, DOB3=>mdout1_7_12, DOB2=>mdout1_7_11, + DOB1=>mdout1_7_10, DOB0=>mdout1_7_9); + + pdp_ram_7_2_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_26, + DOB7=>mdout1_7_25, DOB6=>mdout1_7_24, DOB5=>mdout1_7_23, + DOB4=>mdout1_7_22, DOB3=>mdout1_7_21, DOB2=>mdout1_7_20, + DOB1=>mdout1_7_19, DOB0=>mdout1_7_18); + + pdp_ram_7_3_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>wptr_13, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, CSB0=>rptr_11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_35, + DOB7=>mdout1_7_34, DOB6=>mdout1_7_33, DOB5=>mdout1_7_32, + DOB4=>mdout1_7_31, DOB3=>mdout1_7_30, DOB2=>mdout1_7_29, + DOB1=>mdout1_7_28, DOB0=>mdout1_7_27); + + FF_98: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_97: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_96: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_95: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_94: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_93: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_92: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_91: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_90: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_89: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_88: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_87: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_86: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_85: FD1P3DX + port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_13); + + FF_84: FD1P3DX + port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_14); + + FF_83: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_82: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_81: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_80: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_79: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_78: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_77: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_76: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_75: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_74: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_73: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_72: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_71: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_70: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_69: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_68: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_13); + + FF_67: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_14); + + FF_66: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_65: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_64: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_63: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_62: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_61: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_60: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_59: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_58: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_57: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_56: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_55: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_54: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_53: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_13); + + FF_52: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_14); + + FF_51: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_50: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_49: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_48: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_47: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_46: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_45: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_44: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_43: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_42: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_41: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_40: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_39: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_12); + + FF_38: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_13); + + FF_37: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_14); + + FF_36: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_35: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_34: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_33: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_32: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_31: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_30: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_29: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_28: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_27: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_26: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_25: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_24: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_12); + + FF_23: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_13); + + FF_22: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_14); + + FF_21: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_20: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_19: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_18: FD1P3DX + port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff2); + + FF_17: FD1P3DX + port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff2); + + FF_16: FD1P3DX + port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_13_ff2); + + FF_15: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_14: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_13: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + bdcnt_bctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6); + + bdcnt_bctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co6, S0=>ifcount_14, S1=>open, COUT=>co7); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1); + + e_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, + B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, COUT=>co6_1); + + e_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_14, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2); + + g_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_2, S0=>open, S1=>open, COUT=>co6_2); + + g_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_3); + + w_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6_3); + + w_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_14, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>iwcount_14, S1=>open, + COUT=>co7_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_4); + + r_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_4); + + r_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_14, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_4, S0=>ircount_14, S1=>open, + COUT=>co7_2); + + mux_35: MUX81 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(0)); + + mux_34: MUX81 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(1)); + + mux_33: MUX81 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(2)); + + mux_32: MUX81 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(3)); + + mux_31: MUX81 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(4)); + + mux_30: MUX81 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(5)); + + mux_29: MUX81 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(6)); + + mux_28: MUX81 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(7)); + + mux_27: MUX81 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(8)); + + mux_26: MUX81 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, + D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, + D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(9)); + + mux_25: MUX81 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, + D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, + D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(10)); + + mux_24: MUX81 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, + D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, + D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(11)); + + mux_23: MUX81 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, + D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, + D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(12)); + + mux_22: MUX81 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, + D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, + D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(13)); + + mux_21: MUX81 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, + D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, + D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(14)); + + mux_20: MUX81 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, + D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, + D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(15)); + + mux_19: MUX81 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, + D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, + D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(16)); + + mux_18: MUX81 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, + D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, + D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(17)); + + mux_17: MUX81 + port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, + D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18, + D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(18)); + + mux_16: MUX81 + port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, + D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19, + D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(19)); + + mux_15: MUX81 + port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, + D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20, + D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(20)); + + mux_14: MUX81 + port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, + D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21, + D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(21)); + + mux_13: MUX81 + port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, + D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22, + D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(22)); + + mux_12: MUX81 + port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, + D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23, + D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(23)); + + mux_11: MUX81 + port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, + D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24, + D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(24)); + + mux_10: MUX81 + port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, + D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25, + D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(25)); + + mux_9: MUX81 + port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, + D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26, + D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(26)); + + mux_8: MUX81 + port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, + D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27, + D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(27)); + + mux_7: MUX81 + port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, + D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28, + D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(28)); + + mux_6: MUX81 + port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, + D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29, + D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(29)); + + mux_5: MUX81 + port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, + D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30, + D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(30)); + + mux_4: MUX81 + port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, + D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31, + D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(31)); + + mux_3: MUX81 + port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, + D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32, + D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(32)); + + mux_2: MUX81 + port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, + D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33, + D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(33)); + + mux_1: MUX81 + port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, + D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34, + D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(34)); + + mux_0: MUX81 + port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, + D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35, + D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff2, + SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(35)); + + precin_inst636: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_5); + + wcnt_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_13, A1=>wcnt_sub_msb, B0=>rptr_13, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_5, S0=>wcnt_sub_13, S1=>wcnt_sub_14, + COUT=>co7_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_3, S0=>co7_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>co5_6); + + af_set_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, + COUT=>co6_6); + + af_set_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_14, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + WCNT(13) <= fcount_13; + WCNT(14) <= fcount_14; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst new file mode 100644 index 0000000..e2ce71a --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:40:46 + diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn new file mode 100644 index 0000000..a1e46fb --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn @@ -0,0 +1,3251 @@ +(edif fifo_36x1k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 40 48) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell fifo_36x1k_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(9:0)") 10) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(10:0)") 11) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_1 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x1k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "18")) + (property DATA_WIDTH_A + (string "18"))) + (instance pdp_ram_0_1_0 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x1k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "18")) + (property DATA_WIDTH_A + (string "18"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string 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(member Data 31)) + (portRef DIA4 (instanceRef pdp_ram_0_0_1)))) + (net datain3 + (joined + (portRef (member Data 32)) + (portRef DIA3 (instanceRef pdp_ram_0_0_1)))) + (net datain2 + (joined + (portRef (member Data 33)) + (portRef DIA2 (instanceRef pdp_ram_0_0_1)))) + (net datain1 + (joined + (portRef (member Data 34)) + (portRef DIA1 (instanceRef pdp_ram_0_0_1)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DIA0 (instanceRef pdp_ram_0_0_1)))))))) + (design fifo_36x1k_oreg + (cellRef fifo_36x1k_oreg + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc new file mode 100644 index 0000000..2dc804f --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x1k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:40:46 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode 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zti&{7Js08Bay(ni0{)2EdNIdhrLbO=*Z^U@Cb24EySLVxV_`MvES(`NE5g#5!pchQEMfgkVrL6$BPWJ*VZEPYv07Lknk)?w z)@F&-2y2VPh6*d62Gc1di6uy#vqq_Dotaq1{x3zMbM!Y(}g zJVw}E493O^yIYKg=d!o+b#loH@JKG##Ul3+&uCOo4 zvvdij8a0;Y3469ooiFUUGWAkn&rfse0{nAEoTY`rUY25Mk+4@JSXwOXl@f~!+mP60 z!d|6u>Jnk!oM!2AVc!~OX{oSpkFs=yuN@XP7sL zvUHoUH)<^XT-ck!EZr{bk5Vipg#Af^r8|VZRi@sFg&`VacZp1=G)s4jOjjx0BQiZw zjNL0T;RH+fiOhi#`-RB#me~Cw(Pw{qrm(Mdsu*OOJ|-Cb3_MOr^vg6PbZ2PJLWt1}9khwaA z_6xK0g2)~zr58o^=rm(5iR^I+mR=Uw6QeA>BC;n*-m4;es+3HTEl+dmYa%-!!P4s@ zds>vGKZ@)qDZL@GW2N*bk&T8q_0J+ZG0oDOB0D9)(pw@sP4fPNxAqx~y^VME=`8&f zZ|Gwo^j{)7$7Jyxyp7LbX+7S-C#CPe{q z@6pp4YsB00SO_(V>_kZM+MQg-}Lh6DEsUk-f`csRd(t zDZMAM_v?)P4Yx@wgmNPLu*u@zap!5Uv{7Uqm(o8(_6eP__i?MwLTHo7t}|KuKxEfT z>_d@#S4tm=Y`skVSY)?LY_rJjkk}_8`<21qry~1}l(vYLkj~gv(b9p1&_6{>CzHjz zXenH0wuzQ*24kOzmcn)BbJ5b1q0kqi?C55iEpu ziIyWx7QYfL#~3VqEn1G3(r&y*S!e7UygiwP(6^%HRFlQ;@TO#gB#aWrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, + ADB10=>rptr_6, ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, + ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), + DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), + DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), + DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), + DOB0=>Q(0)); + + pdp_ram_0_1_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(35), DIA16=>Data(34), DIA15=>Data(33), + DIA14=>Data(32), DIA13=>Data(31), DIA12=>Data(30), + DIA11=>Data(29), DIA10=>Data(28), DIA9=>Data(27), + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, ADA10=>wptr_6, + ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, ADA6=>wptr_2, + ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, ADA2=>scuba_vlo, + ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, ADB10=>rptr_6, + ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, ADB6=>rptr_2, + ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(35), DOB16=>Q(34), DOB15=>Q(33), + DOB14=>Q(32), DOB13=>Q(31), DOB12=>Q(30), DOB11=>Q(29), + DOB10=>Q(28), DOB9=>Q(27), DOB8=>Q(26), DOB7=>Q(25), + DOB6=>Q(24), DOB5=>Q(23), DOB4=>Q(22), DOB3=>Q(21), + DOB2=>Q(20), DOB1=>Q(19), DOB0=>Q(18)); + + FF_68: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_67: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_66: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_65: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_64: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_63: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_62: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_61: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_60: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_59: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_58: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_57: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_56: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_55: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_54: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_53: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_52: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_51: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_50: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_49: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_48: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_47: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_46: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_45: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_44: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_43: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_42: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_41: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_40: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_39: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_38: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_37: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_36: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_35: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_34: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_33: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_32: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_31: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_30: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_29: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_28: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_27: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_26: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_25: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_24: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_23: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_22: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_21: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_20: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_19: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_18: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_17: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_16: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_15: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_14: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_13: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_12: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>open, COUT=>co5); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>open, + COUT=>co5_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>open, + COUT=>co5_2); + + precin_inst288: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcnt_sub_msb, B0=>rptr_9, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, + COUT=>co5_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>co5_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst new file mode 100644 index 0000000..644f757 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:41:09 + diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn new file mode 100644 index 0000000..7dc903a --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn @@ -0,0 +1,3557 @@ +(edif fifo_36x2k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 41 11) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell fifo_36x2k_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(10:0)") 11) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(11:0)") 12) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_3 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x2k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_1_2 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x2k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_2_1 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x2k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_3_0 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x2k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_74 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_73 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_72 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_71 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_70 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_69 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + 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b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x2k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:41:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable 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zMSPsZZV~Yb61!EzCnh=dHW8nqv-DdLpH^b&b`hT`v1KAYOJd7Kd~T6bSBUt$JWDG@ z{L~yvcZm2xiQOsUXG-iY5nq(y)Vnb~pJwSEOe^Rt&(hN(u~PD$5sAFT*s~&Wzsb^bBJrTX((@wmkj>HtkyvA~^nyq{ zCZ!ieVy($oQ6$zGEWIQWPuVQJEE3OHEWIKU&r9i5{LOKbvDZZ6WrL;HMdDSPr8h+4 z4U45WMPj3r-V%v-O~y8ggl(|&wn%(nv-FNgd}Oiou1I_;rT0W)lgZfoBJrick}VP? zo25U9#Mc%}ABe2smSY?d|&Jz=r*C!y~kr7tjHU^4cl(04Uh`m@k?vso$$J!P`=mC*Z3=`Z+BpuyPJ zLO)5i+c!d=Birq-LO(glshfrF^r62A{j?Hee;4}cGRGF7pCxnrL+Izo9RC#hc~bgT z=;xO>$A1a^qC89g!rueWu=E}N3OMsHg4ALm0lN|f432>q%&OPz&&ZHA?4pn zNnS$e4@*fG`XePy{ejRQ&$G0H(4WY#w4>0Ul)RmU{WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>Q(8), DOB7=>Q(7), + DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), + DOB1=>Q(1), DOB0=>Q(0)); + + pdp_ram_0_1_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>Q(17), DOB7=>Q(16), + DOB6=>Q(15), DOB5=>Q(14), DOB4=>Q(13), DOB3=>Q(12), + DOB2=>Q(11), DOB1=>Q(10), DOB0=>Q(9)); + + pdp_ram_0_2_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>Q(26), DOB7=>Q(25), + DOB6=>Q(24), DOB5=>Q(23), DOB4=>Q(22), DOB3=>Q(21), + DOB2=>Q(20), DOB1=>Q(19), DOB0=>Q(18)); + + pdp_ram_0_3_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>Q(35), DOB7=>Q(34), + DOB6=>Q(33), DOB5=>Q(32), DOB4=>Q(31), DOB3=>Q(30), + DOB2=>Q(29), DOB1=>Q(28), DOB0=>Q(27)); + + FF_74: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_73: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_72: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_71: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_70: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_69: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_68: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_67: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_66: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_65: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_64: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_63: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_62: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_61: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_60: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_59: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_58: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_57: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_56: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_55: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_54: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_53: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_52: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_51: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_50: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_49: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_48: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_47: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_46: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_45: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_44: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_43: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_42: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_41: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_40: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_39: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_38: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_37: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_36: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_35: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_34: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_33: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_32: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_31: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_30: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_29: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_28: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_27: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_26: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_25: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_24: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_23: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_22: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_21: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_20: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_19: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_18: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_17: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_16: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_15: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_14: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_13: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, + B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_2); + + precin_inst299: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_3); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>wcnt_sub_11, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst new file mode 100644 index 0000000..318c0e9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:42:29 + diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn new file mode 100644 index 0000000..c7477aa --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn @@ -0,0 +1,15178 @@ +(edif fifo_36x32k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 42 30) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell MUX161 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port D2 + (direction INPUT)) + (port D3 + (direction INPUT)) + (port D4 + (direction INPUT)) + (port D5 + (direction INPUT)) + (port D6 + (direction INPUT)) + (port D7 + (direction INPUT)) + (port D8 + (direction INPUT)) + (port D9 + (direction INPUT)) + (port D10 + (direction INPUT)) + (port D11 + (direction INPUT)) + (port D12 + (direction INPUT)) + (port D13 + (direction INPUT)) + (port D14 + (direction INPUT)) + (port D15 + (direction INPUT)) + (port SD1 + (direction INPUT)) + (port SD2 + (direction INPUT)) + (port SD3 + (direction INPUT)) + (port SD4 + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell fifo_36x32k_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(14:0)") 15) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(15:0)") 16) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_13 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_12 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_11 + (viewRef view1 + (cellRef INV))) + (instance INV_10 + (viewRef view1 + (cellRef INV))) + (instance LUT4_129 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_128 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance INV_9 + (viewRef view1 + (cellRef INV))) + (instance INV_8 + (viewRef view1 + (cellRef INV))) + (instance INV_7 + (viewRef view1 + (cellRef INV))) + (instance INV_6 + (viewRef view1 + (cellRef INV))) + (instance LUT4_127 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_126 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_125 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_124 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_123 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_122 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_121 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_120 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_119 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_118 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_117 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_116 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_115 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_114 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_113 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_112 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_111 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_110 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_109 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_108 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_107 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_106 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_105 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_104 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_103 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_102 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_101 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_100 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_99 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_98 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_97 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_96 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_95 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_94 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_93 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_92 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_91 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_90 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_89 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_88 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_87 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_86 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_85 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_84 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_83 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_82 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_81 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_80 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_79 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_78 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_77 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_76 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_75 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_74 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_73 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_72 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_71 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_70 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_69 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_68 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_67 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_66 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_65 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_64 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_63 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_62 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_61 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_60 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_59 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_58 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_57 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_56 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_55 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_54 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_53 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_52 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_51 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_50 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_49 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_48 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_47 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_46 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_45 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_44 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_43 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_42 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_41 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_40 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_39 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_38 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_37 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_36 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_35 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_34 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_33 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_32 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_31 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_30 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_29 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_28 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_27 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_26 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_25 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_24 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_23 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_22 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_21 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_20 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_19 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_18 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_17 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_16 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_15 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_14 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_13 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_12 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_11 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_10 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_9 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_8 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_7 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_6 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_5 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_4 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_3 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_2 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x8000"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_63 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_1_62 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_2_61 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_3_60 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_0_59 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_1_58 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_2_57 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_3_56 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_0_55 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_1_54 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_2_53 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_3_52 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_0_51 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_1_50 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_2_49 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_3_48 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_0_47 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_1_46 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_2_45 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_4_3_44 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_0_43 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_1_42 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_2_41 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_5_3_40 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_0_39 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_1_38 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_2_37 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_6_3_36 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_0_35 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_1_34 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_2_33 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_7_3_32 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_0_31 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_1_30 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_2_29 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_8_3_28 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_0_27 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_1_26 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_2_25 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_9_3_24 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_0_23 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_1_22 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_2_21 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_10_3_20 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_0_19 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_1_18 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_2_17 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_11_3_16 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_0_15 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_1_14 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_2_13 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_12_3_12 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_0_11 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_1_10 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_2_9 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_13_3_8 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_0_7 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_1_6 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_2_5 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_14_3_4 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_0_3 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_1_2 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_2_1 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_15_3_0 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x32k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_106 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_105 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_104 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_103 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_102 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_101 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_100 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_99 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_98 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_97 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_96 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_95 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_94 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_93 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_92 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_91 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_90 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_89 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_88 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_87 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_86 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_85 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_84 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_83 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_82 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_81 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_80 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_79 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_78 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_77 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_76 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_75 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_74 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_73 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_72 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_71 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_70 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_69 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_4 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_3 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_2 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_1 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_0 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance bdcnt_bctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance bdcnt_bctr_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance bdcnt_bctr_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_ci_a + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance e_cmp_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance e_cmp_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance a0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance g_cmp_ci_a + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance g_cmp_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance g_cmp_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance a1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance w_ctr_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_cia + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_3 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_4 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_5 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_6 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance r_ctr_7 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + 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(property INIT0 + (string "0x99AA"))) + (instance wcnt_8 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance af_set_cmp_ci_a + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x66AA")) + (property INIT0 + (string "0x66AA"))) + (instance af_set_cmp_0 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance af_set_cmp_1 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string "NO")) + (property INJECT1_0 + (string "NO")) + (property INIT1 + (string "0x99AA")) + (property INIT0 + (string "0x99AA"))) + (instance af_set_cmp_2 + (viewRef view1 + (cellRef CCU2C)) + (property INJECT1_1 + (string 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ADA6 (instanceRef pdp_ram_0_0_63)) + (portRef ADA6 (instanceRef pdp_ram_0_1_62)) + (portRef ADA6 (instanceRef pdp_ram_0_2_61)) + (portRef ADA6 (instanceRef pdp_ram_0_3_60)) + (portRef ADA6 (instanceRef pdp_ram_1_0_59)) + (portRef ADA6 (instanceRef pdp_ram_1_1_58)) + (portRef ADA6 (instanceRef pdp_ram_1_2_57)) + (portRef ADA6 (instanceRef pdp_ram_1_3_56)) + (portRef ADA6 (instanceRef pdp_ram_2_0_55)) + (portRef ADA6 (instanceRef pdp_ram_2_1_54)) + (portRef ADA6 (instanceRef pdp_ram_2_2_53)) + (portRef ADA6 (instanceRef pdp_ram_2_3_52)) + (portRef ADA6 (instanceRef pdp_ram_3_0_51)) + (portRef ADA6 (instanceRef pdp_ram_3_1_50)) + (portRef ADA6 (instanceRef pdp_ram_3_2_49)) + (portRef ADA6 (instanceRef pdp_ram_3_3_48)) + (portRef ADA6 (instanceRef pdp_ram_4_0_47)) + (portRef ADA6 (instanceRef pdp_ram_4_1_46)) + (portRef ADA6 (instanceRef pdp_ram_4_2_45)) + (portRef ADA6 (instanceRef pdp_ram_4_3_44)) + (portRef ADA6 (instanceRef pdp_ram_5_0_43)) + (portRef ADA6 (instanceRef pdp_ram_5_1_42)) + (portRef ADA6 (instanceRef pdp_ram_5_2_41)) + (portRef ADA6 (instanceRef pdp_ram_5_3_40)) + (portRef ADA6 (instanceRef pdp_ram_6_0_39)) + (portRef ADA6 (instanceRef pdp_ram_6_1_38)) + (portRef ADA6 (instanceRef pdp_ram_6_2_37)) + (portRef ADA6 (instanceRef pdp_ram_6_3_36)) + (portRef ADA6 (instanceRef pdp_ram_7_0_35)) + (portRef ADA6 (instanceRef pdp_ram_7_1_34)) + (portRef ADA6 (instanceRef pdp_ram_7_2_33)) + (portRef ADA6 (instanceRef pdp_ram_7_3_32)) + (portRef ADA6 (instanceRef pdp_ram_8_0_31)) + (portRef ADA6 (instanceRef pdp_ram_8_1_30)) + (portRef ADA6 (instanceRef pdp_ram_8_2_29)) + (portRef ADA6 (instanceRef pdp_ram_8_3_28)) + (portRef ADA6 (instanceRef pdp_ram_9_0_27)) + (portRef ADA6 (instanceRef pdp_ram_9_1_26)) + (portRef ADA6 (instanceRef pdp_ram_9_2_25)) + (portRef ADA6 (instanceRef pdp_ram_9_3_24)) + (portRef ADA6 (instanceRef pdp_ram_10_0_23)) + (portRef ADA6 (instanceRef pdp_ram_10_1_22)) + (portRef ADA6 (instanceRef pdp_ram_10_2_21)) + (portRef ADA6 (instanceRef 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(portRef ADA7 (instanceRef pdp_ram_10_3_20)) + (portRef ADA7 (instanceRef pdp_ram_11_0_19)) + (portRef ADA7 (instanceRef pdp_ram_11_1_18)) + (portRef ADA7 (instanceRef pdp_ram_11_2_17)) + (portRef ADA7 (instanceRef pdp_ram_11_3_16)) + (portRef ADA7 (instanceRef pdp_ram_12_0_15)) + (portRef ADA7 (instanceRef pdp_ram_12_1_14)) + (portRef ADA7 (instanceRef pdp_ram_12_2_13)) + (portRef ADA7 (instanceRef pdp_ram_12_3_12)) + (portRef ADA7 (instanceRef pdp_ram_13_0_11)) + (portRef ADA7 (instanceRef pdp_ram_13_1_10)) + (portRef ADA7 (instanceRef pdp_ram_13_2_9)) + (portRef ADA7 (instanceRef pdp_ram_13_3_8)) + (portRef ADA7 (instanceRef pdp_ram_14_0_7)) + (portRef ADA7 (instanceRef pdp_ram_14_1_6)) + (portRef ADA7 (instanceRef pdp_ram_14_2_5)) + (portRef ADA7 (instanceRef pdp_ram_14_3_4)) + (portRef ADA7 (instanceRef pdp_ram_15_0_3)) + (portRef ADA7 (instanceRef pdp_ram_15_1_2)) + (portRef ADA7 (instanceRef pdp_ram_15_2_1)) + (portRef ADA7 (instanceRef pdp_ram_15_3_0)))) + (net wptr_5 + (joined + (portRef Q (instanceRef FF_51)) + (portRef ADA8 (instanceRef pdp_ram_0_0_63)) + (portRef ADA8 (instanceRef pdp_ram_0_1_62)) + (portRef ADA8 (instanceRef pdp_ram_0_2_61)) + (portRef ADA8 (instanceRef pdp_ram_0_3_60)) + (portRef ADA8 (instanceRef pdp_ram_1_0_59)) + (portRef ADA8 (instanceRef pdp_ram_1_1_58)) + (portRef ADA8 (instanceRef pdp_ram_1_2_57)) + (portRef ADA8 (instanceRef pdp_ram_1_3_56)) + (portRef ADA8 (instanceRef pdp_ram_2_0_55)) + (portRef ADA8 (instanceRef pdp_ram_2_1_54)) + (portRef ADA8 (instanceRef pdp_ram_2_2_53)) + (portRef ADA8 (instanceRef pdp_ram_2_3_52)) + (portRef ADA8 (instanceRef pdp_ram_3_0_51)) + (portRef ADA8 (instanceRef pdp_ram_3_1_50)) + (portRef ADA8 (instanceRef pdp_ram_3_2_49)) + (portRef ADA8 (instanceRef pdp_ram_3_3_48)) + (portRef ADA8 (instanceRef pdp_ram_4_0_47)) + (portRef ADA8 (instanceRef pdp_ram_4_1_46)) + (portRef ADA8 (instanceRef pdp_ram_4_2_45)) + (portRef ADA8 (instanceRef pdp_ram_4_3_44)) + (portRef ADA8 (instanceRef pdp_ram_5_0_43)) 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pdp_ram_1_0_59)) + (portRef ADB2 (instanceRef pdp_ram_1_0_59)) + (portRef ADA2 (instanceRef pdp_ram_1_0_59)) + (portRef ADB1 (instanceRef pdp_ram_1_0_59)) + (portRef ADA1 (instanceRef pdp_ram_1_0_59)) + (portRef ADB0 (instanceRef pdp_ram_1_0_59)) + (portRef ADA0 (instanceRef pdp_ram_1_0_59)) + (portRef DIB17 (instanceRef pdp_ram_1_0_59)) + (portRef DIA17 (instanceRef pdp_ram_1_0_59)) + (portRef DIB16 (instanceRef pdp_ram_1_0_59)) + (portRef DIA16 (instanceRef pdp_ram_1_0_59)) + (portRef DIB15 (instanceRef pdp_ram_1_0_59)) + (portRef DIA15 (instanceRef pdp_ram_1_0_59)) + (portRef DIB14 (instanceRef pdp_ram_1_0_59)) + (portRef DIA14 (instanceRef pdp_ram_1_0_59)) + (portRef DIB13 (instanceRef pdp_ram_1_0_59)) + (portRef DIA13 (instanceRef pdp_ram_1_0_59)) + (portRef DIB12 (instanceRef pdp_ram_1_0_59)) + (portRef DIA12 (instanceRef pdp_ram_1_0_59)) + (portRef DIB11 (instanceRef pdp_ram_1_0_59)) + (portRef DIA11 (instanceRef pdp_ram_1_0_59)) + (portRef DIB10 (instanceRef pdp_ram_1_0_59)) + (portRef DIA10 (instanceRef pdp_ram_1_0_59)) + (portRef DIB9 (instanceRef pdp_ram_1_0_59)) + (portRef DIA9 (instanceRef pdp_ram_1_0_59)) + (portRef DIB8 (instanceRef pdp_ram_1_0_59)) + (portRef DIB7 (instanceRef pdp_ram_1_0_59)) + (portRef DIB6 (instanceRef pdp_ram_1_0_59)) + (portRef DIB5 (instanceRef pdp_ram_1_0_59)) + (portRef DIB4 (instanceRef pdp_ram_1_0_59)) + (portRef DIB3 (instanceRef pdp_ram_1_0_59)) + (portRef DIB2 (instanceRef pdp_ram_1_0_59)) + (portRef DIB1 (instanceRef pdp_ram_1_0_59)) + (portRef DIB0 (instanceRef pdp_ram_1_0_59)) + (portRef CSB2 (instanceRef pdp_ram_1_1_58)) + (portRef CSA2 (instanceRef pdp_ram_1_1_58)) + (portRef CSB1 (instanceRef pdp_ram_1_1_58)) + (portRef CSA1 (instanceRef pdp_ram_1_1_58)) + (portRef WEB (instanceRef pdp_ram_1_1_58)) + (portRef ADB2 (instanceRef pdp_ram_1_1_58)) + (portRef ADA2 (instanceRef pdp_ram_1_1_58)) + (portRef ADB1 (instanceRef pdp_ram_1_1_58)) + (portRef ADA1 (instanceRef pdp_ram_1_1_58)) + (portRef ADB0 (instanceRef pdp_ram_1_1_58)) + (portRef ADA0 (instanceRef pdp_ram_1_1_58)) + (portRef DIB17 (instanceRef pdp_ram_1_1_58)) + (portRef DIA17 (instanceRef pdp_ram_1_1_58)) + (portRef DIB16 (instanceRef pdp_ram_1_1_58)) + (portRef DIA16 (instanceRef pdp_ram_1_1_58)) + (portRef DIB15 (instanceRef pdp_ram_1_1_58)) + (portRef DIA15 (instanceRef pdp_ram_1_1_58)) + (portRef DIB14 (instanceRef pdp_ram_1_1_58)) + (portRef DIA14 (instanceRef pdp_ram_1_1_58)) + (portRef DIB13 (instanceRef pdp_ram_1_1_58)) + (portRef DIA13 (instanceRef pdp_ram_1_1_58)) + (portRef DIB12 (instanceRef pdp_ram_1_1_58)) + (portRef DIA12 (instanceRef pdp_ram_1_1_58)) + (portRef DIB11 (instanceRef pdp_ram_1_1_58)) + (portRef DIA11 (instanceRef pdp_ram_1_1_58)) + (portRef DIB10 (instanceRef pdp_ram_1_1_58)) + (portRef DIA10 (instanceRef pdp_ram_1_1_58)) + (portRef DIB9 (instanceRef pdp_ram_1_1_58)) + (portRef DIA9 (instanceRef pdp_ram_1_1_58)) + (portRef DIB8 (instanceRef pdp_ram_1_1_58)) + (portRef DIB7 (instanceRef pdp_ram_1_1_58)) + (portRef DIB6 (instanceRef pdp_ram_1_1_58)) + (portRef DIB5 (instanceRef pdp_ram_1_1_58)) + (portRef DIB4 (instanceRef pdp_ram_1_1_58)) + (portRef DIB3 (instanceRef pdp_ram_1_1_58)) + (portRef DIB2 (instanceRef pdp_ram_1_1_58)) + (portRef DIB1 (instanceRef pdp_ram_1_1_58)) + (portRef DIB0 (instanceRef pdp_ram_1_1_58)) + (portRef CSB2 (instanceRef pdp_ram_1_2_57)) + (portRef CSA2 (instanceRef pdp_ram_1_2_57)) + (portRef CSB1 (instanceRef pdp_ram_1_2_57)) + (portRef CSA1 (instanceRef pdp_ram_1_2_57)) + (portRef WEB (instanceRef pdp_ram_1_2_57)) + (portRef ADB2 (instanceRef pdp_ram_1_2_57)) + (portRef ADA2 (instanceRef pdp_ram_1_2_57)) + (portRef ADB1 (instanceRef pdp_ram_1_2_57)) + (portRef ADA1 (instanceRef pdp_ram_1_2_57)) + (portRef ADB0 (instanceRef pdp_ram_1_2_57)) + (portRef ADA0 (instanceRef pdp_ram_1_2_57)) + (portRef DIB17 (instanceRef pdp_ram_1_2_57)) + (portRef DIA17 (instanceRef pdp_ram_1_2_57)) + (portRef DIB16 (instanceRef pdp_ram_1_2_57)) + (portRef DIA16 (instanceRef pdp_ram_1_2_57)) + (portRef DIB15 (instanceRef pdp_ram_1_2_57)) + (portRef DIA15 (instanceRef pdp_ram_1_2_57)) + (portRef DIB14 (instanceRef pdp_ram_1_2_57)) + (portRef DIA14 (instanceRef pdp_ram_1_2_57)) + (portRef DIB13 (instanceRef pdp_ram_1_2_57)) + (portRef DIA13 (instanceRef pdp_ram_1_2_57)) + (portRef DIB12 (instanceRef pdp_ram_1_2_57)) + (portRef DIA12 (instanceRef pdp_ram_1_2_57)) + (portRef DIB11 (instanceRef pdp_ram_1_2_57)) + (portRef DIA11 (instanceRef pdp_ram_1_2_57)) + (portRef DIB10 (instanceRef pdp_ram_1_2_57)) + (portRef DIA10 (instanceRef pdp_ram_1_2_57)) + (portRef DIB9 (instanceRef pdp_ram_1_2_57)) + (portRef DIA9 (instanceRef pdp_ram_1_2_57)) + (portRef DIB8 (instanceRef pdp_ram_1_2_57)) + (portRef DIB7 (instanceRef pdp_ram_1_2_57)) + (portRef DIB6 (instanceRef pdp_ram_1_2_57)) + (portRef DIB5 (instanceRef pdp_ram_1_2_57)) + (portRef DIB4 (instanceRef pdp_ram_1_2_57)) + (portRef DIB3 (instanceRef pdp_ram_1_2_57)) + (portRef DIB2 (instanceRef pdp_ram_1_2_57)) + (portRef DIB1 (instanceRef pdp_ram_1_2_57)) + (portRef DIB0 (instanceRef pdp_ram_1_2_57)) + (portRef CSB2 (instanceRef pdp_ram_1_3_56)) + (portRef CSA2 (instanceRef pdp_ram_1_3_56)) + (portRef CSB1 (instanceRef pdp_ram_1_3_56)) + (portRef CSA1 (instanceRef pdp_ram_1_3_56)) + (portRef WEB (instanceRef pdp_ram_1_3_56)) + (portRef ADB2 (instanceRef pdp_ram_1_3_56)) + (portRef ADA2 (instanceRef pdp_ram_1_3_56)) + (portRef ADB1 (instanceRef pdp_ram_1_3_56)) + (portRef ADA1 (instanceRef pdp_ram_1_3_56)) + (portRef ADB0 (instanceRef pdp_ram_1_3_56)) + (portRef ADA0 (instanceRef pdp_ram_1_3_56)) + (portRef DIB17 (instanceRef pdp_ram_1_3_56)) + (portRef DIA17 (instanceRef pdp_ram_1_3_56)) + (portRef DIB16 (instanceRef pdp_ram_1_3_56)) + (portRef DIA16 (instanceRef pdp_ram_1_3_56)) + (portRef DIB15 (instanceRef pdp_ram_1_3_56)) + (portRef DIA15 (instanceRef pdp_ram_1_3_56)) + (portRef DIB14 (instanceRef pdp_ram_1_3_56)) + (portRef DIA14 (instanceRef pdp_ram_1_3_56)) + (portRef DIB13 (instanceRef pdp_ram_1_3_56)) + (portRef DIA13 (instanceRef pdp_ram_1_3_56)) + (portRef DIB12 (instanceRef pdp_ram_1_3_56)) + (portRef DIA12 (instanceRef pdp_ram_1_3_56)) + (portRef DIB11 (instanceRef pdp_ram_1_3_56)) + (portRef DIA11 (instanceRef pdp_ram_1_3_56)) + (portRef DIB10 (instanceRef pdp_ram_1_3_56)) + (portRef DIA10 (instanceRef pdp_ram_1_3_56)) + (portRef DIB9 (instanceRef pdp_ram_1_3_56)) + (portRef DIA9 (instanceRef pdp_ram_1_3_56)) + (portRef DIB8 (instanceRef pdp_ram_1_3_56)) + (portRef DIB7 (instanceRef pdp_ram_1_3_56)) + (portRef DIB6 (instanceRef pdp_ram_1_3_56)) + (portRef DIB5 (instanceRef pdp_ram_1_3_56)) + (portRef DIB4 (instanceRef pdp_ram_1_3_56)) + (portRef DIB3 (instanceRef pdp_ram_1_3_56)) + (portRef DIB2 (instanceRef pdp_ram_1_3_56)) + (portRef DIB1 (instanceRef pdp_ram_1_3_56)) + (portRef DIB0 (instanceRef pdp_ram_1_3_56)) + (portRef CSB2 (instanceRef pdp_ram_2_0_55)) + (portRef CSA2 (instanceRef pdp_ram_2_0_55)) + (portRef CSB1 (instanceRef pdp_ram_2_0_55)) + (portRef CSA1 (instanceRef pdp_ram_2_0_55)) + (portRef WEB (instanceRef pdp_ram_2_0_55)) + (portRef ADB2 (instanceRef pdp_ram_2_0_55)) + (portRef ADA2 (instanceRef pdp_ram_2_0_55)) + (portRef ADB1 (instanceRef pdp_ram_2_0_55)) + (portRef ADA1 (instanceRef pdp_ram_2_0_55)) + (portRef ADB0 (instanceRef pdp_ram_2_0_55)) + (portRef ADA0 (instanceRef pdp_ram_2_0_55)) + (portRef DIB17 (instanceRef pdp_ram_2_0_55)) + (portRef DIA17 (instanceRef pdp_ram_2_0_55)) + (portRef DIB16 (instanceRef pdp_ram_2_0_55)) + (portRef DIA16 (instanceRef pdp_ram_2_0_55)) + (portRef DIB15 (instanceRef pdp_ram_2_0_55)) + (portRef DIA15 (instanceRef pdp_ram_2_0_55)) + (portRef DIB14 (instanceRef pdp_ram_2_0_55)) + (portRef DIA14 (instanceRef pdp_ram_2_0_55)) + (portRef DIB13 (instanceRef pdp_ram_2_0_55)) + (portRef DIA13 (instanceRef pdp_ram_2_0_55)) + (portRef DIB12 (instanceRef pdp_ram_2_0_55)) + (portRef DIA12 (instanceRef pdp_ram_2_0_55)) + (portRef DIB11 (instanceRef pdp_ram_2_0_55)) + (portRef DIA11 (instanceRef pdp_ram_2_0_55)) + (portRef DIB10 (instanceRef pdp_ram_2_0_55)) + (portRef DIA10 (instanceRef pdp_ram_2_0_55)) + (portRef DIB9 (instanceRef pdp_ram_2_0_55)) + (portRef DIA9 (instanceRef pdp_ram_2_0_55)) + (portRef DIB8 (instanceRef pdp_ram_2_0_55)) + (portRef DIB7 (instanceRef pdp_ram_2_0_55)) + (portRef DIB6 (instanceRef pdp_ram_2_0_55)) + (portRef DIB5 (instanceRef pdp_ram_2_0_55)) + (portRef DIB4 (instanceRef pdp_ram_2_0_55)) + (portRef DIB3 (instanceRef pdp_ram_2_0_55)) + (portRef DIB2 (instanceRef pdp_ram_2_0_55)) + (portRef DIB1 (instanceRef pdp_ram_2_0_55)) + (portRef DIB0 (instanceRef pdp_ram_2_0_55)) + (portRef CSB2 (instanceRef pdp_ram_2_1_54)) + (portRef CSA2 (instanceRef pdp_ram_2_1_54)) + (portRef CSB1 (instanceRef pdp_ram_2_1_54)) + (portRef CSA1 (instanceRef pdp_ram_2_1_54)) + (portRef WEB (instanceRef pdp_ram_2_1_54)) + (portRef ADB2 (instanceRef pdp_ram_2_1_54)) + (portRef ADA2 (instanceRef pdp_ram_2_1_54)) + (portRef ADB1 (instanceRef pdp_ram_2_1_54)) + (portRef ADA1 (instanceRef pdp_ram_2_1_54)) + (portRef ADB0 (instanceRef pdp_ram_2_1_54)) + (portRef ADA0 (instanceRef pdp_ram_2_1_54)) + (portRef DIB17 (instanceRef pdp_ram_2_1_54)) + (portRef DIA17 (instanceRef pdp_ram_2_1_54)) + (portRef DIB16 (instanceRef pdp_ram_2_1_54)) + (portRef DIA16 (instanceRef pdp_ram_2_1_54)) + (portRef DIB15 (instanceRef pdp_ram_2_1_54)) + (portRef DIA15 (instanceRef pdp_ram_2_1_54)) + (portRef DIB14 (instanceRef pdp_ram_2_1_54)) + (portRef DIA14 (instanceRef pdp_ram_2_1_54)) + (portRef DIB13 (instanceRef pdp_ram_2_1_54)) + (portRef DIA13 (instanceRef pdp_ram_2_1_54)) + (portRef DIB12 (instanceRef pdp_ram_2_1_54)) + (portRef DIA12 (instanceRef pdp_ram_2_1_54)) + (portRef DIB11 (instanceRef pdp_ram_2_1_54)) + (portRef DIA11 (instanceRef pdp_ram_2_1_54)) + (portRef DIB10 (instanceRef pdp_ram_2_1_54)) + (portRef DIA10 (instanceRef pdp_ram_2_1_54)) + (portRef DIB9 (instanceRef pdp_ram_2_1_54)) + (portRef DIA9 (instanceRef pdp_ram_2_1_54)) + (portRef DIB8 (instanceRef pdp_ram_2_1_54)) + (portRef DIB7 (instanceRef pdp_ram_2_1_54)) + (portRef DIB6 (instanceRef pdp_ram_2_1_54)) + (portRef DIB5 (instanceRef pdp_ram_2_1_54)) + (portRef DIB4 (instanceRef pdp_ram_2_1_54)) + (portRef DIB3 (instanceRef pdp_ram_2_1_54)) + (portRef DIB2 (instanceRef pdp_ram_2_1_54)) + (portRef DIB1 (instanceRef pdp_ram_2_1_54)) + (portRef DIB0 (instanceRef pdp_ram_2_1_54)) + (portRef CSB2 (instanceRef pdp_ram_2_2_53)) + (portRef CSA2 (instanceRef pdp_ram_2_2_53)) + (portRef CSB1 (instanceRef pdp_ram_2_2_53)) + (portRef CSA1 (instanceRef pdp_ram_2_2_53)) + (portRef WEB (instanceRef pdp_ram_2_2_53)) + (portRef ADB2 (instanceRef pdp_ram_2_2_53)) + (portRef ADA2 (instanceRef pdp_ram_2_2_53)) + (portRef ADB1 (instanceRef pdp_ram_2_2_53)) + (portRef ADA1 (instanceRef pdp_ram_2_2_53)) + (portRef ADB0 (instanceRef pdp_ram_2_2_53)) + (portRef ADA0 (instanceRef pdp_ram_2_2_53)) + (portRef DIB17 (instanceRef pdp_ram_2_2_53)) + (portRef DIA17 (instanceRef pdp_ram_2_2_53)) + (portRef DIB16 (instanceRef pdp_ram_2_2_53)) + (portRef DIA16 (instanceRef pdp_ram_2_2_53)) + (portRef DIB15 (instanceRef pdp_ram_2_2_53)) + (portRef DIA15 (instanceRef pdp_ram_2_2_53)) + (portRef DIB14 (instanceRef pdp_ram_2_2_53)) + (portRef DIA14 (instanceRef pdp_ram_2_2_53)) + (portRef DIB13 (instanceRef pdp_ram_2_2_53)) + (portRef DIA13 (instanceRef pdp_ram_2_2_53)) + (portRef DIB12 (instanceRef pdp_ram_2_2_53)) + (portRef DIA12 (instanceRef pdp_ram_2_2_53)) + (portRef DIB11 (instanceRef pdp_ram_2_2_53)) + (portRef DIA11 (instanceRef pdp_ram_2_2_53)) + (portRef DIB10 (instanceRef pdp_ram_2_2_53)) + (portRef DIA10 (instanceRef pdp_ram_2_2_53)) + (portRef DIB9 (instanceRef pdp_ram_2_2_53)) + (portRef DIA9 (instanceRef pdp_ram_2_2_53)) + (portRef DIB8 (instanceRef pdp_ram_2_2_53)) + (portRef DIB7 (instanceRef pdp_ram_2_2_53)) + (portRef DIB6 (instanceRef pdp_ram_2_2_53)) + (portRef DIB5 (instanceRef pdp_ram_2_2_53)) + (portRef DIB4 (instanceRef pdp_ram_2_2_53)) + (portRef DIB3 (instanceRef pdp_ram_2_2_53)) + (portRef DIB2 (instanceRef pdp_ram_2_2_53)) + (portRef DIB1 (instanceRef pdp_ram_2_2_53)) + (portRef DIB0 (instanceRef pdp_ram_2_2_53)) + (portRef CSB2 (instanceRef pdp_ram_2_3_52)) + (portRef CSA2 (instanceRef pdp_ram_2_3_52)) + (portRef CSB1 (instanceRef pdp_ram_2_3_52)) + (portRef CSA1 (instanceRef pdp_ram_2_3_52)) + (portRef WEB (instanceRef pdp_ram_2_3_52)) + (portRef ADB2 (instanceRef pdp_ram_2_3_52)) + (portRef ADA2 (instanceRef pdp_ram_2_3_52)) + (portRef ADB1 (instanceRef pdp_ram_2_3_52)) + (portRef ADA1 (instanceRef pdp_ram_2_3_52)) + (portRef ADB0 (instanceRef pdp_ram_2_3_52)) + (portRef ADA0 (instanceRef pdp_ram_2_3_52)) + (portRef DIB17 (instanceRef pdp_ram_2_3_52)) + (portRef DIA17 (instanceRef pdp_ram_2_3_52)) + (portRef DIB16 (instanceRef pdp_ram_2_3_52)) + (portRef DIA16 (instanceRef pdp_ram_2_3_52)) + (portRef DIB15 (instanceRef pdp_ram_2_3_52)) + (portRef DIA15 (instanceRef pdp_ram_2_3_52)) + (portRef DIB14 (instanceRef pdp_ram_2_3_52)) + (portRef DIA14 (instanceRef pdp_ram_2_3_52)) + (portRef DIB13 (instanceRef pdp_ram_2_3_52)) + (portRef DIA13 (instanceRef pdp_ram_2_3_52)) + (portRef DIB12 (instanceRef pdp_ram_2_3_52)) + (portRef DIA12 (instanceRef pdp_ram_2_3_52)) + (portRef DIB11 (instanceRef pdp_ram_2_3_52)) + (portRef DIA11 (instanceRef pdp_ram_2_3_52)) + (portRef DIB10 (instanceRef pdp_ram_2_3_52)) + (portRef DIA10 (instanceRef pdp_ram_2_3_52)) + (portRef DIB9 (instanceRef pdp_ram_2_3_52)) + (portRef DIA9 (instanceRef pdp_ram_2_3_52)) + (portRef DIB8 (instanceRef pdp_ram_2_3_52)) + (portRef DIB7 (instanceRef pdp_ram_2_3_52)) + (portRef DIB6 (instanceRef pdp_ram_2_3_52)) + (portRef DIB5 (instanceRef pdp_ram_2_3_52)) + (portRef DIB4 (instanceRef pdp_ram_2_3_52)) + (portRef DIB3 (instanceRef pdp_ram_2_3_52)) + (portRef DIB2 (instanceRef pdp_ram_2_3_52)) + (portRef DIB1 (instanceRef pdp_ram_2_3_52)) + (portRef DIB0 (instanceRef pdp_ram_2_3_52)) + (portRef CSB2 (instanceRef pdp_ram_3_0_51)) + (portRef CSA2 (instanceRef pdp_ram_3_0_51)) + (portRef CSB1 (instanceRef pdp_ram_3_0_51)) + (portRef CSA1 (instanceRef pdp_ram_3_0_51)) + (portRef WEB (instanceRef pdp_ram_3_0_51)) + (portRef ADB2 (instanceRef pdp_ram_3_0_51)) + (portRef ADA2 (instanceRef pdp_ram_3_0_51)) + (portRef ADB1 (instanceRef pdp_ram_3_0_51)) + (portRef ADA1 (instanceRef pdp_ram_3_0_51)) + (portRef ADB0 (instanceRef pdp_ram_3_0_51)) + (portRef ADA0 (instanceRef pdp_ram_3_0_51)) + (portRef DIB17 (instanceRef pdp_ram_3_0_51)) + (portRef DIA17 (instanceRef pdp_ram_3_0_51)) + (portRef DIB16 (instanceRef pdp_ram_3_0_51)) + (portRef DIA16 (instanceRef pdp_ram_3_0_51)) + (portRef DIB15 (instanceRef pdp_ram_3_0_51)) + (portRef DIA15 (instanceRef pdp_ram_3_0_51)) + (portRef DIB14 (instanceRef pdp_ram_3_0_51)) + (portRef DIA14 (instanceRef pdp_ram_3_0_51)) + (portRef DIB13 (instanceRef pdp_ram_3_0_51)) + (portRef DIA13 (instanceRef pdp_ram_3_0_51)) + (portRef DIB12 (instanceRef pdp_ram_3_0_51)) + (portRef DIA12 (instanceRef pdp_ram_3_0_51)) + (portRef DIB11 (instanceRef pdp_ram_3_0_51)) + (portRef DIA11 (instanceRef pdp_ram_3_0_51)) + (portRef DIB10 (instanceRef pdp_ram_3_0_51)) + (portRef DIA10 (instanceRef pdp_ram_3_0_51)) + (portRef DIB9 (instanceRef pdp_ram_3_0_51)) + (portRef DIA9 (instanceRef pdp_ram_3_0_51)) + (portRef DIB8 (instanceRef pdp_ram_3_0_51)) + (portRef DIB7 (instanceRef pdp_ram_3_0_51)) + (portRef DIB6 (instanceRef pdp_ram_3_0_51)) + (portRef DIB5 (instanceRef pdp_ram_3_0_51)) + (portRef DIB4 (instanceRef pdp_ram_3_0_51)) + (portRef DIB3 (instanceRef pdp_ram_3_0_51)) + (portRef DIB2 (instanceRef pdp_ram_3_0_51)) + (portRef DIB1 (instanceRef pdp_ram_3_0_51)) + (portRef DIB0 (instanceRef pdp_ram_3_0_51)) + (portRef CSB2 (instanceRef pdp_ram_3_1_50)) + (portRef CSA2 (instanceRef pdp_ram_3_1_50)) + (portRef CSB1 (instanceRef pdp_ram_3_1_50)) + (portRef CSA1 (instanceRef pdp_ram_3_1_50)) + (portRef WEB (instanceRef pdp_ram_3_1_50)) + (portRef ADB2 (instanceRef pdp_ram_3_1_50)) + (portRef ADA2 (instanceRef pdp_ram_3_1_50)) + (portRef ADB1 (instanceRef pdp_ram_3_1_50)) + (portRef ADA1 (instanceRef pdp_ram_3_1_50)) + (portRef ADB0 (instanceRef pdp_ram_3_1_50)) + (portRef ADA0 (instanceRef pdp_ram_3_1_50)) + (portRef DIB17 (instanceRef pdp_ram_3_1_50)) + (portRef DIA17 (instanceRef pdp_ram_3_1_50)) + (portRef DIB16 (instanceRef pdp_ram_3_1_50)) + (portRef DIA16 (instanceRef pdp_ram_3_1_50)) + (portRef DIB15 (instanceRef pdp_ram_3_1_50)) + (portRef DIA15 (instanceRef pdp_ram_3_1_50)) + (portRef DIB14 (instanceRef pdp_ram_3_1_50)) + (portRef DIA14 (instanceRef pdp_ram_3_1_50)) + (portRef DIB13 (instanceRef pdp_ram_3_1_50)) + (portRef DIA13 (instanceRef pdp_ram_3_1_50)) + (portRef DIB12 (instanceRef pdp_ram_3_1_50)) + (portRef DIA12 (instanceRef pdp_ram_3_1_50)) + (portRef DIB11 (instanceRef pdp_ram_3_1_50)) + (portRef DIA11 (instanceRef pdp_ram_3_1_50)) + (portRef DIB10 (instanceRef pdp_ram_3_1_50)) + (portRef DIA10 (instanceRef pdp_ram_3_1_50)) + (portRef DIB9 (instanceRef pdp_ram_3_1_50)) + (portRef DIA9 (instanceRef pdp_ram_3_1_50)) + (portRef DIB8 (instanceRef pdp_ram_3_1_50)) + (portRef DIB7 (instanceRef pdp_ram_3_1_50)) + (portRef DIB6 (instanceRef pdp_ram_3_1_50)) + (portRef DIB5 (instanceRef pdp_ram_3_1_50)) + (portRef DIB4 (instanceRef pdp_ram_3_1_50)) + (portRef DIB3 (instanceRef pdp_ram_3_1_50)) + (portRef DIB2 (instanceRef pdp_ram_3_1_50)) + (portRef DIB1 (instanceRef pdp_ram_3_1_50)) + (portRef DIB0 (instanceRef pdp_ram_3_1_50)) + (portRef CSB2 (instanceRef pdp_ram_3_2_49)) + (portRef CSA2 (instanceRef pdp_ram_3_2_49)) + (portRef CSB1 (instanceRef pdp_ram_3_2_49)) + (portRef CSA1 (instanceRef pdp_ram_3_2_49)) + (portRef WEB (instanceRef pdp_ram_3_2_49)) + (portRef ADB2 (instanceRef pdp_ram_3_2_49)) + (portRef ADA2 (instanceRef pdp_ram_3_2_49)) + (portRef ADB1 (instanceRef pdp_ram_3_2_49)) + (portRef ADA1 (instanceRef pdp_ram_3_2_49)) + (portRef ADB0 (instanceRef pdp_ram_3_2_49)) + (portRef ADA0 (instanceRef pdp_ram_3_2_49)) + (portRef DIB17 (instanceRef pdp_ram_3_2_49)) + (portRef DIA17 (instanceRef pdp_ram_3_2_49)) + (portRef DIB16 (instanceRef pdp_ram_3_2_49)) + (portRef DIA16 (instanceRef pdp_ram_3_2_49)) + (portRef DIB15 (instanceRef pdp_ram_3_2_49)) + (portRef DIA15 (instanceRef pdp_ram_3_2_49)) + (portRef DIB14 (instanceRef pdp_ram_3_2_49)) + (portRef DIA14 (instanceRef pdp_ram_3_2_49)) + (portRef DIB13 (instanceRef pdp_ram_3_2_49)) + (portRef DIA13 (instanceRef pdp_ram_3_2_49)) + (portRef DIB12 (instanceRef pdp_ram_3_2_49)) + (portRef DIA12 (instanceRef pdp_ram_3_2_49)) + (portRef DIB11 (instanceRef pdp_ram_3_2_49)) + (portRef DIA11 (instanceRef pdp_ram_3_2_49)) + (portRef DIB10 (instanceRef pdp_ram_3_2_49)) + (portRef DIA10 (instanceRef pdp_ram_3_2_49)) + (portRef DIB9 (instanceRef pdp_ram_3_2_49)) + (portRef DIA9 (instanceRef pdp_ram_3_2_49)) + (portRef DIB8 (instanceRef pdp_ram_3_2_49)) + (portRef DIB7 (instanceRef pdp_ram_3_2_49)) + (portRef DIB6 (instanceRef pdp_ram_3_2_49)) + (portRef DIB5 (instanceRef pdp_ram_3_2_49)) + (portRef DIB4 (instanceRef pdp_ram_3_2_49)) + (portRef DIB3 (instanceRef pdp_ram_3_2_49)) + (portRef DIB2 (instanceRef pdp_ram_3_2_49)) + (portRef DIB1 (instanceRef pdp_ram_3_2_49)) + (portRef DIB0 (instanceRef pdp_ram_3_2_49)) + (portRef CSB2 (instanceRef pdp_ram_3_3_48)) + (portRef CSA2 (instanceRef pdp_ram_3_3_48)) + (portRef CSB1 (instanceRef pdp_ram_3_3_48)) + (portRef CSA1 (instanceRef pdp_ram_3_3_48)) + (portRef WEB (instanceRef pdp_ram_3_3_48)) + (portRef ADB2 (instanceRef pdp_ram_3_3_48)) + (portRef ADA2 (instanceRef pdp_ram_3_3_48)) + (portRef ADB1 (instanceRef pdp_ram_3_3_48)) + (portRef ADA1 (instanceRef pdp_ram_3_3_48)) + (portRef ADB0 (instanceRef pdp_ram_3_3_48)) + (portRef ADA0 (instanceRef pdp_ram_3_3_48)) + (portRef DIB17 (instanceRef pdp_ram_3_3_48)) + (portRef DIA17 (instanceRef pdp_ram_3_3_48)) + (portRef DIB16 (instanceRef pdp_ram_3_3_48)) + (portRef DIA16 (instanceRef pdp_ram_3_3_48)) + (portRef DIB15 (instanceRef pdp_ram_3_3_48)) + (portRef DIA15 (instanceRef pdp_ram_3_3_48)) + (portRef DIB14 (instanceRef pdp_ram_3_3_48)) + (portRef DIA14 (instanceRef pdp_ram_3_3_48)) + (portRef DIB13 (instanceRef pdp_ram_3_3_48)) + (portRef DIA13 (instanceRef pdp_ram_3_3_48)) + (portRef DIB12 (instanceRef pdp_ram_3_3_48)) + (portRef DIA12 (instanceRef pdp_ram_3_3_48)) + (portRef DIB11 (instanceRef pdp_ram_3_3_48)) + (portRef DIA11 (instanceRef pdp_ram_3_3_48)) + (portRef DIB10 (instanceRef pdp_ram_3_3_48)) + (portRef DIA10 (instanceRef pdp_ram_3_3_48)) + (portRef DIB9 (instanceRef pdp_ram_3_3_48)) + (portRef DIA9 (instanceRef pdp_ram_3_3_48)) + (portRef DIB8 (instanceRef pdp_ram_3_3_48)) + (portRef DIB7 (instanceRef pdp_ram_3_3_48)) + (portRef DIB6 (instanceRef pdp_ram_3_3_48)) + (portRef DIB5 (instanceRef pdp_ram_3_3_48)) + (portRef DIB4 (instanceRef pdp_ram_3_3_48)) + (portRef DIB3 (instanceRef pdp_ram_3_3_48)) + (portRef DIB2 (instanceRef pdp_ram_3_3_48)) + (portRef DIB1 (instanceRef pdp_ram_3_3_48)) + (portRef DIB0 (instanceRef pdp_ram_3_3_48)) + (portRef CSB2 (instanceRef pdp_ram_4_0_47)) + (portRef CSA2 (instanceRef pdp_ram_4_0_47)) + (portRef CSB1 (instanceRef pdp_ram_4_0_47)) + (portRef CSA1 (instanceRef pdp_ram_4_0_47)) + (portRef WEB (instanceRef pdp_ram_4_0_47)) + (portRef ADB2 (instanceRef pdp_ram_4_0_47)) + (portRef ADA2 (instanceRef pdp_ram_4_0_47)) + (portRef ADB1 (instanceRef pdp_ram_4_0_47)) + (portRef ADA1 (instanceRef pdp_ram_4_0_47)) + (portRef ADB0 (instanceRef pdp_ram_4_0_47)) + (portRef ADA0 (instanceRef pdp_ram_4_0_47)) + (portRef DIB17 (instanceRef pdp_ram_4_0_47)) + (portRef DIA17 (instanceRef pdp_ram_4_0_47)) + (portRef DIB16 (instanceRef pdp_ram_4_0_47)) + (portRef DIA16 (instanceRef pdp_ram_4_0_47)) + (portRef DIB15 (instanceRef pdp_ram_4_0_47)) + (portRef DIA15 (instanceRef pdp_ram_4_0_47)) + (portRef DIB14 (instanceRef pdp_ram_4_0_47)) + (portRef DIA14 (instanceRef pdp_ram_4_0_47)) + (portRef DIB13 (instanceRef pdp_ram_4_0_47)) + (portRef DIA13 (instanceRef pdp_ram_4_0_47)) + (portRef DIB12 (instanceRef pdp_ram_4_0_47)) + (portRef DIA12 (instanceRef pdp_ram_4_0_47)) + (portRef DIB11 (instanceRef pdp_ram_4_0_47)) + (portRef DIA11 (instanceRef pdp_ram_4_0_47)) + (portRef DIB10 (instanceRef pdp_ram_4_0_47)) + (portRef DIA10 (instanceRef pdp_ram_4_0_47)) + (portRef DIB9 (instanceRef pdp_ram_4_0_47)) + (portRef DIA9 (instanceRef pdp_ram_4_0_47)) + (portRef DIB8 (instanceRef pdp_ram_4_0_47)) + (portRef DIB7 (instanceRef pdp_ram_4_0_47)) + (portRef DIB6 (instanceRef pdp_ram_4_0_47)) + (portRef DIB5 (instanceRef pdp_ram_4_0_47)) + (portRef DIB4 (instanceRef pdp_ram_4_0_47)) + (portRef DIB3 (instanceRef pdp_ram_4_0_47)) + (portRef DIB2 (instanceRef pdp_ram_4_0_47)) + (portRef DIB1 (instanceRef pdp_ram_4_0_47)) + (portRef DIB0 (instanceRef pdp_ram_4_0_47)) + (portRef CSB2 (instanceRef pdp_ram_4_1_46)) + (portRef CSA2 (instanceRef pdp_ram_4_1_46)) + (portRef CSB1 (instanceRef pdp_ram_4_1_46)) + (portRef CSA1 (instanceRef pdp_ram_4_1_46)) + (portRef WEB (instanceRef pdp_ram_4_1_46)) + (portRef ADB2 (instanceRef pdp_ram_4_1_46)) + (portRef ADA2 (instanceRef pdp_ram_4_1_46)) + (portRef ADB1 (instanceRef pdp_ram_4_1_46)) + (portRef ADA1 (instanceRef pdp_ram_4_1_46)) + (portRef ADB0 (instanceRef pdp_ram_4_1_46)) + (portRef ADA0 (instanceRef pdp_ram_4_1_46)) + (portRef DIB17 (instanceRef pdp_ram_4_1_46)) + (portRef DIA17 (instanceRef pdp_ram_4_1_46)) + (portRef DIB16 (instanceRef pdp_ram_4_1_46)) + (portRef DIA16 (instanceRef pdp_ram_4_1_46)) + (portRef DIB15 (instanceRef pdp_ram_4_1_46)) + (portRef DIA15 (instanceRef pdp_ram_4_1_46)) + (portRef DIB14 (instanceRef pdp_ram_4_1_46)) + (portRef DIA14 (instanceRef pdp_ram_4_1_46)) + (portRef DIB13 (instanceRef pdp_ram_4_1_46)) + (portRef DIA13 (instanceRef pdp_ram_4_1_46)) + (portRef DIB12 (instanceRef pdp_ram_4_1_46)) + (portRef DIA12 (instanceRef pdp_ram_4_1_46)) + (portRef DIB11 (instanceRef pdp_ram_4_1_46)) + (portRef DIA11 (instanceRef pdp_ram_4_1_46)) + (portRef DIB10 (instanceRef pdp_ram_4_1_46)) + (portRef DIA10 (instanceRef pdp_ram_4_1_46)) + (portRef DIB9 (instanceRef pdp_ram_4_1_46)) + (portRef DIA9 (instanceRef pdp_ram_4_1_46)) + (portRef DIB8 (instanceRef pdp_ram_4_1_46)) + (portRef DIB7 (instanceRef pdp_ram_4_1_46)) + (portRef DIB6 (instanceRef pdp_ram_4_1_46)) + (portRef DIB5 (instanceRef pdp_ram_4_1_46)) + (portRef DIB4 (instanceRef pdp_ram_4_1_46)) + (portRef DIB3 (instanceRef pdp_ram_4_1_46)) + (portRef DIB2 (instanceRef pdp_ram_4_1_46)) + (portRef DIB1 (instanceRef pdp_ram_4_1_46)) + (portRef DIB0 (instanceRef pdp_ram_4_1_46)) + (portRef CSB2 (instanceRef pdp_ram_4_2_45)) + (portRef CSA2 (instanceRef pdp_ram_4_2_45)) + (portRef CSB1 (instanceRef pdp_ram_4_2_45)) + (portRef CSA1 (instanceRef pdp_ram_4_2_45)) + (portRef WEB (instanceRef pdp_ram_4_2_45)) + (portRef ADB2 (instanceRef pdp_ram_4_2_45)) + (portRef ADA2 (instanceRef pdp_ram_4_2_45)) + (portRef ADB1 (instanceRef pdp_ram_4_2_45)) + (portRef ADA1 (instanceRef pdp_ram_4_2_45)) + (portRef ADB0 (instanceRef pdp_ram_4_2_45)) + (portRef ADA0 (instanceRef pdp_ram_4_2_45)) + (portRef DIB17 (instanceRef pdp_ram_4_2_45)) + (portRef DIA17 (instanceRef pdp_ram_4_2_45)) + (portRef DIB16 (instanceRef pdp_ram_4_2_45)) + (portRef DIA16 (instanceRef pdp_ram_4_2_45)) + (portRef DIB15 (instanceRef pdp_ram_4_2_45)) + (portRef DIA15 (instanceRef pdp_ram_4_2_45)) + (portRef DIB14 (instanceRef pdp_ram_4_2_45)) + (portRef DIA14 (instanceRef pdp_ram_4_2_45)) + (portRef DIB13 (instanceRef pdp_ram_4_2_45)) + (portRef DIA13 (instanceRef pdp_ram_4_2_45)) + (portRef DIB12 (instanceRef pdp_ram_4_2_45)) + (portRef DIA12 (instanceRef pdp_ram_4_2_45)) + (portRef DIB11 (instanceRef pdp_ram_4_2_45)) + (portRef DIA11 (instanceRef pdp_ram_4_2_45)) + (portRef DIB10 (instanceRef pdp_ram_4_2_45)) + (portRef DIA10 (instanceRef pdp_ram_4_2_45)) + (portRef DIB9 (instanceRef pdp_ram_4_2_45)) + (portRef DIA9 (instanceRef pdp_ram_4_2_45)) + (portRef DIB8 (instanceRef pdp_ram_4_2_45)) + (portRef DIB7 (instanceRef pdp_ram_4_2_45)) + (portRef DIB6 (instanceRef pdp_ram_4_2_45)) + (portRef DIB5 (instanceRef pdp_ram_4_2_45)) + (portRef DIB4 (instanceRef pdp_ram_4_2_45)) + (portRef DIB3 (instanceRef pdp_ram_4_2_45)) + (portRef DIB2 (instanceRef pdp_ram_4_2_45)) + (portRef DIB1 (instanceRef pdp_ram_4_2_45)) + (portRef DIB0 (instanceRef pdp_ram_4_2_45)) + (portRef CSB2 (instanceRef pdp_ram_4_3_44)) + (portRef CSA2 (instanceRef pdp_ram_4_3_44)) + (portRef CSB1 (instanceRef pdp_ram_4_3_44)) + (portRef CSA1 (instanceRef pdp_ram_4_3_44)) + (portRef WEB (instanceRef pdp_ram_4_3_44)) + (portRef ADB2 (instanceRef pdp_ram_4_3_44)) + (portRef ADA2 (instanceRef pdp_ram_4_3_44)) + (portRef ADB1 (instanceRef pdp_ram_4_3_44)) + (portRef ADA1 (instanceRef pdp_ram_4_3_44)) + (portRef ADB0 (instanceRef pdp_ram_4_3_44)) + (portRef ADA0 (instanceRef pdp_ram_4_3_44)) + (portRef DIB17 (instanceRef pdp_ram_4_3_44)) + (portRef DIA17 (instanceRef pdp_ram_4_3_44)) + (portRef DIB16 (instanceRef pdp_ram_4_3_44)) + (portRef DIA16 (instanceRef pdp_ram_4_3_44)) + (portRef DIB15 (instanceRef pdp_ram_4_3_44)) + (portRef DIA15 (instanceRef pdp_ram_4_3_44)) + (portRef DIB14 (instanceRef pdp_ram_4_3_44)) + (portRef DIA14 (instanceRef pdp_ram_4_3_44)) + (portRef DIB13 (instanceRef pdp_ram_4_3_44)) + (portRef DIA13 (instanceRef pdp_ram_4_3_44)) + (portRef DIB12 (instanceRef pdp_ram_4_3_44)) + (portRef DIA12 (instanceRef pdp_ram_4_3_44)) + (portRef DIB11 (instanceRef pdp_ram_4_3_44)) + (portRef DIA11 (instanceRef pdp_ram_4_3_44)) + (portRef DIB10 (instanceRef pdp_ram_4_3_44)) + (portRef DIA10 (instanceRef pdp_ram_4_3_44)) + (portRef DIB9 (instanceRef pdp_ram_4_3_44)) + (portRef DIA9 (instanceRef pdp_ram_4_3_44)) + (portRef DIB8 (instanceRef pdp_ram_4_3_44)) + (portRef DIB7 (instanceRef pdp_ram_4_3_44)) + (portRef DIB6 (instanceRef pdp_ram_4_3_44)) + (portRef DIB5 (instanceRef pdp_ram_4_3_44)) + (portRef DIB4 (instanceRef pdp_ram_4_3_44)) + (portRef DIB3 (instanceRef pdp_ram_4_3_44)) + (portRef DIB2 (instanceRef pdp_ram_4_3_44)) + (portRef DIB1 (instanceRef pdp_ram_4_3_44)) + (portRef DIB0 (instanceRef pdp_ram_4_3_44)) + (portRef CSB2 (instanceRef pdp_ram_5_0_43)) + (portRef CSA2 (instanceRef pdp_ram_5_0_43)) + (portRef CSB1 (instanceRef pdp_ram_5_0_43)) + (portRef CSA1 (instanceRef pdp_ram_5_0_43)) + (portRef WEB (instanceRef pdp_ram_5_0_43)) + (portRef ADB2 (instanceRef pdp_ram_5_0_43)) + (portRef ADA2 (instanceRef pdp_ram_5_0_43)) + (portRef ADB1 (instanceRef pdp_ram_5_0_43)) + (portRef ADA1 (instanceRef pdp_ram_5_0_43)) + (portRef ADB0 (instanceRef pdp_ram_5_0_43)) + (portRef ADA0 (instanceRef pdp_ram_5_0_43)) + (portRef DIB17 (instanceRef pdp_ram_5_0_43)) + (portRef DIA17 (instanceRef pdp_ram_5_0_43)) + (portRef DIB16 (instanceRef pdp_ram_5_0_43)) + (portRef DIA16 (instanceRef pdp_ram_5_0_43)) + (portRef DIB15 (instanceRef pdp_ram_5_0_43)) + (portRef DIA15 (instanceRef pdp_ram_5_0_43)) + (portRef DIB14 (instanceRef pdp_ram_5_0_43)) + (portRef DIA14 (instanceRef pdp_ram_5_0_43)) + (portRef DIB13 (instanceRef pdp_ram_5_0_43)) + (portRef DIA13 (instanceRef pdp_ram_5_0_43)) + (portRef DIB12 (instanceRef pdp_ram_5_0_43)) + (portRef DIA12 (instanceRef pdp_ram_5_0_43)) + (portRef DIB11 (instanceRef pdp_ram_5_0_43)) + (portRef DIA11 (instanceRef pdp_ram_5_0_43)) + (portRef DIB10 (instanceRef pdp_ram_5_0_43)) + (portRef DIA10 (instanceRef pdp_ram_5_0_43)) + (portRef DIB9 (instanceRef pdp_ram_5_0_43)) + (portRef DIA9 (instanceRef pdp_ram_5_0_43)) + (portRef DIB8 (instanceRef pdp_ram_5_0_43)) + (portRef DIB7 (instanceRef pdp_ram_5_0_43)) + (portRef DIB6 (instanceRef pdp_ram_5_0_43)) + (portRef DIB5 (instanceRef pdp_ram_5_0_43)) + (portRef DIB4 (instanceRef pdp_ram_5_0_43)) + (portRef DIB3 (instanceRef pdp_ram_5_0_43)) + (portRef DIB2 (instanceRef pdp_ram_5_0_43)) + (portRef DIB1 (instanceRef pdp_ram_5_0_43)) + (portRef DIB0 (instanceRef pdp_ram_5_0_43)) + (portRef CSB2 (instanceRef pdp_ram_5_1_42)) + (portRef CSA2 (instanceRef pdp_ram_5_1_42)) + (portRef CSB1 (instanceRef pdp_ram_5_1_42)) + (portRef CSA1 (instanceRef pdp_ram_5_1_42)) + (portRef WEB (instanceRef pdp_ram_5_1_42)) + (portRef ADB2 (instanceRef pdp_ram_5_1_42)) + (portRef ADA2 (instanceRef pdp_ram_5_1_42)) + (portRef ADB1 (instanceRef pdp_ram_5_1_42)) + (portRef ADA1 (instanceRef pdp_ram_5_1_42)) + (portRef ADB0 (instanceRef pdp_ram_5_1_42)) + (portRef ADA0 (instanceRef pdp_ram_5_1_42)) + (portRef DIB17 (instanceRef pdp_ram_5_1_42)) + (portRef DIA17 (instanceRef pdp_ram_5_1_42)) + (portRef DIB16 (instanceRef pdp_ram_5_1_42)) + (portRef DIA16 (instanceRef pdp_ram_5_1_42)) + (portRef DIB15 (instanceRef pdp_ram_5_1_42)) + (portRef DIA15 (instanceRef pdp_ram_5_1_42)) + (portRef DIB14 (instanceRef pdp_ram_5_1_42)) + (portRef DIA14 (instanceRef pdp_ram_5_1_42)) + (portRef DIB13 (instanceRef pdp_ram_5_1_42)) + (portRef DIA13 (instanceRef pdp_ram_5_1_42)) + (portRef DIB12 (instanceRef pdp_ram_5_1_42)) + (portRef DIA12 (instanceRef pdp_ram_5_1_42)) + (portRef DIB11 (instanceRef pdp_ram_5_1_42)) + (portRef DIA11 (instanceRef pdp_ram_5_1_42)) + (portRef DIB10 (instanceRef pdp_ram_5_1_42)) + (portRef DIA10 (instanceRef pdp_ram_5_1_42)) + (portRef DIB9 (instanceRef pdp_ram_5_1_42)) + (portRef DIA9 (instanceRef pdp_ram_5_1_42)) + (portRef DIB8 (instanceRef pdp_ram_5_1_42)) + (portRef DIB7 (instanceRef pdp_ram_5_1_42)) + (portRef DIB6 (instanceRef pdp_ram_5_1_42)) + (portRef DIB5 (instanceRef pdp_ram_5_1_42)) + (portRef DIB4 (instanceRef pdp_ram_5_1_42)) + (portRef DIB3 (instanceRef pdp_ram_5_1_42)) + (portRef DIB2 (instanceRef pdp_ram_5_1_42)) + (portRef DIB1 (instanceRef pdp_ram_5_1_42)) + (portRef DIB0 (instanceRef pdp_ram_5_1_42)) + (portRef CSB2 (instanceRef pdp_ram_5_2_41)) + (portRef CSA2 (instanceRef pdp_ram_5_2_41)) + (portRef CSB1 (instanceRef pdp_ram_5_2_41)) + (portRef CSA1 (instanceRef pdp_ram_5_2_41)) + (portRef WEB (instanceRef pdp_ram_5_2_41)) + (portRef ADB2 (instanceRef pdp_ram_5_2_41)) + (portRef ADA2 (instanceRef pdp_ram_5_2_41)) + (portRef ADB1 (instanceRef pdp_ram_5_2_41)) + (portRef ADA1 (instanceRef pdp_ram_5_2_41)) + (portRef ADB0 (instanceRef pdp_ram_5_2_41)) + (portRef ADA0 (instanceRef pdp_ram_5_2_41)) + (portRef DIB17 (instanceRef pdp_ram_5_2_41)) + (portRef DIA17 (instanceRef pdp_ram_5_2_41)) + (portRef DIB16 (instanceRef pdp_ram_5_2_41)) + (portRef DIA16 (instanceRef pdp_ram_5_2_41)) + (portRef DIB15 (instanceRef pdp_ram_5_2_41)) + (portRef DIA15 (instanceRef pdp_ram_5_2_41)) + (portRef DIB14 (instanceRef pdp_ram_5_2_41)) + (portRef DIA14 (instanceRef pdp_ram_5_2_41)) + (portRef DIB13 (instanceRef pdp_ram_5_2_41)) + (portRef DIA13 (instanceRef pdp_ram_5_2_41)) + (portRef DIB12 (instanceRef pdp_ram_5_2_41)) + (portRef DIA12 (instanceRef pdp_ram_5_2_41)) + (portRef DIB11 (instanceRef pdp_ram_5_2_41)) + (portRef DIA11 (instanceRef pdp_ram_5_2_41)) + (portRef DIB10 (instanceRef pdp_ram_5_2_41)) + (portRef DIA10 (instanceRef pdp_ram_5_2_41)) + (portRef DIB9 (instanceRef pdp_ram_5_2_41)) + (portRef DIA9 (instanceRef pdp_ram_5_2_41)) + (portRef DIB8 (instanceRef pdp_ram_5_2_41)) + (portRef DIB7 (instanceRef pdp_ram_5_2_41)) + (portRef DIB6 (instanceRef pdp_ram_5_2_41)) + (portRef DIB5 (instanceRef pdp_ram_5_2_41)) + (portRef DIB4 (instanceRef pdp_ram_5_2_41)) + (portRef DIB3 (instanceRef pdp_ram_5_2_41)) + (portRef DIB2 (instanceRef pdp_ram_5_2_41)) + (portRef DIB1 (instanceRef pdp_ram_5_2_41)) + (portRef DIB0 (instanceRef pdp_ram_5_2_41)) + (portRef CSB2 (instanceRef pdp_ram_5_3_40)) + (portRef CSA2 (instanceRef pdp_ram_5_3_40)) + (portRef CSB1 (instanceRef pdp_ram_5_3_40)) + (portRef CSA1 (instanceRef pdp_ram_5_3_40)) + (portRef WEB (instanceRef pdp_ram_5_3_40)) + (portRef ADB2 (instanceRef pdp_ram_5_3_40)) + (portRef ADA2 (instanceRef pdp_ram_5_3_40)) + (portRef ADB1 (instanceRef pdp_ram_5_3_40)) + (portRef ADA1 (instanceRef pdp_ram_5_3_40)) + (portRef ADB0 (instanceRef pdp_ram_5_3_40)) + (portRef ADA0 (instanceRef pdp_ram_5_3_40)) + (portRef DIB17 (instanceRef pdp_ram_5_3_40)) + (portRef DIA17 (instanceRef pdp_ram_5_3_40)) + (portRef DIB16 (instanceRef pdp_ram_5_3_40)) + (portRef DIA16 (instanceRef pdp_ram_5_3_40)) + (portRef DIB15 (instanceRef pdp_ram_5_3_40)) + (portRef DIA15 (instanceRef pdp_ram_5_3_40)) + (portRef DIB14 (instanceRef pdp_ram_5_3_40)) + (portRef DIA14 (instanceRef pdp_ram_5_3_40)) + (portRef DIB13 (instanceRef pdp_ram_5_3_40)) + (portRef DIA13 (instanceRef pdp_ram_5_3_40)) + (portRef DIB12 (instanceRef pdp_ram_5_3_40)) + (portRef DIA12 (instanceRef pdp_ram_5_3_40)) + (portRef DIB11 (instanceRef pdp_ram_5_3_40)) + (portRef DIA11 (instanceRef pdp_ram_5_3_40)) + (portRef DIB10 (instanceRef pdp_ram_5_3_40)) + (portRef DIA10 (instanceRef pdp_ram_5_3_40)) + (portRef DIB9 (instanceRef pdp_ram_5_3_40)) + (portRef DIA9 (instanceRef pdp_ram_5_3_40)) + (portRef DIB8 (instanceRef pdp_ram_5_3_40)) + (portRef DIB7 (instanceRef pdp_ram_5_3_40)) + (portRef DIB6 (instanceRef pdp_ram_5_3_40)) + (portRef DIB5 (instanceRef pdp_ram_5_3_40)) + (portRef DIB4 (instanceRef pdp_ram_5_3_40)) + (portRef DIB3 (instanceRef pdp_ram_5_3_40)) + (portRef DIB2 (instanceRef pdp_ram_5_3_40)) + (portRef DIB1 (instanceRef pdp_ram_5_3_40)) + (portRef DIB0 (instanceRef pdp_ram_5_3_40)) + (portRef CSB2 (instanceRef pdp_ram_6_0_39)) + (portRef CSA2 (instanceRef pdp_ram_6_0_39)) + (portRef CSB1 (instanceRef pdp_ram_6_0_39)) + (portRef CSA1 (instanceRef pdp_ram_6_0_39)) + (portRef WEB (instanceRef pdp_ram_6_0_39)) + (portRef ADB2 (instanceRef pdp_ram_6_0_39)) + (portRef ADA2 (instanceRef pdp_ram_6_0_39)) + (portRef ADB1 (instanceRef pdp_ram_6_0_39)) + (portRef ADA1 (instanceRef pdp_ram_6_0_39)) + (portRef ADB0 (instanceRef pdp_ram_6_0_39)) + (portRef ADA0 (instanceRef pdp_ram_6_0_39)) + (portRef DIB17 (instanceRef pdp_ram_6_0_39)) + (portRef DIA17 (instanceRef pdp_ram_6_0_39)) + (portRef DIB16 (instanceRef pdp_ram_6_0_39)) + (portRef DIA16 (instanceRef pdp_ram_6_0_39)) + (portRef DIB15 (instanceRef pdp_ram_6_0_39)) + (portRef DIA15 (instanceRef pdp_ram_6_0_39)) + (portRef DIB14 (instanceRef pdp_ram_6_0_39)) + (portRef DIA14 (instanceRef pdp_ram_6_0_39)) + (portRef DIB13 (instanceRef pdp_ram_6_0_39)) + (portRef DIA13 (instanceRef pdp_ram_6_0_39)) + (portRef DIB12 (instanceRef pdp_ram_6_0_39)) + (portRef DIA12 (instanceRef pdp_ram_6_0_39)) + (portRef DIB11 (instanceRef pdp_ram_6_0_39)) + (portRef DIA11 (instanceRef pdp_ram_6_0_39)) + (portRef DIB10 (instanceRef pdp_ram_6_0_39)) + (portRef DIA10 (instanceRef pdp_ram_6_0_39)) + (portRef DIB9 (instanceRef pdp_ram_6_0_39)) + (portRef DIA9 (instanceRef pdp_ram_6_0_39)) + (portRef DIB8 (instanceRef pdp_ram_6_0_39)) + (portRef DIB7 (instanceRef pdp_ram_6_0_39)) + (portRef DIB6 (instanceRef pdp_ram_6_0_39)) + (portRef DIB5 (instanceRef pdp_ram_6_0_39)) + (portRef DIB4 (instanceRef pdp_ram_6_0_39)) + (portRef DIB3 (instanceRef pdp_ram_6_0_39)) + (portRef DIB2 (instanceRef pdp_ram_6_0_39)) + (portRef DIB1 (instanceRef pdp_ram_6_0_39)) + (portRef DIB0 (instanceRef pdp_ram_6_0_39)) + (portRef CSB2 (instanceRef pdp_ram_6_1_38)) + (portRef CSA2 (instanceRef pdp_ram_6_1_38)) + (portRef CSB1 (instanceRef pdp_ram_6_1_38)) + (portRef CSA1 (instanceRef pdp_ram_6_1_38)) + (portRef WEB (instanceRef pdp_ram_6_1_38)) + (portRef ADB2 (instanceRef pdp_ram_6_1_38)) + (portRef ADA2 (instanceRef pdp_ram_6_1_38)) + (portRef ADB1 (instanceRef pdp_ram_6_1_38)) + (portRef ADA1 (instanceRef pdp_ram_6_1_38)) + (portRef ADB0 (instanceRef pdp_ram_6_1_38)) + (portRef ADA0 (instanceRef pdp_ram_6_1_38)) + (portRef DIB17 (instanceRef pdp_ram_6_1_38)) + (portRef DIA17 (instanceRef pdp_ram_6_1_38)) + (portRef DIB16 (instanceRef pdp_ram_6_1_38)) + (portRef DIA16 (instanceRef pdp_ram_6_1_38)) + (portRef DIB15 (instanceRef pdp_ram_6_1_38)) + (portRef DIA15 (instanceRef pdp_ram_6_1_38)) + (portRef DIB14 (instanceRef pdp_ram_6_1_38)) + (portRef DIA14 (instanceRef pdp_ram_6_1_38)) + (portRef DIB13 (instanceRef pdp_ram_6_1_38)) + (portRef DIA13 (instanceRef pdp_ram_6_1_38)) + (portRef DIB12 (instanceRef pdp_ram_6_1_38)) + (portRef DIA12 (instanceRef pdp_ram_6_1_38)) + (portRef DIB11 (instanceRef pdp_ram_6_1_38)) + (portRef DIA11 (instanceRef pdp_ram_6_1_38)) + (portRef DIB10 (instanceRef pdp_ram_6_1_38)) + (portRef DIA10 (instanceRef pdp_ram_6_1_38)) + (portRef DIB9 (instanceRef pdp_ram_6_1_38)) + (portRef DIA9 (instanceRef pdp_ram_6_1_38)) + (portRef DIB8 (instanceRef pdp_ram_6_1_38)) + (portRef DIB7 (instanceRef pdp_ram_6_1_38)) + (portRef DIB6 (instanceRef pdp_ram_6_1_38)) + (portRef DIB5 (instanceRef pdp_ram_6_1_38)) + (portRef DIB4 (instanceRef pdp_ram_6_1_38)) + (portRef DIB3 (instanceRef pdp_ram_6_1_38)) + (portRef DIB2 (instanceRef pdp_ram_6_1_38)) + (portRef DIB1 (instanceRef pdp_ram_6_1_38)) + (portRef DIB0 (instanceRef pdp_ram_6_1_38)) + (portRef CSB2 (instanceRef pdp_ram_6_2_37)) + (portRef CSA2 (instanceRef pdp_ram_6_2_37)) + (portRef CSB1 (instanceRef pdp_ram_6_2_37)) + (portRef CSA1 (instanceRef pdp_ram_6_2_37)) + (portRef WEB (instanceRef pdp_ram_6_2_37)) + (portRef ADB2 (instanceRef pdp_ram_6_2_37)) + (portRef ADA2 (instanceRef pdp_ram_6_2_37)) + (portRef ADB1 (instanceRef pdp_ram_6_2_37)) + (portRef ADA1 (instanceRef pdp_ram_6_2_37)) + (portRef ADB0 (instanceRef pdp_ram_6_2_37)) + (portRef ADA0 (instanceRef pdp_ram_6_2_37)) + (portRef DIB17 (instanceRef pdp_ram_6_2_37)) + (portRef DIA17 (instanceRef pdp_ram_6_2_37)) + (portRef DIB16 (instanceRef pdp_ram_6_2_37)) + (portRef DIA16 (instanceRef pdp_ram_6_2_37)) + (portRef DIB15 (instanceRef pdp_ram_6_2_37)) + (portRef DIA15 (instanceRef pdp_ram_6_2_37)) + (portRef DIB14 (instanceRef pdp_ram_6_2_37)) + (portRef DIA14 (instanceRef pdp_ram_6_2_37)) + (portRef DIB13 (instanceRef pdp_ram_6_2_37)) + (portRef DIA13 (instanceRef pdp_ram_6_2_37)) + (portRef DIB12 (instanceRef pdp_ram_6_2_37)) + (portRef DIA12 (instanceRef pdp_ram_6_2_37)) + (portRef DIB11 (instanceRef pdp_ram_6_2_37)) + (portRef DIA11 (instanceRef pdp_ram_6_2_37)) + (portRef DIB10 (instanceRef pdp_ram_6_2_37)) + (portRef DIA10 (instanceRef pdp_ram_6_2_37)) + (portRef DIB9 (instanceRef pdp_ram_6_2_37)) + (portRef DIA9 (instanceRef pdp_ram_6_2_37)) + (portRef DIB8 (instanceRef pdp_ram_6_2_37)) + (portRef DIB7 (instanceRef pdp_ram_6_2_37)) + (portRef DIB6 (instanceRef pdp_ram_6_2_37)) + (portRef DIB5 (instanceRef pdp_ram_6_2_37)) + (portRef DIB4 (instanceRef pdp_ram_6_2_37)) + (portRef DIB3 (instanceRef pdp_ram_6_2_37)) + (portRef DIB2 (instanceRef pdp_ram_6_2_37)) + (portRef DIB1 (instanceRef pdp_ram_6_2_37)) + (portRef DIB0 (instanceRef pdp_ram_6_2_37)) + (portRef CSB2 (instanceRef pdp_ram_6_3_36)) + (portRef CSA2 (instanceRef pdp_ram_6_3_36)) + (portRef CSB1 (instanceRef pdp_ram_6_3_36)) + (portRef CSA1 (instanceRef pdp_ram_6_3_36)) + (portRef WEB (instanceRef pdp_ram_6_3_36)) + (portRef ADB2 (instanceRef pdp_ram_6_3_36)) + (portRef ADA2 (instanceRef pdp_ram_6_3_36)) + (portRef ADB1 (instanceRef pdp_ram_6_3_36)) + (portRef ADA1 (instanceRef pdp_ram_6_3_36)) + (portRef ADB0 (instanceRef pdp_ram_6_3_36)) + (portRef ADA0 (instanceRef pdp_ram_6_3_36)) + (portRef DIB17 (instanceRef pdp_ram_6_3_36)) + (portRef DIA17 (instanceRef pdp_ram_6_3_36)) + (portRef DIB16 (instanceRef pdp_ram_6_3_36)) + (portRef DIA16 (instanceRef pdp_ram_6_3_36)) + (portRef DIB15 (instanceRef pdp_ram_6_3_36)) + (portRef DIA15 (instanceRef pdp_ram_6_3_36)) + (portRef DIB14 (instanceRef pdp_ram_6_3_36)) + (portRef DIA14 (instanceRef pdp_ram_6_3_36)) + (portRef DIB13 (instanceRef pdp_ram_6_3_36)) + (portRef DIA13 (instanceRef pdp_ram_6_3_36)) + (portRef DIB12 (instanceRef pdp_ram_6_3_36)) + (portRef DIA12 (instanceRef pdp_ram_6_3_36)) + (portRef DIB11 (instanceRef pdp_ram_6_3_36)) + (portRef DIA11 (instanceRef pdp_ram_6_3_36)) + (portRef DIB10 (instanceRef pdp_ram_6_3_36)) + (portRef DIA10 (instanceRef pdp_ram_6_3_36)) + (portRef DIB9 (instanceRef pdp_ram_6_3_36)) + (portRef DIA9 (instanceRef pdp_ram_6_3_36)) + (portRef DIB8 (instanceRef pdp_ram_6_3_36)) + (portRef DIB7 (instanceRef pdp_ram_6_3_36)) + (portRef DIB6 (instanceRef pdp_ram_6_3_36)) + (portRef DIB5 (instanceRef pdp_ram_6_3_36)) + (portRef DIB4 (instanceRef pdp_ram_6_3_36)) + (portRef DIB3 (instanceRef pdp_ram_6_3_36)) + (portRef DIB2 (instanceRef pdp_ram_6_3_36)) + (portRef DIB1 (instanceRef pdp_ram_6_3_36)) + (portRef DIB0 (instanceRef pdp_ram_6_3_36)) + (portRef CSB2 (instanceRef pdp_ram_7_0_35)) + (portRef CSA2 (instanceRef pdp_ram_7_0_35)) + (portRef CSB1 (instanceRef pdp_ram_7_0_35)) + (portRef CSA1 (instanceRef pdp_ram_7_0_35)) + (portRef WEB (instanceRef pdp_ram_7_0_35)) + (portRef ADB2 (instanceRef pdp_ram_7_0_35)) + (portRef ADA2 (instanceRef pdp_ram_7_0_35)) + (portRef ADB1 (instanceRef pdp_ram_7_0_35)) + (portRef ADA1 (instanceRef pdp_ram_7_0_35)) + (portRef ADB0 (instanceRef pdp_ram_7_0_35)) + (portRef ADA0 (instanceRef pdp_ram_7_0_35)) + (portRef DIB17 (instanceRef pdp_ram_7_0_35)) + (portRef DIA17 (instanceRef pdp_ram_7_0_35)) + (portRef DIB16 (instanceRef pdp_ram_7_0_35)) + (portRef DIA16 (instanceRef pdp_ram_7_0_35)) + (portRef DIB15 (instanceRef pdp_ram_7_0_35)) + (portRef DIA15 (instanceRef pdp_ram_7_0_35)) + (portRef DIB14 (instanceRef pdp_ram_7_0_35)) + (portRef DIA14 (instanceRef pdp_ram_7_0_35)) + (portRef DIB13 (instanceRef pdp_ram_7_0_35)) + (portRef DIA13 (instanceRef pdp_ram_7_0_35)) + (portRef DIB12 (instanceRef pdp_ram_7_0_35)) + (portRef DIA12 (instanceRef pdp_ram_7_0_35)) + (portRef DIB11 (instanceRef pdp_ram_7_0_35)) + (portRef DIA11 (instanceRef pdp_ram_7_0_35)) + (portRef DIB10 (instanceRef pdp_ram_7_0_35)) + (portRef DIA10 (instanceRef pdp_ram_7_0_35)) + (portRef DIB9 (instanceRef pdp_ram_7_0_35)) + (portRef DIA9 (instanceRef pdp_ram_7_0_35)) + (portRef DIB8 (instanceRef pdp_ram_7_0_35)) + (portRef DIB7 (instanceRef pdp_ram_7_0_35)) + (portRef DIB6 (instanceRef pdp_ram_7_0_35)) + (portRef DIB5 (instanceRef pdp_ram_7_0_35)) + (portRef DIB4 (instanceRef pdp_ram_7_0_35)) + (portRef DIB3 (instanceRef pdp_ram_7_0_35)) + (portRef DIB2 (instanceRef pdp_ram_7_0_35)) + (portRef DIB1 (instanceRef pdp_ram_7_0_35)) + (portRef DIB0 (instanceRef pdp_ram_7_0_35)) + (portRef CSB2 (instanceRef pdp_ram_7_1_34)) + (portRef CSA2 (instanceRef pdp_ram_7_1_34)) + (portRef CSB1 (instanceRef pdp_ram_7_1_34)) + (portRef CSA1 (instanceRef pdp_ram_7_1_34)) + (portRef WEB (instanceRef pdp_ram_7_1_34)) + (portRef ADB2 (instanceRef pdp_ram_7_1_34)) + (portRef ADA2 (instanceRef pdp_ram_7_1_34)) + (portRef ADB1 (instanceRef pdp_ram_7_1_34)) + (portRef ADA1 (instanceRef pdp_ram_7_1_34)) + (portRef ADB0 (instanceRef pdp_ram_7_1_34)) + (portRef ADA0 (instanceRef pdp_ram_7_1_34)) + (portRef DIB17 (instanceRef pdp_ram_7_1_34)) + (portRef DIA17 (instanceRef pdp_ram_7_1_34)) + (portRef DIB16 (instanceRef pdp_ram_7_1_34)) + (portRef DIA16 (instanceRef pdp_ram_7_1_34)) + (portRef DIB15 (instanceRef pdp_ram_7_1_34)) + (portRef DIA15 (instanceRef pdp_ram_7_1_34)) + (portRef DIB14 (instanceRef pdp_ram_7_1_34)) + (portRef DIA14 (instanceRef pdp_ram_7_1_34)) + (portRef DIB13 (instanceRef pdp_ram_7_1_34)) + (portRef DIA13 (instanceRef pdp_ram_7_1_34)) + (portRef DIB12 (instanceRef pdp_ram_7_1_34)) + (portRef DIA12 (instanceRef pdp_ram_7_1_34)) + (portRef DIB11 (instanceRef pdp_ram_7_1_34)) + (portRef DIA11 (instanceRef pdp_ram_7_1_34)) + (portRef DIB10 (instanceRef pdp_ram_7_1_34)) + (portRef DIA10 (instanceRef pdp_ram_7_1_34)) + (portRef DIB9 (instanceRef pdp_ram_7_1_34)) + (portRef DIA9 (instanceRef pdp_ram_7_1_34)) + (portRef DIB8 (instanceRef pdp_ram_7_1_34)) + (portRef DIB7 (instanceRef pdp_ram_7_1_34)) + (portRef DIB6 (instanceRef pdp_ram_7_1_34)) + (portRef DIB5 (instanceRef pdp_ram_7_1_34)) + (portRef DIB4 (instanceRef pdp_ram_7_1_34)) + (portRef DIB3 (instanceRef pdp_ram_7_1_34)) + (portRef DIB2 (instanceRef pdp_ram_7_1_34)) + (portRef DIB1 (instanceRef pdp_ram_7_1_34)) + (portRef DIB0 (instanceRef pdp_ram_7_1_34)) + (portRef CSB2 (instanceRef pdp_ram_7_2_33)) + (portRef CSA2 (instanceRef pdp_ram_7_2_33)) + (portRef CSB1 (instanceRef pdp_ram_7_2_33)) + (portRef CSA1 (instanceRef pdp_ram_7_2_33)) + (portRef WEB (instanceRef pdp_ram_7_2_33)) + (portRef ADB2 (instanceRef pdp_ram_7_2_33)) + (portRef ADA2 (instanceRef pdp_ram_7_2_33)) + (portRef ADB1 (instanceRef pdp_ram_7_2_33)) + (portRef ADA1 (instanceRef pdp_ram_7_2_33)) + (portRef ADB0 (instanceRef pdp_ram_7_2_33)) + (portRef ADA0 (instanceRef pdp_ram_7_2_33)) + (portRef DIB17 (instanceRef pdp_ram_7_2_33)) + (portRef DIA17 (instanceRef pdp_ram_7_2_33)) + (portRef DIB16 (instanceRef pdp_ram_7_2_33)) + (portRef DIA16 (instanceRef pdp_ram_7_2_33)) + (portRef DIB15 (instanceRef pdp_ram_7_2_33)) + (portRef DIA15 (instanceRef pdp_ram_7_2_33)) + (portRef DIB14 (instanceRef pdp_ram_7_2_33)) + (portRef DIA14 (instanceRef pdp_ram_7_2_33)) + (portRef DIB13 (instanceRef pdp_ram_7_2_33)) + (portRef DIA13 (instanceRef pdp_ram_7_2_33)) + (portRef DIB12 (instanceRef pdp_ram_7_2_33)) + (portRef DIA12 (instanceRef pdp_ram_7_2_33)) + (portRef DIB11 (instanceRef pdp_ram_7_2_33)) + (portRef DIA11 (instanceRef pdp_ram_7_2_33)) + (portRef DIB10 (instanceRef pdp_ram_7_2_33)) + (portRef DIA10 (instanceRef pdp_ram_7_2_33)) + (portRef DIB9 (instanceRef pdp_ram_7_2_33)) + (portRef DIA9 (instanceRef pdp_ram_7_2_33)) + (portRef DIB8 (instanceRef pdp_ram_7_2_33)) + (portRef DIB7 (instanceRef pdp_ram_7_2_33)) + (portRef DIB6 (instanceRef pdp_ram_7_2_33)) + (portRef DIB5 (instanceRef pdp_ram_7_2_33)) + (portRef DIB4 (instanceRef pdp_ram_7_2_33)) + (portRef DIB3 (instanceRef pdp_ram_7_2_33)) + (portRef DIB2 (instanceRef pdp_ram_7_2_33)) + (portRef DIB1 (instanceRef pdp_ram_7_2_33)) + (portRef DIB0 (instanceRef pdp_ram_7_2_33)) + (portRef CSB2 (instanceRef pdp_ram_7_3_32)) + (portRef CSA2 (instanceRef pdp_ram_7_3_32)) + (portRef CSB1 (instanceRef pdp_ram_7_3_32)) + (portRef CSA1 (instanceRef pdp_ram_7_3_32)) + (portRef WEB (instanceRef pdp_ram_7_3_32)) + (portRef ADB2 (instanceRef pdp_ram_7_3_32)) + (portRef ADA2 (instanceRef pdp_ram_7_3_32)) + (portRef ADB1 (instanceRef pdp_ram_7_3_32)) + (portRef ADA1 (instanceRef pdp_ram_7_3_32)) + (portRef ADB0 (instanceRef pdp_ram_7_3_32)) + (portRef ADA0 (instanceRef pdp_ram_7_3_32)) + (portRef DIB17 (instanceRef pdp_ram_7_3_32)) + (portRef DIA17 (instanceRef pdp_ram_7_3_32)) + (portRef DIB16 (instanceRef pdp_ram_7_3_32)) + (portRef DIA16 (instanceRef pdp_ram_7_3_32)) + (portRef DIB15 (instanceRef pdp_ram_7_3_32)) + (portRef DIA15 (instanceRef pdp_ram_7_3_32)) + (portRef DIB14 (instanceRef pdp_ram_7_3_32)) + (portRef DIA14 (instanceRef pdp_ram_7_3_32)) + (portRef DIB13 (instanceRef pdp_ram_7_3_32)) + (portRef DIA13 (instanceRef pdp_ram_7_3_32)) + (portRef DIB12 (instanceRef pdp_ram_7_3_32)) + (portRef DIA12 (instanceRef pdp_ram_7_3_32)) + (portRef DIB11 (instanceRef pdp_ram_7_3_32)) + (portRef DIA11 (instanceRef pdp_ram_7_3_32)) + (portRef DIB10 (instanceRef pdp_ram_7_3_32)) + (portRef DIA10 (instanceRef pdp_ram_7_3_32)) + (portRef DIB9 (instanceRef pdp_ram_7_3_32)) + (portRef DIA9 (instanceRef pdp_ram_7_3_32)) + (portRef DIB8 (instanceRef pdp_ram_7_3_32)) + (portRef DIB7 (instanceRef pdp_ram_7_3_32)) + (portRef DIB6 (instanceRef pdp_ram_7_3_32)) + (portRef DIB5 (instanceRef pdp_ram_7_3_32)) + (portRef DIB4 (instanceRef pdp_ram_7_3_32)) + (portRef DIB3 (instanceRef pdp_ram_7_3_32)) + (portRef DIB2 (instanceRef pdp_ram_7_3_32)) + (portRef DIB1 (instanceRef pdp_ram_7_3_32)) + (portRef DIB0 (instanceRef pdp_ram_7_3_32)) + (portRef CSB2 (instanceRef pdp_ram_8_0_31)) + (portRef CSA2 (instanceRef pdp_ram_8_0_31)) + (portRef CSB1 (instanceRef pdp_ram_8_0_31)) + (portRef CSA1 (instanceRef pdp_ram_8_0_31)) + (portRef WEB (instanceRef pdp_ram_8_0_31)) + (portRef ADB2 (instanceRef pdp_ram_8_0_31)) + (portRef ADA2 (instanceRef pdp_ram_8_0_31)) + (portRef ADB1 (instanceRef pdp_ram_8_0_31)) + (portRef ADA1 (instanceRef pdp_ram_8_0_31)) + (portRef ADB0 (instanceRef pdp_ram_8_0_31)) + (portRef ADA0 (instanceRef pdp_ram_8_0_31)) + (portRef DIB17 (instanceRef pdp_ram_8_0_31)) + (portRef DIA17 (instanceRef pdp_ram_8_0_31)) + (portRef DIB16 (instanceRef pdp_ram_8_0_31)) + (portRef DIA16 (instanceRef pdp_ram_8_0_31)) + (portRef DIB15 (instanceRef pdp_ram_8_0_31)) + (portRef DIA15 (instanceRef pdp_ram_8_0_31)) + (portRef DIB14 (instanceRef pdp_ram_8_0_31)) + (portRef DIA14 (instanceRef pdp_ram_8_0_31)) + (portRef DIB13 (instanceRef pdp_ram_8_0_31)) + (portRef DIA13 (instanceRef pdp_ram_8_0_31)) + (portRef DIB12 (instanceRef pdp_ram_8_0_31)) + (portRef DIA12 (instanceRef pdp_ram_8_0_31)) + (portRef DIB11 (instanceRef pdp_ram_8_0_31)) + (portRef DIA11 (instanceRef pdp_ram_8_0_31)) + (portRef DIB10 (instanceRef pdp_ram_8_0_31)) + (portRef DIA10 (instanceRef pdp_ram_8_0_31)) + (portRef DIB9 (instanceRef pdp_ram_8_0_31)) + (portRef DIA9 (instanceRef pdp_ram_8_0_31)) + (portRef DIB8 (instanceRef pdp_ram_8_0_31)) + (portRef DIB7 (instanceRef pdp_ram_8_0_31)) + (portRef DIB6 (instanceRef pdp_ram_8_0_31)) + (portRef DIB5 (instanceRef pdp_ram_8_0_31)) + (portRef DIB4 (instanceRef pdp_ram_8_0_31)) + (portRef DIB3 (instanceRef pdp_ram_8_0_31)) + (portRef DIB2 (instanceRef pdp_ram_8_0_31)) + (portRef DIB1 (instanceRef pdp_ram_8_0_31)) + (portRef DIB0 (instanceRef pdp_ram_8_0_31)) + (portRef CSB2 (instanceRef pdp_ram_8_1_30)) + (portRef CSA2 (instanceRef pdp_ram_8_1_30)) + (portRef CSB1 (instanceRef pdp_ram_8_1_30)) + (portRef CSA1 (instanceRef pdp_ram_8_1_30)) + (portRef WEB (instanceRef pdp_ram_8_1_30)) + (portRef ADB2 (instanceRef pdp_ram_8_1_30)) + (portRef ADA2 (instanceRef pdp_ram_8_1_30)) + (portRef ADB1 (instanceRef pdp_ram_8_1_30)) + (portRef ADA1 (instanceRef pdp_ram_8_1_30)) + (portRef ADB0 (instanceRef pdp_ram_8_1_30)) + (portRef ADA0 (instanceRef pdp_ram_8_1_30)) + (portRef DIB17 (instanceRef pdp_ram_8_1_30)) + (portRef DIA17 (instanceRef pdp_ram_8_1_30)) + (portRef DIB16 (instanceRef pdp_ram_8_1_30)) + (portRef DIA16 (instanceRef pdp_ram_8_1_30)) + (portRef DIB15 (instanceRef pdp_ram_8_1_30)) + (portRef DIA15 (instanceRef pdp_ram_8_1_30)) + (portRef DIB14 (instanceRef pdp_ram_8_1_30)) + (portRef DIA14 (instanceRef pdp_ram_8_1_30)) + (portRef DIB13 (instanceRef pdp_ram_8_1_30)) + (portRef DIA13 (instanceRef pdp_ram_8_1_30)) + (portRef DIB12 (instanceRef pdp_ram_8_1_30)) + (portRef DIA12 (instanceRef pdp_ram_8_1_30)) + (portRef DIB11 (instanceRef pdp_ram_8_1_30)) + (portRef DIA11 (instanceRef pdp_ram_8_1_30)) + (portRef DIB10 (instanceRef pdp_ram_8_1_30)) + (portRef DIA10 (instanceRef pdp_ram_8_1_30)) + (portRef DIB9 (instanceRef pdp_ram_8_1_30)) + (portRef DIA9 (instanceRef pdp_ram_8_1_30)) + (portRef DIB8 (instanceRef pdp_ram_8_1_30)) + (portRef DIB7 (instanceRef pdp_ram_8_1_30)) + (portRef DIB6 (instanceRef pdp_ram_8_1_30)) + (portRef DIB5 (instanceRef pdp_ram_8_1_30)) + (portRef DIB4 (instanceRef pdp_ram_8_1_30)) + (portRef DIB3 (instanceRef pdp_ram_8_1_30)) + (portRef DIB2 (instanceRef pdp_ram_8_1_30)) + (portRef DIB1 (instanceRef pdp_ram_8_1_30)) + (portRef DIB0 (instanceRef pdp_ram_8_1_30)) + (portRef CSB2 (instanceRef pdp_ram_8_2_29)) + (portRef CSA2 (instanceRef pdp_ram_8_2_29)) + (portRef CSB1 (instanceRef pdp_ram_8_2_29)) + (portRef CSA1 (instanceRef pdp_ram_8_2_29)) + (portRef WEB (instanceRef pdp_ram_8_2_29)) + (portRef ADB2 (instanceRef pdp_ram_8_2_29)) + (portRef ADA2 (instanceRef pdp_ram_8_2_29)) + (portRef ADB1 (instanceRef pdp_ram_8_2_29)) + (portRef ADA1 (instanceRef pdp_ram_8_2_29)) + (portRef ADB0 (instanceRef pdp_ram_8_2_29)) + (portRef ADA0 (instanceRef pdp_ram_8_2_29)) + (portRef DIB17 (instanceRef pdp_ram_8_2_29)) + (portRef DIA17 (instanceRef pdp_ram_8_2_29)) + (portRef DIB16 (instanceRef pdp_ram_8_2_29)) + (portRef DIA16 (instanceRef pdp_ram_8_2_29)) + (portRef DIB15 (instanceRef pdp_ram_8_2_29)) + (portRef DIA15 (instanceRef pdp_ram_8_2_29)) + (portRef DIB14 (instanceRef pdp_ram_8_2_29)) + (portRef DIA14 (instanceRef pdp_ram_8_2_29)) + (portRef DIB13 (instanceRef pdp_ram_8_2_29)) + (portRef DIA13 (instanceRef pdp_ram_8_2_29)) + (portRef DIB12 (instanceRef pdp_ram_8_2_29)) + (portRef DIA12 (instanceRef pdp_ram_8_2_29)) + (portRef DIB11 (instanceRef pdp_ram_8_2_29)) + (portRef DIA11 (instanceRef pdp_ram_8_2_29)) + (portRef DIB10 (instanceRef pdp_ram_8_2_29)) + (portRef DIA10 (instanceRef pdp_ram_8_2_29)) + (portRef DIB9 (instanceRef pdp_ram_8_2_29)) + (portRef DIA9 (instanceRef pdp_ram_8_2_29)) + (portRef DIB8 (instanceRef pdp_ram_8_2_29)) + (portRef DIB7 (instanceRef pdp_ram_8_2_29)) + (portRef DIB6 (instanceRef pdp_ram_8_2_29)) + (portRef DIB5 (instanceRef pdp_ram_8_2_29)) + (portRef DIB4 (instanceRef pdp_ram_8_2_29)) + (portRef DIB3 (instanceRef pdp_ram_8_2_29)) + (portRef DIB2 (instanceRef pdp_ram_8_2_29)) + (portRef DIB1 (instanceRef pdp_ram_8_2_29)) + (portRef DIB0 (instanceRef pdp_ram_8_2_29)) + (portRef CSB2 (instanceRef pdp_ram_8_3_28)) + (portRef CSA2 (instanceRef pdp_ram_8_3_28)) + (portRef CSB1 (instanceRef pdp_ram_8_3_28)) + (portRef CSA1 (instanceRef pdp_ram_8_3_28)) + (portRef WEB (instanceRef pdp_ram_8_3_28)) + (portRef ADB2 (instanceRef pdp_ram_8_3_28)) + (portRef ADA2 (instanceRef pdp_ram_8_3_28)) + (portRef ADB1 (instanceRef pdp_ram_8_3_28)) + (portRef ADA1 (instanceRef pdp_ram_8_3_28)) + (portRef ADB0 (instanceRef pdp_ram_8_3_28)) + (portRef ADA0 (instanceRef pdp_ram_8_3_28)) + (portRef DIB17 (instanceRef pdp_ram_8_3_28)) + (portRef DIA17 (instanceRef pdp_ram_8_3_28)) + (portRef DIB16 (instanceRef pdp_ram_8_3_28)) + (portRef DIA16 (instanceRef pdp_ram_8_3_28)) + (portRef DIB15 (instanceRef pdp_ram_8_3_28)) + (portRef DIA15 (instanceRef pdp_ram_8_3_28)) + (portRef DIB14 (instanceRef pdp_ram_8_3_28)) + (portRef DIA14 (instanceRef pdp_ram_8_3_28)) + (portRef DIB13 (instanceRef pdp_ram_8_3_28)) + (portRef DIA13 (instanceRef pdp_ram_8_3_28)) + (portRef DIB12 (instanceRef pdp_ram_8_3_28)) + (portRef DIA12 (instanceRef pdp_ram_8_3_28)) + (portRef DIB11 (instanceRef pdp_ram_8_3_28)) + (portRef DIA11 (instanceRef pdp_ram_8_3_28)) + (portRef DIB10 (instanceRef pdp_ram_8_3_28)) + (portRef DIA10 (instanceRef pdp_ram_8_3_28)) + (portRef DIB9 (instanceRef pdp_ram_8_3_28)) + (portRef DIA9 (instanceRef pdp_ram_8_3_28)) + (portRef DIB8 (instanceRef pdp_ram_8_3_28)) + (portRef DIB7 (instanceRef pdp_ram_8_3_28)) + (portRef DIB6 (instanceRef pdp_ram_8_3_28)) + (portRef DIB5 (instanceRef pdp_ram_8_3_28)) + (portRef DIB4 (instanceRef pdp_ram_8_3_28)) + (portRef DIB3 (instanceRef pdp_ram_8_3_28)) + (portRef DIB2 (instanceRef pdp_ram_8_3_28)) + (portRef DIB1 (instanceRef pdp_ram_8_3_28)) + (portRef DIB0 (instanceRef pdp_ram_8_3_28)) + (portRef CSB2 (instanceRef pdp_ram_9_0_27)) + (portRef CSA2 (instanceRef pdp_ram_9_0_27)) + (portRef CSB1 (instanceRef pdp_ram_9_0_27)) + (portRef CSA1 (instanceRef pdp_ram_9_0_27)) + (portRef WEB (instanceRef pdp_ram_9_0_27)) + (portRef ADB2 (instanceRef pdp_ram_9_0_27)) + (portRef ADA2 (instanceRef pdp_ram_9_0_27)) + (portRef ADB1 (instanceRef pdp_ram_9_0_27)) + (portRef ADA1 (instanceRef pdp_ram_9_0_27)) + (portRef ADB0 (instanceRef pdp_ram_9_0_27)) + (portRef ADA0 (instanceRef pdp_ram_9_0_27)) + (portRef DIB17 (instanceRef pdp_ram_9_0_27)) + (portRef DIA17 (instanceRef pdp_ram_9_0_27)) + (portRef DIB16 (instanceRef pdp_ram_9_0_27)) + (portRef DIA16 (instanceRef pdp_ram_9_0_27)) + (portRef DIB15 (instanceRef pdp_ram_9_0_27)) + (portRef DIA15 (instanceRef pdp_ram_9_0_27)) + (portRef DIB14 (instanceRef pdp_ram_9_0_27)) + (portRef DIA14 (instanceRef pdp_ram_9_0_27)) + (portRef DIB13 (instanceRef pdp_ram_9_0_27)) + (portRef DIA13 (instanceRef pdp_ram_9_0_27)) + (portRef DIB12 (instanceRef pdp_ram_9_0_27)) + (portRef DIA12 (instanceRef pdp_ram_9_0_27)) + (portRef DIB11 (instanceRef pdp_ram_9_0_27)) + (portRef DIA11 (instanceRef pdp_ram_9_0_27)) + (portRef DIB10 (instanceRef pdp_ram_9_0_27)) + (portRef DIA10 (instanceRef pdp_ram_9_0_27)) + (portRef DIB9 (instanceRef pdp_ram_9_0_27)) + (portRef DIA9 (instanceRef pdp_ram_9_0_27)) + (portRef DIB8 (instanceRef pdp_ram_9_0_27)) + (portRef DIB7 (instanceRef pdp_ram_9_0_27)) + (portRef DIB6 (instanceRef pdp_ram_9_0_27)) + (portRef DIB5 (instanceRef pdp_ram_9_0_27)) + (portRef DIB4 (instanceRef pdp_ram_9_0_27)) + (portRef DIB3 (instanceRef pdp_ram_9_0_27)) + (portRef DIB2 (instanceRef pdp_ram_9_0_27)) + (portRef DIB1 (instanceRef pdp_ram_9_0_27)) + (portRef DIB0 (instanceRef pdp_ram_9_0_27)) + (portRef CSB2 (instanceRef pdp_ram_9_1_26)) + (portRef CSA2 (instanceRef pdp_ram_9_1_26)) + (portRef CSB1 (instanceRef pdp_ram_9_1_26)) + (portRef CSA1 (instanceRef pdp_ram_9_1_26)) + (portRef WEB (instanceRef pdp_ram_9_1_26)) + (portRef ADB2 (instanceRef pdp_ram_9_1_26)) + (portRef ADA2 (instanceRef pdp_ram_9_1_26)) + (portRef ADB1 (instanceRef pdp_ram_9_1_26)) + (portRef ADA1 (instanceRef pdp_ram_9_1_26)) + (portRef ADB0 (instanceRef pdp_ram_9_1_26)) + (portRef ADA0 (instanceRef pdp_ram_9_1_26)) + (portRef DIB17 (instanceRef pdp_ram_9_1_26)) + (portRef DIA17 (instanceRef pdp_ram_9_1_26)) + (portRef DIB16 (instanceRef pdp_ram_9_1_26)) + (portRef DIA16 (instanceRef pdp_ram_9_1_26)) + (portRef DIB15 (instanceRef pdp_ram_9_1_26)) + (portRef DIA15 (instanceRef pdp_ram_9_1_26)) + (portRef DIB14 (instanceRef pdp_ram_9_1_26)) + (portRef DIA14 (instanceRef pdp_ram_9_1_26)) + (portRef DIB13 (instanceRef pdp_ram_9_1_26)) + (portRef DIA13 (instanceRef pdp_ram_9_1_26)) + (portRef DIB12 (instanceRef pdp_ram_9_1_26)) + (portRef DIA12 (instanceRef pdp_ram_9_1_26)) + (portRef DIB11 (instanceRef pdp_ram_9_1_26)) + (portRef DIA11 (instanceRef pdp_ram_9_1_26)) + (portRef DIB10 (instanceRef pdp_ram_9_1_26)) + (portRef DIA10 (instanceRef pdp_ram_9_1_26)) + (portRef DIB9 (instanceRef pdp_ram_9_1_26)) + (portRef DIA9 (instanceRef pdp_ram_9_1_26)) + (portRef DIB8 (instanceRef pdp_ram_9_1_26)) + (portRef DIB7 (instanceRef pdp_ram_9_1_26)) + (portRef DIB6 (instanceRef pdp_ram_9_1_26)) + (portRef DIB5 (instanceRef pdp_ram_9_1_26)) + (portRef DIB4 (instanceRef pdp_ram_9_1_26)) + (portRef DIB3 (instanceRef pdp_ram_9_1_26)) + (portRef DIB2 (instanceRef pdp_ram_9_1_26)) + (portRef DIB1 (instanceRef pdp_ram_9_1_26)) + (portRef DIB0 (instanceRef pdp_ram_9_1_26)) + (portRef CSB2 (instanceRef pdp_ram_9_2_25)) + (portRef CSA2 (instanceRef pdp_ram_9_2_25)) + (portRef CSB1 (instanceRef pdp_ram_9_2_25)) + (portRef CSA1 (instanceRef pdp_ram_9_2_25)) + (portRef WEB (instanceRef pdp_ram_9_2_25)) + (portRef ADB2 (instanceRef pdp_ram_9_2_25)) + (portRef ADA2 (instanceRef pdp_ram_9_2_25)) + (portRef ADB1 (instanceRef pdp_ram_9_2_25)) + (portRef ADA1 (instanceRef pdp_ram_9_2_25)) + (portRef ADB0 (instanceRef pdp_ram_9_2_25)) + (portRef ADA0 (instanceRef pdp_ram_9_2_25)) + (portRef DIB17 (instanceRef pdp_ram_9_2_25)) + (portRef DIA17 (instanceRef pdp_ram_9_2_25)) + (portRef DIB16 (instanceRef pdp_ram_9_2_25)) + (portRef DIA16 (instanceRef pdp_ram_9_2_25)) + (portRef DIB15 (instanceRef pdp_ram_9_2_25)) + (portRef DIA15 (instanceRef pdp_ram_9_2_25)) + (portRef DIB14 (instanceRef pdp_ram_9_2_25)) + (portRef DIA14 (instanceRef pdp_ram_9_2_25)) + (portRef DIB13 (instanceRef pdp_ram_9_2_25)) + (portRef DIA13 (instanceRef pdp_ram_9_2_25)) + (portRef DIB12 (instanceRef pdp_ram_9_2_25)) + (portRef DIA12 (instanceRef pdp_ram_9_2_25)) + (portRef DIB11 (instanceRef pdp_ram_9_2_25)) + (portRef DIA11 (instanceRef pdp_ram_9_2_25)) + (portRef DIB10 (instanceRef pdp_ram_9_2_25)) + (portRef DIA10 (instanceRef pdp_ram_9_2_25)) + (portRef DIB9 (instanceRef pdp_ram_9_2_25)) + (portRef DIA9 (instanceRef pdp_ram_9_2_25)) + (portRef DIB8 (instanceRef pdp_ram_9_2_25)) + (portRef DIB7 (instanceRef pdp_ram_9_2_25)) + (portRef DIB6 (instanceRef pdp_ram_9_2_25)) + (portRef DIB5 (instanceRef pdp_ram_9_2_25)) + (portRef DIB4 (instanceRef pdp_ram_9_2_25)) + (portRef DIB3 (instanceRef pdp_ram_9_2_25)) + (portRef DIB2 (instanceRef pdp_ram_9_2_25)) + (portRef DIB1 (instanceRef pdp_ram_9_2_25)) + (portRef DIB0 (instanceRef pdp_ram_9_2_25)) + (portRef CSB2 (instanceRef pdp_ram_9_3_24)) + (portRef CSA2 (instanceRef pdp_ram_9_3_24)) + (portRef CSB1 (instanceRef pdp_ram_9_3_24)) + (portRef CSA1 (instanceRef pdp_ram_9_3_24)) + (portRef WEB (instanceRef pdp_ram_9_3_24)) + (portRef ADB2 (instanceRef pdp_ram_9_3_24)) + (portRef ADA2 (instanceRef pdp_ram_9_3_24)) + (portRef ADB1 (instanceRef pdp_ram_9_3_24)) + (portRef ADA1 (instanceRef pdp_ram_9_3_24)) + (portRef ADB0 (instanceRef pdp_ram_9_3_24)) + (portRef ADA0 (instanceRef pdp_ram_9_3_24)) + (portRef DIB17 (instanceRef pdp_ram_9_3_24)) + (portRef DIA17 (instanceRef pdp_ram_9_3_24)) + (portRef DIB16 (instanceRef pdp_ram_9_3_24)) + (portRef DIA16 (instanceRef pdp_ram_9_3_24)) + (portRef DIB15 (instanceRef pdp_ram_9_3_24)) + (portRef DIA15 (instanceRef pdp_ram_9_3_24)) + (portRef DIB14 (instanceRef pdp_ram_9_3_24)) + (portRef DIA14 (instanceRef pdp_ram_9_3_24)) + (portRef DIB13 (instanceRef pdp_ram_9_3_24)) + (portRef DIA13 (instanceRef pdp_ram_9_3_24)) + (portRef DIB12 (instanceRef pdp_ram_9_3_24)) + (portRef DIA12 (instanceRef pdp_ram_9_3_24)) + (portRef DIB11 (instanceRef pdp_ram_9_3_24)) + (portRef DIA11 (instanceRef pdp_ram_9_3_24)) + (portRef DIB10 (instanceRef pdp_ram_9_3_24)) + (portRef DIA10 (instanceRef pdp_ram_9_3_24)) + (portRef DIB9 (instanceRef pdp_ram_9_3_24)) + (portRef DIA9 (instanceRef pdp_ram_9_3_24)) + (portRef DIB8 (instanceRef pdp_ram_9_3_24)) + (portRef DIB7 (instanceRef pdp_ram_9_3_24)) + (portRef DIB6 (instanceRef pdp_ram_9_3_24)) + (portRef DIB5 (instanceRef pdp_ram_9_3_24)) + (portRef DIB4 (instanceRef pdp_ram_9_3_24)) + (portRef DIB3 (instanceRef pdp_ram_9_3_24)) + (portRef DIB2 (instanceRef pdp_ram_9_3_24)) + (portRef DIB1 (instanceRef pdp_ram_9_3_24)) + (portRef DIB0 (instanceRef pdp_ram_9_3_24)) + (portRef CSB2 (instanceRef pdp_ram_10_0_23)) + (portRef CSA2 (instanceRef pdp_ram_10_0_23)) + (portRef CSB1 (instanceRef pdp_ram_10_0_23)) + (portRef CSA1 (instanceRef pdp_ram_10_0_23)) + (portRef WEB (instanceRef pdp_ram_10_0_23)) + (portRef ADB2 (instanceRef pdp_ram_10_0_23)) + (portRef ADA2 (instanceRef pdp_ram_10_0_23)) + (portRef ADB1 (instanceRef pdp_ram_10_0_23)) + (portRef ADA1 (instanceRef pdp_ram_10_0_23)) + (portRef ADB0 (instanceRef pdp_ram_10_0_23)) + (portRef ADA0 (instanceRef pdp_ram_10_0_23)) + (portRef DIB17 (instanceRef pdp_ram_10_0_23)) + (portRef DIA17 (instanceRef pdp_ram_10_0_23)) + (portRef DIB16 (instanceRef pdp_ram_10_0_23)) + (portRef DIA16 (instanceRef pdp_ram_10_0_23)) + (portRef DIB15 (instanceRef pdp_ram_10_0_23)) + (portRef DIA15 (instanceRef pdp_ram_10_0_23)) + (portRef DIB14 (instanceRef pdp_ram_10_0_23)) + (portRef DIA14 (instanceRef pdp_ram_10_0_23)) + (portRef DIB13 (instanceRef pdp_ram_10_0_23)) + (portRef DIA13 (instanceRef pdp_ram_10_0_23)) + (portRef DIB12 (instanceRef pdp_ram_10_0_23)) + (portRef DIA12 (instanceRef pdp_ram_10_0_23)) + (portRef DIB11 (instanceRef pdp_ram_10_0_23)) + (portRef DIA11 (instanceRef pdp_ram_10_0_23)) + (portRef DIB10 (instanceRef pdp_ram_10_0_23)) + (portRef DIA10 (instanceRef pdp_ram_10_0_23)) + (portRef DIB9 (instanceRef pdp_ram_10_0_23)) + (portRef DIA9 (instanceRef pdp_ram_10_0_23)) + (portRef DIB8 (instanceRef pdp_ram_10_0_23)) + (portRef DIB7 (instanceRef pdp_ram_10_0_23)) + (portRef DIB6 (instanceRef pdp_ram_10_0_23)) + (portRef DIB5 (instanceRef pdp_ram_10_0_23)) + (portRef DIB4 (instanceRef pdp_ram_10_0_23)) + (portRef DIB3 (instanceRef pdp_ram_10_0_23)) + (portRef DIB2 (instanceRef pdp_ram_10_0_23)) + (portRef DIB1 (instanceRef pdp_ram_10_0_23)) + (portRef DIB0 (instanceRef pdp_ram_10_0_23)) + (portRef CSB2 (instanceRef pdp_ram_10_1_22)) + (portRef CSA2 (instanceRef pdp_ram_10_1_22)) + (portRef CSB1 (instanceRef pdp_ram_10_1_22)) + (portRef CSA1 (instanceRef pdp_ram_10_1_22)) + (portRef WEB (instanceRef pdp_ram_10_1_22)) + (portRef ADB2 (instanceRef pdp_ram_10_1_22)) + (portRef ADA2 (instanceRef pdp_ram_10_1_22)) + (portRef ADB1 (instanceRef pdp_ram_10_1_22)) + (portRef ADA1 (instanceRef pdp_ram_10_1_22)) + (portRef ADB0 (instanceRef pdp_ram_10_1_22)) + (portRef ADA0 (instanceRef pdp_ram_10_1_22)) + (portRef DIB17 (instanceRef pdp_ram_10_1_22)) + (portRef DIA17 (instanceRef pdp_ram_10_1_22)) + (portRef DIB16 (instanceRef pdp_ram_10_1_22)) + (portRef DIA16 (instanceRef pdp_ram_10_1_22)) + (portRef DIB15 (instanceRef pdp_ram_10_1_22)) + (portRef DIA15 (instanceRef pdp_ram_10_1_22)) + (portRef DIB14 (instanceRef pdp_ram_10_1_22)) + (portRef DIA14 (instanceRef pdp_ram_10_1_22)) + (portRef DIB13 (instanceRef pdp_ram_10_1_22)) + (portRef DIA13 (instanceRef pdp_ram_10_1_22)) + (portRef DIB12 (instanceRef pdp_ram_10_1_22)) + (portRef DIA12 (instanceRef pdp_ram_10_1_22)) + (portRef DIB11 (instanceRef pdp_ram_10_1_22)) + (portRef DIA11 (instanceRef pdp_ram_10_1_22)) + (portRef DIB10 (instanceRef pdp_ram_10_1_22)) + (portRef DIA10 (instanceRef pdp_ram_10_1_22)) + (portRef DIB9 (instanceRef pdp_ram_10_1_22)) + (portRef DIA9 (instanceRef pdp_ram_10_1_22)) + (portRef DIB8 (instanceRef pdp_ram_10_1_22)) + (portRef DIB7 (instanceRef pdp_ram_10_1_22)) + (portRef DIB6 (instanceRef pdp_ram_10_1_22)) + (portRef DIB5 (instanceRef pdp_ram_10_1_22)) + (portRef DIB4 (instanceRef pdp_ram_10_1_22)) + (portRef DIB3 (instanceRef pdp_ram_10_1_22)) + (portRef DIB2 (instanceRef pdp_ram_10_1_22)) + (portRef DIB1 (instanceRef pdp_ram_10_1_22)) + (portRef DIB0 (instanceRef pdp_ram_10_1_22)) + (portRef CSB2 (instanceRef pdp_ram_10_2_21)) + (portRef CSA2 (instanceRef pdp_ram_10_2_21)) + (portRef CSB1 (instanceRef pdp_ram_10_2_21)) + (portRef CSA1 (instanceRef pdp_ram_10_2_21)) + (portRef WEB (instanceRef pdp_ram_10_2_21)) + (portRef ADB2 (instanceRef pdp_ram_10_2_21)) + (portRef ADA2 (instanceRef pdp_ram_10_2_21)) + (portRef ADB1 (instanceRef pdp_ram_10_2_21)) + (portRef ADA1 (instanceRef pdp_ram_10_2_21)) + (portRef ADB0 (instanceRef pdp_ram_10_2_21)) + (portRef ADA0 (instanceRef pdp_ram_10_2_21)) + (portRef DIB17 (instanceRef pdp_ram_10_2_21)) + (portRef DIA17 (instanceRef pdp_ram_10_2_21)) + (portRef DIB16 (instanceRef pdp_ram_10_2_21)) + (portRef DIA16 (instanceRef pdp_ram_10_2_21)) + (portRef DIB15 (instanceRef pdp_ram_10_2_21)) + (portRef DIA15 (instanceRef pdp_ram_10_2_21)) + (portRef DIB14 (instanceRef pdp_ram_10_2_21)) + (portRef DIA14 (instanceRef pdp_ram_10_2_21)) + (portRef DIB13 (instanceRef pdp_ram_10_2_21)) + (portRef DIA13 (instanceRef pdp_ram_10_2_21)) + (portRef DIB12 (instanceRef pdp_ram_10_2_21)) + (portRef DIA12 (instanceRef pdp_ram_10_2_21)) + (portRef DIB11 (instanceRef pdp_ram_10_2_21)) + (portRef DIA11 (instanceRef pdp_ram_10_2_21)) + (portRef DIB10 (instanceRef pdp_ram_10_2_21)) + (portRef DIA10 (instanceRef pdp_ram_10_2_21)) + (portRef DIB9 (instanceRef pdp_ram_10_2_21)) + (portRef DIA9 (instanceRef pdp_ram_10_2_21)) + (portRef DIB8 (instanceRef pdp_ram_10_2_21)) + (portRef DIB7 (instanceRef pdp_ram_10_2_21)) + (portRef DIB6 (instanceRef pdp_ram_10_2_21)) + (portRef DIB5 (instanceRef pdp_ram_10_2_21)) + (portRef DIB4 (instanceRef pdp_ram_10_2_21)) + (portRef DIB3 (instanceRef pdp_ram_10_2_21)) + (portRef DIB2 (instanceRef pdp_ram_10_2_21)) + (portRef DIB1 (instanceRef pdp_ram_10_2_21)) + (portRef DIB0 (instanceRef pdp_ram_10_2_21)) + (portRef CSB2 (instanceRef pdp_ram_10_3_20)) + (portRef CSA2 (instanceRef pdp_ram_10_3_20)) + (portRef CSB1 (instanceRef pdp_ram_10_3_20)) + (portRef CSA1 (instanceRef pdp_ram_10_3_20)) + (portRef WEB (instanceRef pdp_ram_10_3_20)) + (portRef ADB2 (instanceRef pdp_ram_10_3_20)) + (portRef ADA2 (instanceRef pdp_ram_10_3_20)) + (portRef ADB1 (instanceRef pdp_ram_10_3_20)) + (portRef ADA1 (instanceRef pdp_ram_10_3_20)) + (portRef ADB0 (instanceRef pdp_ram_10_3_20)) + (portRef ADA0 (instanceRef pdp_ram_10_3_20)) + (portRef DIB17 (instanceRef pdp_ram_10_3_20)) + (portRef DIA17 (instanceRef pdp_ram_10_3_20)) + (portRef DIB16 (instanceRef pdp_ram_10_3_20)) + (portRef DIA16 (instanceRef pdp_ram_10_3_20)) + (portRef DIB15 (instanceRef pdp_ram_10_3_20)) + (portRef DIA15 (instanceRef pdp_ram_10_3_20)) + (portRef DIB14 (instanceRef pdp_ram_10_3_20)) + (portRef DIA14 (instanceRef pdp_ram_10_3_20)) + (portRef DIB13 (instanceRef pdp_ram_10_3_20)) + (portRef DIA13 (instanceRef pdp_ram_10_3_20)) + (portRef DIB12 (instanceRef pdp_ram_10_3_20)) + (portRef DIA12 (instanceRef pdp_ram_10_3_20)) + (portRef DIB11 (instanceRef pdp_ram_10_3_20)) + (portRef DIA11 (instanceRef pdp_ram_10_3_20)) + (portRef DIB10 (instanceRef pdp_ram_10_3_20)) + (portRef DIA10 (instanceRef pdp_ram_10_3_20)) + (portRef DIB9 (instanceRef pdp_ram_10_3_20)) + (portRef DIA9 (instanceRef pdp_ram_10_3_20)) + (portRef DIB8 (instanceRef pdp_ram_10_3_20)) + (portRef DIB7 (instanceRef pdp_ram_10_3_20)) + (portRef DIB6 (instanceRef pdp_ram_10_3_20)) + (portRef DIB5 (instanceRef pdp_ram_10_3_20)) + (portRef DIB4 (instanceRef pdp_ram_10_3_20)) + (portRef DIB3 (instanceRef pdp_ram_10_3_20)) + (portRef DIB2 (instanceRef pdp_ram_10_3_20)) + (portRef DIB1 (instanceRef pdp_ram_10_3_20)) + (portRef DIB0 (instanceRef pdp_ram_10_3_20)) + (portRef CSB2 (instanceRef pdp_ram_11_0_19)) + (portRef CSA2 (instanceRef pdp_ram_11_0_19)) + (portRef CSB1 (instanceRef pdp_ram_11_0_19)) + (portRef CSA1 (instanceRef pdp_ram_11_0_19)) + (portRef WEB (instanceRef pdp_ram_11_0_19)) + (portRef ADB2 (instanceRef pdp_ram_11_0_19)) + (portRef ADA2 (instanceRef pdp_ram_11_0_19)) + (portRef ADB1 (instanceRef pdp_ram_11_0_19)) + (portRef ADA1 (instanceRef pdp_ram_11_0_19)) + (portRef ADB0 (instanceRef pdp_ram_11_0_19)) + (portRef ADA0 (instanceRef pdp_ram_11_0_19)) + (portRef DIB17 (instanceRef pdp_ram_11_0_19)) + (portRef DIA17 (instanceRef pdp_ram_11_0_19)) + (portRef DIB16 (instanceRef pdp_ram_11_0_19)) + (portRef DIA16 (instanceRef pdp_ram_11_0_19)) + (portRef DIB15 (instanceRef pdp_ram_11_0_19)) + (portRef DIA15 (instanceRef pdp_ram_11_0_19)) + (portRef DIB14 (instanceRef pdp_ram_11_0_19)) + (portRef DIA14 (instanceRef pdp_ram_11_0_19)) + (portRef DIB13 (instanceRef pdp_ram_11_0_19)) + (portRef DIA13 (instanceRef pdp_ram_11_0_19)) + (portRef DIB12 (instanceRef pdp_ram_11_0_19)) + (portRef DIA12 (instanceRef pdp_ram_11_0_19)) + (portRef DIB11 (instanceRef pdp_ram_11_0_19)) + (portRef DIA11 (instanceRef pdp_ram_11_0_19)) + (portRef DIB10 (instanceRef pdp_ram_11_0_19)) + (portRef DIA10 (instanceRef pdp_ram_11_0_19)) + (portRef DIB9 (instanceRef pdp_ram_11_0_19)) + (portRef DIA9 (instanceRef pdp_ram_11_0_19)) + (portRef DIB8 (instanceRef pdp_ram_11_0_19)) + (portRef DIB7 (instanceRef pdp_ram_11_0_19)) + (portRef DIB6 (instanceRef pdp_ram_11_0_19)) + (portRef DIB5 (instanceRef pdp_ram_11_0_19)) + (portRef DIB4 (instanceRef pdp_ram_11_0_19)) + (portRef DIB3 (instanceRef pdp_ram_11_0_19)) + (portRef DIB2 (instanceRef pdp_ram_11_0_19)) + (portRef DIB1 (instanceRef pdp_ram_11_0_19)) + (portRef DIB0 (instanceRef pdp_ram_11_0_19)) + (portRef CSB2 (instanceRef pdp_ram_11_1_18)) + (portRef CSA2 (instanceRef pdp_ram_11_1_18)) + (portRef CSB1 (instanceRef pdp_ram_11_1_18)) + (portRef CSA1 (instanceRef pdp_ram_11_1_18)) + (portRef WEB (instanceRef pdp_ram_11_1_18)) + (portRef ADB2 (instanceRef pdp_ram_11_1_18)) + (portRef ADA2 (instanceRef pdp_ram_11_1_18)) + (portRef ADB1 (instanceRef pdp_ram_11_1_18)) + (portRef ADA1 (instanceRef pdp_ram_11_1_18)) + (portRef ADB0 (instanceRef pdp_ram_11_1_18)) + (portRef ADA0 (instanceRef pdp_ram_11_1_18)) + (portRef DIB17 (instanceRef pdp_ram_11_1_18)) + (portRef DIA17 (instanceRef pdp_ram_11_1_18)) + (portRef DIB16 (instanceRef pdp_ram_11_1_18)) + (portRef DIA16 (instanceRef pdp_ram_11_1_18)) + (portRef DIB15 (instanceRef pdp_ram_11_1_18)) + (portRef DIA15 (instanceRef pdp_ram_11_1_18)) + (portRef DIB14 (instanceRef pdp_ram_11_1_18)) + (portRef DIA14 (instanceRef pdp_ram_11_1_18)) + (portRef DIB13 (instanceRef pdp_ram_11_1_18)) + (portRef DIA13 (instanceRef pdp_ram_11_1_18)) + (portRef DIB12 (instanceRef pdp_ram_11_1_18)) + (portRef DIA12 (instanceRef pdp_ram_11_1_18)) + (portRef DIB11 (instanceRef pdp_ram_11_1_18)) + (portRef DIA11 (instanceRef pdp_ram_11_1_18)) + (portRef DIB10 (instanceRef pdp_ram_11_1_18)) + (portRef DIA10 (instanceRef pdp_ram_11_1_18)) + (portRef DIB9 (instanceRef pdp_ram_11_1_18)) + (portRef DIA9 (instanceRef pdp_ram_11_1_18)) + (portRef DIB8 (instanceRef pdp_ram_11_1_18)) + (portRef DIB7 (instanceRef pdp_ram_11_1_18)) + (portRef DIB6 (instanceRef pdp_ram_11_1_18)) + (portRef DIB5 (instanceRef pdp_ram_11_1_18)) + (portRef DIB4 (instanceRef pdp_ram_11_1_18)) + (portRef DIB3 (instanceRef pdp_ram_11_1_18)) + (portRef DIB2 (instanceRef pdp_ram_11_1_18)) + (portRef DIB1 (instanceRef pdp_ram_11_1_18)) + (portRef DIB0 (instanceRef pdp_ram_11_1_18)) + (portRef CSB2 (instanceRef pdp_ram_11_2_17)) + (portRef CSA2 (instanceRef pdp_ram_11_2_17)) + (portRef CSB1 (instanceRef pdp_ram_11_2_17)) + (portRef CSA1 (instanceRef pdp_ram_11_2_17)) + (portRef WEB (instanceRef pdp_ram_11_2_17)) + (portRef ADB2 (instanceRef pdp_ram_11_2_17)) + (portRef ADA2 (instanceRef pdp_ram_11_2_17)) + (portRef ADB1 (instanceRef pdp_ram_11_2_17)) + (portRef ADA1 (instanceRef pdp_ram_11_2_17)) + (portRef ADB0 (instanceRef pdp_ram_11_2_17)) + (portRef ADA0 (instanceRef pdp_ram_11_2_17)) + (portRef DIB17 (instanceRef pdp_ram_11_2_17)) + (portRef DIA17 (instanceRef pdp_ram_11_2_17)) + (portRef DIB16 (instanceRef pdp_ram_11_2_17)) + (portRef DIA16 (instanceRef pdp_ram_11_2_17)) + (portRef DIB15 (instanceRef pdp_ram_11_2_17)) + (portRef DIA15 (instanceRef pdp_ram_11_2_17)) + (portRef DIB14 (instanceRef pdp_ram_11_2_17)) + (portRef DIA14 (instanceRef pdp_ram_11_2_17)) + (portRef DIB13 (instanceRef pdp_ram_11_2_17)) + (portRef DIA13 (instanceRef pdp_ram_11_2_17)) + (portRef DIB12 (instanceRef pdp_ram_11_2_17)) + (portRef DIA12 (instanceRef pdp_ram_11_2_17)) + (portRef DIB11 (instanceRef pdp_ram_11_2_17)) + (portRef DIA11 (instanceRef pdp_ram_11_2_17)) + (portRef DIB10 (instanceRef pdp_ram_11_2_17)) + (portRef DIA10 (instanceRef pdp_ram_11_2_17)) + (portRef DIB9 (instanceRef pdp_ram_11_2_17)) + (portRef DIA9 (instanceRef pdp_ram_11_2_17)) + (portRef DIB8 (instanceRef pdp_ram_11_2_17)) + (portRef DIB7 (instanceRef pdp_ram_11_2_17)) + (portRef DIB6 (instanceRef pdp_ram_11_2_17)) + (portRef DIB5 (instanceRef pdp_ram_11_2_17)) + (portRef DIB4 (instanceRef pdp_ram_11_2_17)) + (portRef DIB3 (instanceRef pdp_ram_11_2_17)) + (portRef DIB2 (instanceRef pdp_ram_11_2_17)) + (portRef DIB1 (instanceRef pdp_ram_11_2_17)) + (portRef DIB0 (instanceRef pdp_ram_11_2_17)) + (portRef CSB2 (instanceRef pdp_ram_11_3_16)) + (portRef CSA2 (instanceRef pdp_ram_11_3_16)) + (portRef CSB1 (instanceRef pdp_ram_11_3_16)) + (portRef CSA1 (instanceRef pdp_ram_11_3_16)) + (portRef WEB (instanceRef pdp_ram_11_3_16)) + (portRef ADB2 (instanceRef pdp_ram_11_3_16)) + (portRef ADA2 (instanceRef pdp_ram_11_3_16)) + (portRef ADB1 (instanceRef pdp_ram_11_3_16)) + (portRef ADA1 (instanceRef pdp_ram_11_3_16)) + (portRef ADB0 (instanceRef pdp_ram_11_3_16)) + (portRef ADA0 (instanceRef pdp_ram_11_3_16)) + (portRef DIB17 (instanceRef pdp_ram_11_3_16)) + (portRef DIA17 (instanceRef pdp_ram_11_3_16)) + (portRef DIB16 (instanceRef pdp_ram_11_3_16)) + (portRef DIA16 (instanceRef pdp_ram_11_3_16)) + (portRef DIB15 (instanceRef pdp_ram_11_3_16)) + (portRef DIA15 (instanceRef pdp_ram_11_3_16)) + (portRef DIB14 (instanceRef pdp_ram_11_3_16)) + (portRef DIA14 (instanceRef pdp_ram_11_3_16)) + (portRef DIB13 (instanceRef pdp_ram_11_3_16)) + (portRef DIA13 (instanceRef pdp_ram_11_3_16)) + (portRef DIB12 (instanceRef pdp_ram_11_3_16)) + (portRef DIA12 (instanceRef pdp_ram_11_3_16)) + (portRef DIB11 (instanceRef pdp_ram_11_3_16)) + (portRef DIA11 (instanceRef pdp_ram_11_3_16)) + (portRef DIB10 (instanceRef pdp_ram_11_3_16)) + (portRef DIA10 (instanceRef pdp_ram_11_3_16)) + (portRef DIB9 (instanceRef pdp_ram_11_3_16)) + (portRef DIA9 (instanceRef pdp_ram_11_3_16)) + (portRef DIB8 (instanceRef pdp_ram_11_3_16)) + (portRef DIB7 (instanceRef pdp_ram_11_3_16)) + (portRef DIB6 (instanceRef pdp_ram_11_3_16)) + (portRef DIB5 (instanceRef pdp_ram_11_3_16)) + (portRef DIB4 (instanceRef pdp_ram_11_3_16)) + (portRef DIB3 (instanceRef pdp_ram_11_3_16)) + (portRef DIB2 (instanceRef pdp_ram_11_3_16)) + (portRef DIB1 (instanceRef pdp_ram_11_3_16)) + (portRef DIB0 (instanceRef pdp_ram_11_3_16)) + (portRef CSB2 (instanceRef pdp_ram_12_0_15)) + (portRef CSA2 (instanceRef pdp_ram_12_0_15)) + (portRef CSB1 (instanceRef pdp_ram_12_0_15)) + (portRef CSA1 (instanceRef pdp_ram_12_0_15)) + (portRef WEB (instanceRef pdp_ram_12_0_15)) + (portRef ADB2 (instanceRef pdp_ram_12_0_15)) + (portRef ADA2 (instanceRef pdp_ram_12_0_15)) + (portRef ADB1 (instanceRef pdp_ram_12_0_15)) + (portRef ADA1 (instanceRef pdp_ram_12_0_15)) + (portRef ADB0 (instanceRef pdp_ram_12_0_15)) + (portRef ADA0 (instanceRef pdp_ram_12_0_15)) + (portRef DIB17 (instanceRef pdp_ram_12_0_15)) + (portRef DIA17 (instanceRef pdp_ram_12_0_15)) + (portRef DIB16 (instanceRef pdp_ram_12_0_15)) + (portRef DIA16 (instanceRef pdp_ram_12_0_15)) + (portRef DIB15 (instanceRef pdp_ram_12_0_15)) + (portRef DIA15 (instanceRef pdp_ram_12_0_15)) + (portRef DIB14 (instanceRef pdp_ram_12_0_15)) + (portRef DIA14 (instanceRef pdp_ram_12_0_15)) + (portRef DIB13 (instanceRef pdp_ram_12_0_15)) + (portRef DIA13 (instanceRef pdp_ram_12_0_15)) + (portRef DIB12 (instanceRef pdp_ram_12_0_15)) + (portRef DIA12 (instanceRef pdp_ram_12_0_15)) + (portRef DIB11 (instanceRef pdp_ram_12_0_15)) + (portRef DIA11 (instanceRef pdp_ram_12_0_15)) + (portRef DIB10 (instanceRef pdp_ram_12_0_15)) + (portRef DIA10 (instanceRef pdp_ram_12_0_15)) + (portRef DIB9 (instanceRef pdp_ram_12_0_15)) + (portRef DIA9 (instanceRef pdp_ram_12_0_15)) + (portRef DIB8 (instanceRef pdp_ram_12_0_15)) + (portRef DIB7 (instanceRef pdp_ram_12_0_15)) + (portRef DIB6 (instanceRef pdp_ram_12_0_15)) + (portRef DIB5 (instanceRef pdp_ram_12_0_15)) + (portRef DIB4 (instanceRef pdp_ram_12_0_15)) + (portRef DIB3 (instanceRef pdp_ram_12_0_15)) + (portRef DIB2 (instanceRef pdp_ram_12_0_15)) + (portRef DIB1 (instanceRef pdp_ram_12_0_15)) + (portRef DIB0 (instanceRef pdp_ram_12_0_15)) + (portRef CSB2 (instanceRef pdp_ram_12_1_14)) + (portRef CSA2 (instanceRef pdp_ram_12_1_14)) + (portRef CSB1 (instanceRef pdp_ram_12_1_14)) + (portRef CSA1 (instanceRef pdp_ram_12_1_14)) + (portRef WEB (instanceRef pdp_ram_12_1_14)) + (portRef ADB2 (instanceRef pdp_ram_12_1_14)) + (portRef ADA2 (instanceRef pdp_ram_12_1_14)) + (portRef ADB1 (instanceRef pdp_ram_12_1_14)) + (portRef ADA1 (instanceRef pdp_ram_12_1_14)) + (portRef ADB0 (instanceRef pdp_ram_12_1_14)) + (portRef ADA0 (instanceRef pdp_ram_12_1_14)) + (portRef DIB17 (instanceRef pdp_ram_12_1_14)) + (portRef DIA17 (instanceRef pdp_ram_12_1_14)) + (portRef DIB16 (instanceRef pdp_ram_12_1_14)) + (portRef DIA16 (instanceRef pdp_ram_12_1_14)) + (portRef DIB15 (instanceRef pdp_ram_12_1_14)) + (portRef DIA15 (instanceRef pdp_ram_12_1_14)) + (portRef DIB14 (instanceRef pdp_ram_12_1_14)) + (portRef DIA14 (instanceRef pdp_ram_12_1_14)) + (portRef DIB13 (instanceRef pdp_ram_12_1_14)) + (portRef DIA13 (instanceRef pdp_ram_12_1_14)) + (portRef DIB12 (instanceRef pdp_ram_12_1_14)) + (portRef DIA12 (instanceRef pdp_ram_12_1_14)) + (portRef DIB11 (instanceRef pdp_ram_12_1_14)) + (portRef DIA11 (instanceRef pdp_ram_12_1_14)) + (portRef DIB10 (instanceRef pdp_ram_12_1_14)) + (portRef DIA10 (instanceRef pdp_ram_12_1_14)) + (portRef DIB9 (instanceRef pdp_ram_12_1_14)) + (portRef DIA9 (instanceRef pdp_ram_12_1_14)) + (portRef DIB8 (instanceRef pdp_ram_12_1_14)) + (portRef DIB7 (instanceRef pdp_ram_12_1_14)) + (portRef DIB6 (instanceRef pdp_ram_12_1_14)) + (portRef DIB5 (instanceRef pdp_ram_12_1_14)) + (portRef DIB4 (instanceRef pdp_ram_12_1_14)) + (portRef DIB3 (instanceRef pdp_ram_12_1_14)) + (portRef DIB2 (instanceRef pdp_ram_12_1_14)) + (portRef DIB1 (instanceRef pdp_ram_12_1_14)) + (portRef DIB0 (instanceRef pdp_ram_12_1_14)) + (portRef CSB2 (instanceRef pdp_ram_12_2_13)) + (portRef CSA2 (instanceRef pdp_ram_12_2_13)) + (portRef CSB1 (instanceRef pdp_ram_12_2_13)) + (portRef CSA1 (instanceRef pdp_ram_12_2_13)) + (portRef WEB (instanceRef pdp_ram_12_2_13)) + (portRef ADB2 (instanceRef pdp_ram_12_2_13)) + (portRef ADA2 (instanceRef pdp_ram_12_2_13)) + (portRef ADB1 (instanceRef pdp_ram_12_2_13)) + (portRef ADA1 (instanceRef pdp_ram_12_2_13)) + (portRef ADB0 (instanceRef pdp_ram_12_2_13)) + (portRef ADA0 (instanceRef pdp_ram_12_2_13)) + (portRef DIB17 (instanceRef pdp_ram_12_2_13)) + (portRef DIA17 (instanceRef pdp_ram_12_2_13)) + (portRef DIB16 (instanceRef pdp_ram_12_2_13)) + (portRef DIA16 (instanceRef pdp_ram_12_2_13)) + (portRef DIB15 (instanceRef pdp_ram_12_2_13)) + (portRef DIA15 (instanceRef pdp_ram_12_2_13)) + (portRef DIB14 (instanceRef pdp_ram_12_2_13)) + (portRef DIA14 (instanceRef pdp_ram_12_2_13)) + (portRef DIB13 (instanceRef pdp_ram_12_2_13)) + (portRef DIA13 (instanceRef pdp_ram_12_2_13)) + (portRef DIB12 (instanceRef pdp_ram_12_2_13)) + (portRef DIA12 (instanceRef pdp_ram_12_2_13)) + (portRef DIB11 (instanceRef pdp_ram_12_2_13)) + (portRef DIA11 (instanceRef pdp_ram_12_2_13)) + (portRef DIB10 (instanceRef pdp_ram_12_2_13)) + (portRef DIA10 (instanceRef pdp_ram_12_2_13)) + (portRef DIB9 (instanceRef pdp_ram_12_2_13)) + (portRef DIA9 (instanceRef pdp_ram_12_2_13)) + (portRef DIB8 (instanceRef pdp_ram_12_2_13)) + (portRef DIB7 (instanceRef pdp_ram_12_2_13)) + (portRef DIB6 (instanceRef pdp_ram_12_2_13)) + (portRef DIB5 (instanceRef pdp_ram_12_2_13)) + (portRef DIB4 (instanceRef pdp_ram_12_2_13)) + (portRef DIB3 (instanceRef pdp_ram_12_2_13)) + (portRef DIB2 (instanceRef pdp_ram_12_2_13)) + (portRef DIB1 (instanceRef pdp_ram_12_2_13)) + (portRef DIB0 (instanceRef pdp_ram_12_2_13)) + (portRef CSB2 (instanceRef pdp_ram_12_3_12)) + (portRef CSA2 (instanceRef pdp_ram_12_3_12)) + (portRef CSB1 (instanceRef pdp_ram_12_3_12)) + (portRef CSA1 (instanceRef pdp_ram_12_3_12)) + (portRef WEB (instanceRef pdp_ram_12_3_12)) + (portRef ADB2 (instanceRef pdp_ram_12_3_12)) + (portRef ADA2 (instanceRef pdp_ram_12_3_12)) + (portRef ADB1 (instanceRef pdp_ram_12_3_12)) + (portRef ADA1 (instanceRef pdp_ram_12_3_12)) + (portRef ADB0 (instanceRef pdp_ram_12_3_12)) + (portRef ADA0 (instanceRef pdp_ram_12_3_12)) + (portRef DIB17 (instanceRef pdp_ram_12_3_12)) + (portRef DIA17 (instanceRef pdp_ram_12_3_12)) + (portRef DIB16 (instanceRef pdp_ram_12_3_12)) + (portRef DIA16 (instanceRef pdp_ram_12_3_12)) + (portRef DIB15 (instanceRef pdp_ram_12_3_12)) + (portRef DIA15 (instanceRef pdp_ram_12_3_12)) + (portRef DIB14 (instanceRef pdp_ram_12_3_12)) + (portRef DIA14 (instanceRef pdp_ram_12_3_12)) + (portRef DIB13 (instanceRef pdp_ram_12_3_12)) + (portRef DIA13 (instanceRef pdp_ram_12_3_12)) + (portRef DIB12 (instanceRef pdp_ram_12_3_12)) + (portRef DIA12 (instanceRef pdp_ram_12_3_12)) + (portRef DIB11 (instanceRef pdp_ram_12_3_12)) + (portRef DIA11 (instanceRef pdp_ram_12_3_12)) + (portRef DIB10 (instanceRef pdp_ram_12_3_12)) + (portRef DIA10 (instanceRef pdp_ram_12_3_12)) + (portRef DIB9 (instanceRef pdp_ram_12_3_12)) + (portRef DIA9 (instanceRef pdp_ram_12_3_12)) + (portRef DIB8 (instanceRef pdp_ram_12_3_12)) + (portRef DIB7 (instanceRef pdp_ram_12_3_12)) + (portRef DIB6 (instanceRef pdp_ram_12_3_12)) + (portRef DIB5 (instanceRef pdp_ram_12_3_12)) + (portRef DIB4 (instanceRef pdp_ram_12_3_12)) + (portRef DIB3 (instanceRef pdp_ram_12_3_12)) + (portRef DIB2 (instanceRef pdp_ram_12_3_12)) + (portRef DIB1 (instanceRef pdp_ram_12_3_12)) + (portRef DIB0 (instanceRef pdp_ram_12_3_12)) + (portRef CSB2 (instanceRef pdp_ram_13_0_11)) + (portRef CSA2 (instanceRef pdp_ram_13_0_11)) + (portRef CSB1 (instanceRef pdp_ram_13_0_11)) + (portRef CSA1 (instanceRef pdp_ram_13_0_11)) + (portRef WEB (instanceRef pdp_ram_13_0_11)) + (portRef ADB2 (instanceRef pdp_ram_13_0_11)) + (portRef ADA2 (instanceRef pdp_ram_13_0_11)) + (portRef ADB1 (instanceRef pdp_ram_13_0_11)) + (portRef ADA1 (instanceRef pdp_ram_13_0_11)) + (portRef ADB0 (instanceRef pdp_ram_13_0_11)) + (portRef ADA0 (instanceRef pdp_ram_13_0_11)) + (portRef DIB17 (instanceRef pdp_ram_13_0_11)) + (portRef DIA17 (instanceRef pdp_ram_13_0_11)) + (portRef DIB16 (instanceRef pdp_ram_13_0_11)) + (portRef DIA16 (instanceRef pdp_ram_13_0_11)) + (portRef DIB15 (instanceRef pdp_ram_13_0_11)) + (portRef DIA15 (instanceRef pdp_ram_13_0_11)) + (portRef DIB14 (instanceRef pdp_ram_13_0_11)) + (portRef DIA14 (instanceRef pdp_ram_13_0_11)) + (portRef DIB13 (instanceRef pdp_ram_13_0_11)) + (portRef DIA13 (instanceRef pdp_ram_13_0_11)) + (portRef DIB12 (instanceRef pdp_ram_13_0_11)) + (portRef DIA12 (instanceRef pdp_ram_13_0_11)) + (portRef DIB11 (instanceRef pdp_ram_13_0_11)) + (portRef DIA11 (instanceRef pdp_ram_13_0_11)) + (portRef DIB10 (instanceRef pdp_ram_13_0_11)) + (portRef DIA10 (instanceRef pdp_ram_13_0_11)) + (portRef DIB9 (instanceRef pdp_ram_13_0_11)) + (portRef DIA9 (instanceRef pdp_ram_13_0_11)) + (portRef DIB8 (instanceRef pdp_ram_13_0_11)) + (portRef DIB7 (instanceRef pdp_ram_13_0_11)) + (portRef DIB6 (instanceRef pdp_ram_13_0_11)) + (portRef DIB5 (instanceRef pdp_ram_13_0_11)) + (portRef DIB4 (instanceRef pdp_ram_13_0_11)) + (portRef DIB3 (instanceRef pdp_ram_13_0_11)) + (portRef DIB2 (instanceRef pdp_ram_13_0_11)) + (portRef DIB1 (instanceRef pdp_ram_13_0_11)) + (portRef DIB0 (instanceRef pdp_ram_13_0_11)) + (portRef CSB2 (instanceRef pdp_ram_13_1_10)) + (portRef CSA2 (instanceRef pdp_ram_13_1_10)) + (portRef CSB1 (instanceRef pdp_ram_13_1_10)) + (portRef CSA1 (instanceRef pdp_ram_13_1_10)) + (portRef WEB (instanceRef pdp_ram_13_1_10)) + (portRef ADB2 (instanceRef pdp_ram_13_1_10)) + (portRef ADA2 (instanceRef pdp_ram_13_1_10)) + (portRef ADB1 (instanceRef pdp_ram_13_1_10)) + (portRef ADA1 (instanceRef pdp_ram_13_1_10)) + (portRef ADB0 (instanceRef pdp_ram_13_1_10)) + (portRef ADA0 (instanceRef pdp_ram_13_1_10)) + (portRef DIB17 (instanceRef pdp_ram_13_1_10)) + (portRef DIA17 (instanceRef pdp_ram_13_1_10)) + (portRef DIB16 (instanceRef pdp_ram_13_1_10)) + (portRef DIA16 (instanceRef pdp_ram_13_1_10)) + (portRef DIB15 (instanceRef pdp_ram_13_1_10)) + (portRef DIA15 (instanceRef pdp_ram_13_1_10)) + (portRef DIB14 (instanceRef pdp_ram_13_1_10)) + (portRef DIA14 (instanceRef pdp_ram_13_1_10)) + (portRef DIB13 (instanceRef pdp_ram_13_1_10)) + (portRef DIA13 (instanceRef pdp_ram_13_1_10)) + (portRef DIB12 (instanceRef pdp_ram_13_1_10)) + (portRef DIA12 (instanceRef pdp_ram_13_1_10)) + (portRef DIB11 (instanceRef pdp_ram_13_1_10)) + (portRef DIA11 (instanceRef pdp_ram_13_1_10)) + (portRef DIB10 (instanceRef pdp_ram_13_1_10)) + (portRef DIA10 (instanceRef pdp_ram_13_1_10)) + (portRef DIB9 (instanceRef pdp_ram_13_1_10)) + (portRef DIA9 (instanceRef pdp_ram_13_1_10)) + (portRef DIB8 (instanceRef pdp_ram_13_1_10)) + (portRef DIB7 (instanceRef pdp_ram_13_1_10)) + (portRef DIB6 (instanceRef pdp_ram_13_1_10)) + (portRef DIB5 (instanceRef pdp_ram_13_1_10)) + (portRef DIB4 (instanceRef pdp_ram_13_1_10)) + (portRef DIB3 (instanceRef pdp_ram_13_1_10)) + (portRef DIB2 (instanceRef pdp_ram_13_1_10)) + (portRef DIB1 (instanceRef pdp_ram_13_1_10)) + (portRef DIB0 (instanceRef pdp_ram_13_1_10)) + (portRef CSB2 (instanceRef pdp_ram_13_2_9)) + (portRef CSA2 (instanceRef pdp_ram_13_2_9)) + (portRef CSB1 (instanceRef pdp_ram_13_2_9)) + (portRef CSA1 (instanceRef pdp_ram_13_2_9)) + (portRef WEB (instanceRef pdp_ram_13_2_9)) + (portRef ADB2 (instanceRef pdp_ram_13_2_9)) + (portRef ADA2 (instanceRef pdp_ram_13_2_9)) + (portRef ADB1 (instanceRef pdp_ram_13_2_9)) + (portRef ADA1 (instanceRef pdp_ram_13_2_9)) + (portRef ADB0 (instanceRef pdp_ram_13_2_9)) + (portRef ADA0 (instanceRef pdp_ram_13_2_9)) + (portRef DIB17 (instanceRef pdp_ram_13_2_9)) + (portRef DIA17 (instanceRef pdp_ram_13_2_9)) + (portRef DIB16 (instanceRef pdp_ram_13_2_9)) + (portRef DIA16 (instanceRef pdp_ram_13_2_9)) + (portRef DIB15 (instanceRef pdp_ram_13_2_9)) + (portRef DIA15 (instanceRef pdp_ram_13_2_9)) + (portRef DIB14 (instanceRef pdp_ram_13_2_9)) + (portRef DIA14 (instanceRef pdp_ram_13_2_9)) + (portRef DIB13 (instanceRef pdp_ram_13_2_9)) + (portRef DIA13 (instanceRef pdp_ram_13_2_9)) + (portRef DIB12 (instanceRef pdp_ram_13_2_9)) + (portRef DIA12 (instanceRef pdp_ram_13_2_9)) + (portRef DIB11 (instanceRef pdp_ram_13_2_9)) + (portRef DIA11 (instanceRef pdp_ram_13_2_9)) + (portRef DIB10 (instanceRef pdp_ram_13_2_9)) + (portRef DIA10 (instanceRef pdp_ram_13_2_9)) + (portRef DIB9 (instanceRef pdp_ram_13_2_9)) + (portRef DIA9 (instanceRef pdp_ram_13_2_9)) + (portRef DIB8 (instanceRef pdp_ram_13_2_9)) + (portRef DIB7 (instanceRef pdp_ram_13_2_9)) + (portRef DIB6 (instanceRef pdp_ram_13_2_9)) + (portRef DIB5 (instanceRef pdp_ram_13_2_9)) + (portRef DIB4 (instanceRef pdp_ram_13_2_9)) + (portRef DIB3 (instanceRef pdp_ram_13_2_9)) + (portRef DIB2 (instanceRef pdp_ram_13_2_9)) + (portRef DIB1 (instanceRef pdp_ram_13_2_9)) + (portRef DIB0 (instanceRef pdp_ram_13_2_9)) + (portRef CSB2 (instanceRef pdp_ram_13_3_8)) + (portRef CSA2 (instanceRef pdp_ram_13_3_8)) + (portRef CSB1 (instanceRef pdp_ram_13_3_8)) + (portRef CSA1 (instanceRef pdp_ram_13_3_8)) + (portRef WEB (instanceRef pdp_ram_13_3_8)) + (portRef ADB2 (instanceRef pdp_ram_13_3_8)) + (portRef ADA2 (instanceRef pdp_ram_13_3_8)) + (portRef ADB1 (instanceRef pdp_ram_13_3_8)) + (portRef ADA1 (instanceRef pdp_ram_13_3_8)) + (portRef ADB0 (instanceRef pdp_ram_13_3_8)) + (portRef ADA0 (instanceRef pdp_ram_13_3_8)) + (portRef DIB17 (instanceRef pdp_ram_13_3_8)) + (portRef DIA17 (instanceRef pdp_ram_13_3_8)) + (portRef DIB16 (instanceRef pdp_ram_13_3_8)) + (portRef DIA16 (instanceRef pdp_ram_13_3_8)) + (portRef DIB15 (instanceRef pdp_ram_13_3_8)) + (portRef DIA15 (instanceRef pdp_ram_13_3_8)) + (portRef DIB14 (instanceRef pdp_ram_13_3_8)) + (portRef DIA14 (instanceRef pdp_ram_13_3_8)) + (portRef DIB13 (instanceRef pdp_ram_13_3_8)) + (portRef DIA13 (instanceRef pdp_ram_13_3_8)) + (portRef DIB12 (instanceRef pdp_ram_13_3_8)) + (portRef DIA12 (instanceRef pdp_ram_13_3_8)) + (portRef DIB11 (instanceRef pdp_ram_13_3_8)) + (portRef DIA11 (instanceRef pdp_ram_13_3_8)) + (portRef DIB10 (instanceRef pdp_ram_13_3_8)) + (portRef DIA10 (instanceRef pdp_ram_13_3_8)) + (portRef DIB9 (instanceRef pdp_ram_13_3_8)) + (portRef DIA9 (instanceRef pdp_ram_13_3_8)) + (portRef DIB8 (instanceRef pdp_ram_13_3_8)) + (portRef DIB7 (instanceRef pdp_ram_13_3_8)) + (portRef DIB6 (instanceRef pdp_ram_13_3_8)) + (portRef DIB5 (instanceRef pdp_ram_13_3_8)) + (portRef DIB4 (instanceRef pdp_ram_13_3_8)) + (portRef DIB3 (instanceRef pdp_ram_13_3_8)) + (portRef DIB2 (instanceRef pdp_ram_13_3_8)) + (portRef DIB1 (instanceRef pdp_ram_13_3_8)) + (portRef DIB0 (instanceRef pdp_ram_13_3_8)) + (portRef CSB2 (instanceRef pdp_ram_14_0_7)) + (portRef CSA2 (instanceRef pdp_ram_14_0_7)) + (portRef CSB1 (instanceRef pdp_ram_14_0_7)) + (portRef CSA1 (instanceRef pdp_ram_14_0_7)) + (portRef WEB (instanceRef pdp_ram_14_0_7)) + (portRef ADB2 (instanceRef pdp_ram_14_0_7)) + (portRef ADA2 (instanceRef pdp_ram_14_0_7)) + (portRef ADB1 (instanceRef pdp_ram_14_0_7)) + (portRef ADA1 (instanceRef pdp_ram_14_0_7)) + (portRef ADB0 (instanceRef pdp_ram_14_0_7)) + (portRef ADA0 (instanceRef pdp_ram_14_0_7)) + (portRef DIB17 (instanceRef pdp_ram_14_0_7)) + (portRef DIA17 (instanceRef pdp_ram_14_0_7)) + (portRef DIB16 (instanceRef pdp_ram_14_0_7)) + (portRef DIA16 (instanceRef pdp_ram_14_0_7)) + (portRef DIB15 (instanceRef pdp_ram_14_0_7)) + (portRef DIA15 (instanceRef pdp_ram_14_0_7)) + (portRef DIB14 (instanceRef pdp_ram_14_0_7)) + (portRef DIA14 (instanceRef pdp_ram_14_0_7)) + (portRef DIB13 (instanceRef pdp_ram_14_0_7)) + (portRef DIA13 (instanceRef pdp_ram_14_0_7)) + (portRef DIB12 (instanceRef pdp_ram_14_0_7)) + (portRef DIA12 (instanceRef pdp_ram_14_0_7)) + (portRef DIB11 (instanceRef pdp_ram_14_0_7)) + (portRef DIA11 (instanceRef pdp_ram_14_0_7)) + (portRef DIB10 (instanceRef pdp_ram_14_0_7)) + (portRef DIA10 (instanceRef pdp_ram_14_0_7)) + (portRef DIB9 (instanceRef pdp_ram_14_0_7)) + (portRef DIA9 (instanceRef pdp_ram_14_0_7)) + (portRef DIB8 (instanceRef pdp_ram_14_0_7)) + (portRef DIB7 (instanceRef pdp_ram_14_0_7)) + (portRef DIB6 (instanceRef pdp_ram_14_0_7)) + (portRef DIB5 (instanceRef pdp_ram_14_0_7)) + (portRef DIB4 (instanceRef pdp_ram_14_0_7)) + (portRef DIB3 (instanceRef pdp_ram_14_0_7)) + (portRef DIB2 (instanceRef pdp_ram_14_0_7)) + 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(portRef DIA1 (instanceRef pdp_ram_8_0_31)) + (portRef DIA1 (instanceRef pdp_ram_9_0_27)) + (portRef DIA1 (instanceRef pdp_ram_10_0_23)) + (portRef DIA1 (instanceRef pdp_ram_11_0_19)) + (portRef DIA1 (instanceRef pdp_ram_12_0_15)) + (portRef DIA1 (instanceRef pdp_ram_13_0_11)) + (portRef DIA1 (instanceRef pdp_ram_14_0_7)) + (portRef DIA1 (instanceRef pdp_ram_15_0_3)))) + (net datain0 + (joined + (portRef (member Data 35)) + (portRef DIA0 (instanceRef pdp_ram_0_0_63)) + (portRef DIA0 (instanceRef pdp_ram_1_0_59)) + (portRef DIA0 (instanceRef pdp_ram_2_0_55)) + (portRef DIA0 (instanceRef pdp_ram_3_0_51)) + (portRef DIA0 (instanceRef pdp_ram_4_0_47)) + (portRef DIA0 (instanceRef pdp_ram_5_0_43)) + (portRef DIA0 (instanceRef pdp_ram_6_0_39)) + (portRef DIA0 (instanceRef pdp_ram_7_0_35)) + (portRef DIA0 (instanceRef pdp_ram_8_0_31)) + (portRef DIA0 (instanceRef pdp_ram_9_0_27)) + (portRef DIA0 (instanceRef pdp_ram_10_0_23)) + (portRef DIA0 (instanceRef pdp_ram_11_0_19)) + (portRef DIA0 (instanceRef pdp_ram_12_0_15)) + (portRef DIA0 (instanceRef pdp_ram_13_0_11)) + (portRef DIA0 (instanceRef pdp_ram_14_0_7)) + (portRef DIA0 (instanceRef pdp_ram_15_0_3)))))))) + (design fifo_36x32k_oreg + (cellRef fifo_36x32k_oreg + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc new file mode 100644 index 0000000..6a11f2a --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x32k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:42:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd new file mode 100644 index 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z3LB)BqI85ts*F-ER&S%!+atCNr9KH#|3Im)LFyfpPSi*(N2wpHcTqakBlaFjrzc3g zkJ12x)IU)=OC$9GN`qK^h|;+pv5!zXKSAnal!h3jK0)bXjnoR13|1aWmwUukqI6|~ z)TbzoFi5RJiGRzg`wXS)G-98l#J^?Ltww27g4h=*jWI}liPEhasjtKri$_R(E&kRo zMCu!q#+ONbi_(2@Qs1F8iSxb}f04>+4N7s1q7{@L@<{y)rAHE^eh_~*ZIJpAr8%sA zLg{gh*v}{>JW{`)v>-w1SCkeRq<%x`8CJie^t?vw4>VWrE^E=eO@i3J(Y&2O>Q6M^ z=8;;5=J8UX?k_Y?(WL4GG|$jU)u4HvL8=zbPZvqmp*iJ|>V#%j3Ut~8%}X>=ozeWJ zPHIy$zndVn8JbrVNo|hiFFjIS(ENiG=(Giz*J`A;L`$a_sjbkmRf1Gkv~(|$+8Qmp zd!#~W*G6SrB961wrJ^>AhjJ@1{O(ekCwq6sqSbobW%H@WrEn, B=>invout_2, Z=>wren_i); + + INV_13: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_12: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_11: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_10: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_129: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_128: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec0_p00); + + INV_5: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_4: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_3: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_2: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec1_r10); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec2_p00); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec3_r10); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec4_p00); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec5_r10); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec6_p00); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec7_r10); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec8_p01); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec9_r11); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec10_p01); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec11_r11); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec12_p01); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec13_r11); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec14_p01); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec15_r11); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec16_p02); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec17_r12); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec18_p02); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec19_r12); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec20_p02); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec21_r12); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec22_p02); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec23_r12); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec24_p03); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec25_r13); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec26_p03); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec27_r13); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec28_p03); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec29_r13); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>dec30_p03); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>dec31_r13); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec32_p04); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec33_r14); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec34_p04); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec35_r14); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec36_p04); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec37_r14); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec38_p04); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec39_r14); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec40_p05); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec41_r15); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec42_p05); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec43_r15); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec44_p05); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec45_r15); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec46_p05); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec47_r15); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec48_p06); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec49_r16); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec50_p06); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec51_r16); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec52_p06); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec53_r16); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec54_p06); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec55_r16); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec56_p07); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec57_r17); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec58_p07); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec59_r17); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec60_p07); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec61_r17); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>dec62_p07); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>dec63_r17); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec64_p08); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec65_r18); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec66_p08); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec67_r18); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec68_p08); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec69_r18); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec70_p08); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec71_r18); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec72_p09); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec73_r19); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec74_p09); + + LUT4_52: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec75_r19); + + LUT4_51: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec76_p09); + + LUT4_50: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec77_r19); + + LUT4_49: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec78_p09); + + LUT4_48: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec79_r19); + + LUT4_47: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec80_p010); + + LUT4_46: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec81_r110); + + LUT4_45: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec82_p010); + + LUT4_44: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec83_r110); + + LUT4_43: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec84_p010); + + LUT4_42: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec85_r110); + + LUT4_41: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec86_p010); + + LUT4_40: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec87_r110); + + LUT4_39: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec88_p011); + + LUT4_38: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec89_r111); + + LUT4_37: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec90_p011); + + LUT4_36: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec91_r111); + + LUT4_35: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec92_p011); + + LUT4_34: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec93_r111); + + LUT4_33: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>dec94_p011); + + LUT4_32: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>dec95_r111); + + LUT4_31: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec96_p012); + + LUT4_30: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec97_r112); + + LUT4_29: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec98_p012); + + LUT4_28: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec99_r112); + + LUT4_27: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec100_p012); + + LUT4_26: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec101_r112); + + LUT4_25: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec102_p012); + + LUT4_24: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec103_r112); + + LUT4_23: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec104_p013); + + LUT4_22: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec105_r113); + + LUT4_21: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec106_p013); + + LUT4_20: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec107_r113); + + LUT4_19: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec108_p013); + + LUT4_18: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec109_r113); + + LUT4_17: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec110_p013); + + LUT4_16: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec111_r113); + + LUT4_15: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec112_p014); + + LUT4_14: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec113_r114); + + LUT4_13: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec114_p014); + + LUT4_12: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec115_r114); + + LUT4_11: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec116_p014); + + LUT4_10: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec117_r114); + + LUT4_9: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>dec118_p014); + + LUT4_8: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>dec119_r114); + + LUT4_7: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec120_p015); + + LUT4_6: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec121_r115); + + LUT4_5: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec122_p015); + + LUT4_4: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec123_r115); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec124_p015); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec125_r115); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>dec126_p015); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>dec127_r115); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_15, B=>rptr_15, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_63: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec0_p00, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec1_r10, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8, + DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, + DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, + DOB1=>mdout1_0_1, DOB0=>mdout1_0_0); + + pdp_ram_0_1_62: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec2_p00, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec3_r10, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, + DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, + DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, + DOB1=>mdout1_0_10, DOB0=>mdout1_0_9); + + pdp_ram_0_2_61: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec4_p00, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec5_r10, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, + DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, + DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, + DOB1=>mdout1_0_19, DOB0=>mdout1_0_18); + + pdp_ram_0_3_60: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec6_p00, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec7_r10, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, + DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, + DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, + DOB1=>mdout1_0_28, DOB0=>mdout1_0_27); + + pdp_ram_1_0_59: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec8_p01, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec9_r11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8, + DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, + DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, + DOB1=>mdout1_1_1, DOB0=>mdout1_1_0); + + pdp_ram_1_1_58: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec10_p01, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec11_r11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, + DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, + DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, + DOB1=>mdout1_1_10, DOB0=>mdout1_1_9); + + pdp_ram_1_2_57: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec12_p01, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec13_r11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, + DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, + DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, + DOB1=>mdout1_1_19, DOB0=>mdout1_1_18); + + pdp_ram_1_3_56: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec14_p01, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec15_r11, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, + DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, + DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, + DOB1=>mdout1_1_28, DOB0=>mdout1_1_27); + + pdp_ram_2_0_55: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec16_p02, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec17_r12, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_8, + DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, + DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, + DOB1=>mdout1_2_1, DOB0=>mdout1_2_0); + + pdp_ram_2_1_54: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec18_p02, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec19_r12, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, + DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, + DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, + DOB1=>mdout1_2_10, DOB0=>mdout1_2_9); + + pdp_ram_2_2_53: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec20_p02, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec21_r12, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, + DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, + DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, + DOB1=>mdout1_2_19, DOB0=>mdout1_2_18); + + pdp_ram_2_3_52: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec22_p02, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec23_r12, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, + DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, + DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, + DOB1=>mdout1_2_28, DOB0=>mdout1_2_27); + + pdp_ram_3_0_51: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec24_p03, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec25_r13, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_8, + DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, + DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, + DOB1=>mdout1_3_1, DOB0=>mdout1_3_0); + + pdp_ram_3_1_50: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec26_p03, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec27_r13, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, + DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, + DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, + DOB1=>mdout1_3_10, DOB0=>mdout1_3_9); + + pdp_ram_3_2_49: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec28_p03, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec29_r13, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, + DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, + DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, + DOB1=>mdout1_3_19, DOB0=>mdout1_3_18); + + pdp_ram_3_3_48: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec30_p03, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec31_r13, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, + DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, + DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, + DOB1=>mdout1_3_28, DOB0=>mdout1_3_27); + + pdp_ram_4_0_47: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec32_p04, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec33_r14, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_4_8, + DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, DOB5=>mdout1_4_5, + DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, DOB2=>mdout1_4_2, + DOB1=>mdout1_4_1, DOB0=>mdout1_4_0); + + pdp_ram_4_1_46: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec34_p04, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec35_r14, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_17, + DOB7=>mdout1_4_16, DOB6=>mdout1_4_15, DOB5=>mdout1_4_14, + DOB4=>mdout1_4_13, DOB3=>mdout1_4_12, DOB2=>mdout1_4_11, + DOB1=>mdout1_4_10, DOB0=>mdout1_4_9); + + pdp_ram_4_2_45: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec36_p04, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec37_r14, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_26, + DOB7=>mdout1_4_25, DOB6=>mdout1_4_24, DOB5=>mdout1_4_23, + DOB4=>mdout1_4_22, DOB3=>mdout1_4_21, DOB2=>mdout1_4_20, + DOB1=>mdout1_4_19, DOB0=>mdout1_4_18); + + pdp_ram_4_3_44: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec38_p04, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec39_r14, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_4_35, + DOB7=>mdout1_4_34, DOB6=>mdout1_4_33, DOB5=>mdout1_4_32, + DOB4=>mdout1_4_31, DOB3=>mdout1_4_30, DOB2=>mdout1_4_29, + DOB1=>mdout1_4_28, DOB0=>mdout1_4_27); + + pdp_ram_5_0_43: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec40_p05, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec41_r15, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_5_8, + DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, DOB5=>mdout1_5_5, + DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, DOB2=>mdout1_5_2, + DOB1=>mdout1_5_1, DOB0=>mdout1_5_0); + + pdp_ram_5_1_42: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec42_p05, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec43_r15, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_17, + DOB7=>mdout1_5_16, DOB6=>mdout1_5_15, DOB5=>mdout1_5_14, + DOB4=>mdout1_5_13, DOB3=>mdout1_5_12, DOB2=>mdout1_5_11, + DOB1=>mdout1_5_10, DOB0=>mdout1_5_9); + + pdp_ram_5_2_41: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec44_p05, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec45_r15, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_26, + DOB7=>mdout1_5_25, DOB6=>mdout1_5_24, DOB5=>mdout1_5_23, + DOB4=>mdout1_5_22, DOB3=>mdout1_5_21, DOB2=>mdout1_5_20, + DOB1=>mdout1_5_19, DOB0=>mdout1_5_18); + + pdp_ram_5_3_40: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec46_p05, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec47_r15, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_5_35, + DOB7=>mdout1_5_34, DOB6=>mdout1_5_33, DOB5=>mdout1_5_32, + DOB4=>mdout1_5_31, DOB3=>mdout1_5_30, DOB2=>mdout1_5_29, + DOB1=>mdout1_5_28, DOB0=>mdout1_5_27); + + pdp_ram_6_0_39: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec48_p06, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec49_r16, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_6_8, + DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, DOB5=>mdout1_6_5, + DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, DOB2=>mdout1_6_2, + DOB1=>mdout1_6_1, DOB0=>mdout1_6_0); + + pdp_ram_6_1_38: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec50_p06, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec51_r16, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_17, + DOB7=>mdout1_6_16, DOB6=>mdout1_6_15, DOB5=>mdout1_6_14, + DOB4=>mdout1_6_13, DOB3=>mdout1_6_12, DOB2=>mdout1_6_11, + DOB1=>mdout1_6_10, DOB0=>mdout1_6_9); + + pdp_ram_6_2_37: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec52_p06, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec53_r16, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_26, + DOB7=>mdout1_6_25, DOB6=>mdout1_6_24, DOB5=>mdout1_6_23, + DOB4=>mdout1_6_22, DOB3=>mdout1_6_21, DOB2=>mdout1_6_20, + DOB1=>mdout1_6_19, DOB0=>mdout1_6_18); + + pdp_ram_6_3_36: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec54_p06, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec55_r16, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_6_35, + DOB7=>mdout1_6_34, DOB6=>mdout1_6_33, DOB5=>mdout1_6_32, + DOB4=>mdout1_6_31, DOB3=>mdout1_6_30, DOB2=>mdout1_6_29, + DOB1=>mdout1_6_28, DOB0=>mdout1_6_27); + + pdp_ram_7_0_35: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec56_p07, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec57_r17, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_7_8, + DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, DOB5=>mdout1_7_5, + DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, DOB2=>mdout1_7_2, + DOB1=>mdout1_7_1, DOB0=>mdout1_7_0); + + pdp_ram_7_1_34: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec58_p07, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec59_r17, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_17, + DOB7=>mdout1_7_16, DOB6=>mdout1_7_15, DOB5=>mdout1_7_14, + DOB4=>mdout1_7_13, DOB3=>mdout1_7_12, DOB2=>mdout1_7_11, + DOB1=>mdout1_7_10, DOB0=>mdout1_7_9); + + pdp_ram_7_2_33: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec60_p07, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec61_r17, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_26, + DOB7=>mdout1_7_25, DOB6=>mdout1_7_24, DOB5=>mdout1_7_23, + DOB4=>mdout1_7_22, DOB3=>mdout1_7_21, DOB2=>mdout1_7_20, + DOB1=>mdout1_7_19, DOB0=>mdout1_7_18); + + pdp_ram_7_3_32: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec62_p07, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec63_r17, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_7_35, + DOB7=>mdout1_7_34, DOB6=>mdout1_7_33, DOB5=>mdout1_7_32, + DOB4=>mdout1_7_31, DOB3=>mdout1_7_30, DOB2=>mdout1_7_29, + DOB1=>mdout1_7_28, DOB0=>mdout1_7_27); + + pdp_ram_8_0_31: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec64_p08, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec65_r18, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_8_8, + DOB7=>mdout1_8_7, DOB6=>mdout1_8_6, DOB5=>mdout1_8_5, + DOB4=>mdout1_8_4, DOB3=>mdout1_8_3, DOB2=>mdout1_8_2, + DOB1=>mdout1_8_1, DOB0=>mdout1_8_0); + + pdp_ram_8_1_30: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec66_p08, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec67_r18, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_8_17, + DOB7=>mdout1_8_16, DOB6=>mdout1_8_15, DOB5=>mdout1_8_14, + DOB4=>mdout1_8_13, DOB3=>mdout1_8_12, DOB2=>mdout1_8_11, + DOB1=>mdout1_8_10, DOB0=>mdout1_8_9); + + pdp_ram_8_2_29: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec68_p08, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec69_r18, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_8_26, + DOB7=>mdout1_8_25, DOB6=>mdout1_8_24, DOB5=>mdout1_8_23, + DOB4=>mdout1_8_22, DOB3=>mdout1_8_21, DOB2=>mdout1_8_20, + DOB1=>mdout1_8_19, DOB0=>mdout1_8_18); + + pdp_ram_8_3_28: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec70_p08, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec71_r18, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_8_35, + DOB7=>mdout1_8_34, DOB6=>mdout1_8_33, DOB5=>mdout1_8_32, + DOB4=>mdout1_8_31, DOB3=>mdout1_8_30, DOB2=>mdout1_8_29, + DOB1=>mdout1_8_28, DOB0=>mdout1_8_27); + + pdp_ram_9_0_27: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec72_p09, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec73_r19, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_9_8, + DOB7=>mdout1_9_7, DOB6=>mdout1_9_6, DOB5=>mdout1_9_5, + DOB4=>mdout1_9_4, DOB3=>mdout1_9_3, DOB2=>mdout1_9_2, + DOB1=>mdout1_9_1, DOB0=>mdout1_9_0); + + pdp_ram_9_1_26: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec74_p09, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec75_r19, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_9_17, + DOB7=>mdout1_9_16, DOB6=>mdout1_9_15, DOB5=>mdout1_9_14, + DOB4=>mdout1_9_13, DOB3=>mdout1_9_12, DOB2=>mdout1_9_11, + DOB1=>mdout1_9_10, DOB0=>mdout1_9_9); + + pdp_ram_9_2_25: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec76_p09, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec77_r19, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_9_26, + DOB7=>mdout1_9_25, DOB6=>mdout1_9_24, DOB5=>mdout1_9_23, + DOB4=>mdout1_9_22, DOB3=>mdout1_9_21, DOB2=>mdout1_9_20, + DOB1=>mdout1_9_19, DOB0=>mdout1_9_18); + + pdp_ram_9_3_24: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec78_p09, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec79_r19, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_9_35, + DOB7=>mdout1_9_34, DOB6=>mdout1_9_33, DOB5=>mdout1_9_32, + DOB4=>mdout1_9_31, DOB3=>mdout1_9_30, DOB2=>mdout1_9_29, + DOB1=>mdout1_9_28, DOB0=>mdout1_9_27); + + pdp_ram_10_0_23: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec80_p010, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec81_r110, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_10_8, + DOB7=>mdout1_10_7, DOB6=>mdout1_10_6, DOB5=>mdout1_10_5, + DOB4=>mdout1_10_4, DOB3=>mdout1_10_3, DOB2=>mdout1_10_2, + DOB1=>mdout1_10_1, DOB0=>mdout1_10_0); + + pdp_ram_10_1_22: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec82_p010, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec83_r110, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_10_17, + DOB7=>mdout1_10_16, DOB6=>mdout1_10_15, DOB5=>mdout1_10_14, + DOB4=>mdout1_10_13, DOB3=>mdout1_10_12, DOB2=>mdout1_10_11, + DOB1=>mdout1_10_10, DOB0=>mdout1_10_9); + + pdp_ram_10_2_21: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec84_p010, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec85_r110, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_10_26, + DOB7=>mdout1_10_25, DOB6=>mdout1_10_24, DOB5=>mdout1_10_23, + DOB4=>mdout1_10_22, DOB3=>mdout1_10_21, DOB2=>mdout1_10_20, + DOB1=>mdout1_10_19, DOB0=>mdout1_10_18); + + pdp_ram_10_3_20: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec86_p010, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec87_r110, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_10_35, + DOB7=>mdout1_10_34, DOB6=>mdout1_10_33, DOB5=>mdout1_10_32, + DOB4=>mdout1_10_31, DOB3=>mdout1_10_30, DOB2=>mdout1_10_29, + DOB1=>mdout1_10_28, DOB0=>mdout1_10_27); + + pdp_ram_11_0_19: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec88_p011, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec89_r111, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_11_8, + DOB7=>mdout1_11_7, DOB6=>mdout1_11_6, DOB5=>mdout1_11_5, + DOB4=>mdout1_11_4, DOB3=>mdout1_11_3, DOB2=>mdout1_11_2, + DOB1=>mdout1_11_1, DOB0=>mdout1_11_0); + + pdp_ram_11_1_18: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec90_p011, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec91_r111, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_11_17, + DOB7=>mdout1_11_16, DOB6=>mdout1_11_15, DOB5=>mdout1_11_14, + DOB4=>mdout1_11_13, DOB3=>mdout1_11_12, DOB2=>mdout1_11_11, + DOB1=>mdout1_11_10, DOB0=>mdout1_11_9); + + pdp_ram_11_2_17: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec92_p011, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec93_r111, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_11_26, + DOB7=>mdout1_11_25, DOB6=>mdout1_11_24, DOB5=>mdout1_11_23, + DOB4=>mdout1_11_22, DOB3=>mdout1_11_21, DOB2=>mdout1_11_20, + DOB1=>mdout1_11_19, DOB0=>mdout1_11_18); + + pdp_ram_11_3_16: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec94_p011, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec95_r111, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_11_35, + DOB7=>mdout1_11_34, DOB6=>mdout1_11_33, DOB5=>mdout1_11_32, + DOB4=>mdout1_11_31, DOB3=>mdout1_11_30, DOB2=>mdout1_11_29, + DOB1=>mdout1_11_28, DOB0=>mdout1_11_27); + + pdp_ram_12_0_15: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec96_p012, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec97_r112, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_12_8, + DOB7=>mdout1_12_7, DOB6=>mdout1_12_6, DOB5=>mdout1_12_5, + DOB4=>mdout1_12_4, DOB3=>mdout1_12_3, DOB2=>mdout1_12_2, + DOB1=>mdout1_12_1, DOB0=>mdout1_12_0); + + pdp_ram_12_1_14: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec98_p012, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec99_r112, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_12_17, + DOB7=>mdout1_12_16, DOB6=>mdout1_12_15, DOB5=>mdout1_12_14, + DOB4=>mdout1_12_13, DOB3=>mdout1_12_12, DOB2=>mdout1_12_11, + DOB1=>mdout1_12_10, DOB0=>mdout1_12_9); + + pdp_ram_12_2_13: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec100_p012, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec101_r112, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_12_26, + DOB7=>mdout1_12_25, DOB6=>mdout1_12_24, DOB5=>mdout1_12_23, + DOB4=>mdout1_12_22, DOB3=>mdout1_12_21, DOB2=>mdout1_12_20, + DOB1=>mdout1_12_19, DOB0=>mdout1_12_18); + + pdp_ram_12_3_12: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec102_p012, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec103_r112, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_12_35, + DOB7=>mdout1_12_34, DOB6=>mdout1_12_33, DOB5=>mdout1_12_32, + DOB4=>mdout1_12_31, DOB3=>mdout1_12_30, DOB2=>mdout1_12_29, + DOB1=>mdout1_12_28, DOB0=>mdout1_12_27); + + pdp_ram_13_0_11: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec104_p013, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec105_r113, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_13_8, + DOB7=>mdout1_13_7, DOB6=>mdout1_13_6, DOB5=>mdout1_13_5, + DOB4=>mdout1_13_4, DOB3=>mdout1_13_3, DOB2=>mdout1_13_2, + DOB1=>mdout1_13_1, DOB0=>mdout1_13_0); + + pdp_ram_13_1_10: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec106_p013, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec107_r113, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_13_17, + DOB7=>mdout1_13_16, DOB6=>mdout1_13_15, DOB5=>mdout1_13_14, + DOB4=>mdout1_13_13, DOB3=>mdout1_13_12, DOB2=>mdout1_13_11, + DOB1=>mdout1_13_10, DOB0=>mdout1_13_9); + + pdp_ram_13_2_9: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec108_p013, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec109_r113, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_13_26, + DOB7=>mdout1_13_25, DOB6=>mdout1_13_24, DOB5=>mdout1_13_23, + DOB4=>mdout1_13_22, DOB3=>mdout1_13_21, DOB2=>mdout1_13_20, + DOB1=>mdout1_13_19, DOB0=>mdout1_13_18); + + pdp_ram_13_3_8: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec110_p013, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec111_r113, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_13_35, + DOB7=>mdout1_13_34, DOB6=>mdout1_13_33, DOB5=>mdout1_13_32, + DOB4=>mdout1_13_31, DOB3=>mdout1_13_30, DOB2=>mdout1_13_29, + DOB1=>mdout1_13_28, DOB0=>mdout1_13_27); + + pdp_ram_14_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec112_p014, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec113_r114, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_14_8, + DOB7=>mdout1_14_7, DOB6=>mdout1_14_6, DOB5=>mdout1_14_5, + DOB4=>mdout1_14_4, DOB3=>mdout1_14_3, DOB2=>mdout1_14_2, + DOB1=>mdout1_14_1, DOB0=>mdout1_14_0); + + pdp_ram_14_1_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec114_p014, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec115_r114, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_14_17, + DOB7=>mdout1_14_16, DOB6=>mdout1_14_15, DOB5=>mdout1_14_14, + DOB4=>mdout1_14_13, DOB3=>mdout1_14_12, DOB2=>mdout1_14_11, + DOB1=>mdout1_14_10, DOB0=>mdout1_14_9); + + pdp_ram_14_2_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec116_p014, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec117_r114, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_14_26, + DOB7=>mdout1_14_25, DOB6=>mdout1_14_24, DOB5=>mdout1_14_23, + DOB4=>mdout1_14_22, DOB3=>mdout1_14_21, DOB2=>mdout1_14_20, + DOB1=>mdout1_14_19, DOB0=>mdout1_14_18); + + pdp_ram_14_3_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec118_p014, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec119_r114, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_14_35, + DOB7=>mdout1_14_34, DOB6=>mdout1_14_33, DOB5=>mdout1_14_32, + DOB4=>mdout1_14_31, DOB3=>mdout1_14_30, DOB2=>mdout1_14_29, + DOB1=>mdout1_14_28, DOB0=>mdout1_14_27); + + pdp_ram_15_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec120_p015, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec121_r115, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_15_8, + DOB7=>mdout1_15_7, DOB6=>mdout1_15_6, DOB5=>mdout1_15_5, + DOB4=>mdout1_15_4, DOB3=>mdout1_15_3, DOB2=>mdout1_15_2, + DOB1=>mdout1_15_1, DOB0=>mdout1_15_0); + + pdp_ram_15_1_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec122_p015, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec123_r115, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_15_17, + DOB7=>mdout1_15_16, DOB6=>mdout1_15_15, DOB5=>mdout1_15_14, + DOB4=>mdout1_15_13, DOB3=>mdout1_15_12, DOB2=>mdout1_15_11, + DOB1=>mdout1_15_10, DOB0=>mdout1_15_9); + + pdp_ram_15_2_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec124_p015, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec125_r115, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_15_26, + DOB7=>mdout1_15_25, DOB6=>mdout1_15_24, DOB5=>mdout1_15_23, + DOB4=>mdout1_15_22, DOB3=>mdout1_15_21, DOB2=>mdout1_15_20, + DOB1=>mdout1_15_19, DOB0=>mdout1_15_18); + + pdp_ram_15_3_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>dec126_p015, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>dec127_r115, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open, + DOB10=>open, DOB9=>open, DOB8=>mdout1_15_35, + DOB7=>mdout1_15_34, DOB6=>mdout1_15_33, DOB5=>mdout1_15_32, + DOB4=>mdout1_15_31, DOB3=>mdout1_15_30, DOB2=>mdout1_15_29, + DOB1=>mdout1_15_28, DOB0=>mdout1_15_27); + + FF_106: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_105: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_104: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_103: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_102: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_101: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_100: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_99: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_98: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_97: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_96: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_95: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_94: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_93: FD1P3DX + port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_13); + + FF_92: FD1P3DX + port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_14); + + FF_91: FD1P3DX + port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_15); + + FF_90: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_89: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_88: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_87: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_86: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_85: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_84: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_83: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_82: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_81: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_80: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_79: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_78: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_77: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_76: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_75: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_13); + + FF_74: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_14); + + FF_73: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_15); + + FF_72: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_71: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_70: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_69: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_68: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_67: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_66: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_65: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_64: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_63: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_62: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_61: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_60: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_59: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_13); + + FF_58: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_14); + + FF_57: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_15); + + FF_56: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_55: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_54: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_53: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_52: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_51: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_50: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_49: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_48: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_47: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_46: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_45: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_44: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_12); + + FF_43: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_13); + + FF_42: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_14); + + FF_41: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_15); + + FF_40: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_39: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_38: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_37: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_36: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_35: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_34: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_33: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_32: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_31: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_30: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_29: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_28: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_12); + + FF_27: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_13); + + FF_26: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_14); + + FF_25: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_15); + + FF_24: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_23: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_22: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_21: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_20: FD1P3DX + port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff2); + + FF_19: FD1P3DX + port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff2); + + FF_18: FD1P3DX + port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_13_ff2); + + FF_17: FD1P3DX + port map (D=>rptr_14_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_14_ff2); + + FF_16: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_15: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_14: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_13: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_15, CK=>Clock, CD=>Reset, Q=>wcnt_reg_15); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + bdcnt_bctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6); + + bdcnt_bctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>fcount_15, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co6, S0=>ifcount_14, S1=>ifcount_15, COUT=>co7); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1); + + e_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, + B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, COUT=>co6_1); + + e_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_14, + B1=>fcount_15, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2); + + g_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_2, S0=>open, S1=>open, COUT=>co6_2); + + g_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i, + B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_3); + + w_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6_3); + + w_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_14, A1=>wcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>iwcount_14, S1=>iwcount_15, + COUT=>co7_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_4); + + r_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_4); + + r_ctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_14, A1=>rcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_4, S0=>ircount_14, S1=>ircount_15, + COUT=>co7_2); + + mux_35: MUX161 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(0)); + + mux_34: MUX161 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(1)); + + mux_33: MUX161 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(2)); + + mux_32: MUX161 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(3)); + + mux_31: MUX161 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(4)); + + mux_30: MUX161 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(5)); + + mux_29: MUX161 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(6)); + + mux_28: MUX161 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(7)); + + mux_27: MUX161 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(8)); + + mux_26: MUX161 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, + D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, + D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9, + D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9, + D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9, + D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(9)); + + mux_25: MUX161 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, + D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, + D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10, + D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10, + D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10, + D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(10)); + + mux_24: MUX161 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, + D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, + D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11, + D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11, + D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11, + D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(11)); + + mux_23: MUX161 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, + D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, + D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12, + D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12, + D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12, + D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(12)); + + mux_22: MUX161 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, + D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, + D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13, + D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13, + D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13, + D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(13)); + + mux_21: MUX161 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, + D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, + D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14, + D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14, + D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14, + D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(14)); + + mux_20: MUX161 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, + D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, + D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15, + D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15, + D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15, + D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(15)); + + mux_19: MUX161 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, + D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, + D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16, + D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16, + D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16, + D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(16)); + + mux_18: MUX161 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, + D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, + D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17, + D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17, + D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17, + D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(17)); + + mux_17: MUX161 + port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, + D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18, + D6=>mdout1_6_18, D7=>mdout1_7_18, D8=>mdout1_8_18, + D9=>mdout1_9_18, D10=>mdout1_10_18, D11=>mdout1_11_18, + D12=>mdout1_12_18, D13=>mdout1_13_18, D14=>mdout1_14_18, + D15=>mdout1_15_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(18)); + + mux_16: MUX161 + port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, + D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19, + D6=>mdout1_6_19, D7=>mdout1_7_19, D8=>mdout1_8_19, + D9=>mdout1_9_19, D10=>mdout1_10_19, D11=>mdout1_11_19, + D12=>mdout1_12_19, D13=>mdout1_13_19, D14=>mdout1_14_19, + D15=>mdout1_15_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(19)); + + mux_15: MUX161 + port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, + D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20, + D6=>mdout1_6_20, D7=>mdout1_7_20, D8=>mdout1_8_20, + D9=>mdout1_9_20, D10=>mdout1_10_20, D11=>mdout1_11_20, + D12=>mdout1_12_20, D13=>mdout1_13_20, D14=>mdout1_14_20, + D15=>mdout1_15_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(20)); + + mux_14: MUX161 + port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, + D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21, + D6=>mdout1_6_21, D7=>mdout1_7_21, D8=>mdout1_8_21, + D9=>mdout1_9_21, D10=>mdout1_10_21, D11=>mdout1_11_21, + D12=>mdout1_12_21, D13=>mdout1_13_21, D14=>mdout1_14_21, + D15=>mdout1_15_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(21)); + + mux_13: MUX161 + port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, + D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22, + D6=>mdout1_6_22, D7=>mdout1_7_22, D8=>mdout1_8_22, + D9=>mdout1_9_22, D10=>mdout1_10_22, D11=>mdout1_11_22, + D12=>mdout1_12_22, D13=>mdout1_13_22, D14=>mdout1_14_22, + D15=>mdout1_15_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(22)); + + mux_12: MUX161 + port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, + D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23, + D6=>mdout1_6_23, D7=>mdout1_7_23, D8=>mdout1_8_23, + D9=>mdout1_9_23, D10=>mdout1_10_23, D11=>mdout1_11_23, + D12=>mdout1_12_23, D13=>mdout1_13_23, D14=>mdout1_14_23, + D15=>mdout1_15_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(23)); + + mux_11: MUX161 + port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, + D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24, + D6=>mdout1_6_24, D7=>mdout1_7_24, D8=>mdout1_8_24, + D9=>mdout1_9_24, D10=>mdout1_10_24, D11=>mdout1_11_24, + D12=>mdout1_12_24, D13=>mdout1_13_24, D14=>mdout1_14_24, + D15=>mdout1_15_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(24)); + + mux_10: MUX161 + port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, + D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25, + D6=>mdout1_6_25, D7=>mdout1_7_25, D8=>mdout1_8_25, + D9=>mdout1_9_25, D10=>mdout1_10_25, D11=>mdout1_11_25, + D12=>mdout1_12_25, D13=>mdout1_13_25, D14=>mdout1_14_25, + D15=>mdout1_15_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(25)); + + mux_9: MUX161 + port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, + D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26, + D6=>mdout1_6_26, D7=>mdout1_7_26, D8=>mdout1_8_26, + D9=>mdout1_9_26, D10=>mdout1_10_26, D11=>mdout1_11_26, + D12=>mdout1_12_26, D13=>mdout1_13_26, D14=>mdout1_14_26, + D15=>mdout1_15_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(26)); + + mux_8: MUX161 + port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, + D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27, + D6=>mdout1_6_27, D7=>mdout1_7_27, D8=>mdout1_8_27, + D9=>mdout1_9_27, D10=>mdout1_10_27, D11=>mdout1_11_27, + D12=>mdout1_12_27, D13=>mdout1_13_27, D14=>mdout1_14_27, + D15=>mdout1_15_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(27)); + + mux_7: MUX161 + port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, + D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28, + D6=>mdout1_6_28, D7=>mdout1_7_28, D8=>mdout1_8_28, + D9=>mdout1_9_28, D10=>mdout1_10_28, D11=>mdout1_11_28, + D12=>mdout1_12_28, D13=>mdout1_13_28, D14=>mdout1_14_28, + D15=>mdout1_15_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(28)); + + mux_6: MUX161 + port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, + D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29, + D6=>mdout1_6_29, D7=>mdout1_7_29, D8=>mdout1_8_29, + D9=>mdout1_9_29, D10=>mdout1_10_29, D11=>mdout1_11_29, + D12=>mdout1_12_29, D13=>mdout1_13_29, D14=>mdout1_14_29, + D15=>mdout1_15_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(29)); + + mux_5: MUX161 + port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, + D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30, + D6=>mdout1_6_30, D7=>mdout1_7_30, D8=>mdout1_8_30, + D9=>mdout1_9_30, D10=>mdout1_10_30, D11=>mdout1_11_30, + D12=>mdout1_12_30, D13=>mdout1_13_30, D14=>mdout1_14_30, + D15=>mdout1_15_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(30)); + + mux_4: MUX161 + port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, + D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31, + D6=>mdout1_6_31, D7=>mdout1_7_31, D8=>mdout1_8_31, + D9=>mdout1_9_31, D10=>mdout1_10_31, D11=>mdout1_11_31, + D12=>mdout1_12_31, D13=>mdout1_13_31, D14=>mdout1_14_31, + D15=>mdout1_15_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(31)); + + mux_3: MUX161 + port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, + D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32, + D6=>mdout1_6_32, D7=>mdout1_7_32, D8=>mdout1_8_32, + D9=>mdout1_9_32, D10=>mdout1_10_32, D11=>mdout1_11_32, + D12=>mdout1_12_32, D13=>mdout1_13_32, D14=>mdout1_14_32, + D15=>mdout1_15_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(32)); + + mux_2: MUX161 + port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, + D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33, + D6=>mdout1_6_33, D7=>mdout1_7_33, D8=>mdout1_8_33, + D9=>mdout1_9_33, D10=>mdout1_10_33, D11=>mdout1_11_33, + D12=>mdout1_12_33, D13=>mdout1_13_33, D14=>mdout1_14_33, + D15=>mdout1_15_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(33)); + + mux_1: MUX161 + port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, + D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34, + D6=>mdout1_6_34, D7=>mdout1_7_34, D8=>mdout1_8_34, + D9=>mdout1_9_34, D10=>mdout1_10_34, D11=>mdout1_11_34, + D12=>mdout1_12_34, D13=>mdout1_13_34, D14=>mdout1_14_34, + D15=>mdout1_15_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(34)); + + mux_0: MUX161 + port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, + D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35, + D6=>mdout1_6_35, D7=>mdout1_7_35, D8=>mdout1_8_35, + D9=>mdout1_9_35, D10=>mdout1_10_35, D11=>mdout1_11_35, + D12=>mdout1_12_35, D13=>mdout1_13_35, D14=>mdout1_14_35, + D15=>mdout1_15_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(35)); + + precin_inst1073: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_5); + + wcnt_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_13, A1=>wcount_14, B0=>rptr_13, B1=>rptr_14, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co6_5, S0=>wcnt_sub_13, S1=>wcnt_sub_14, COUT=>co7_3); + + wcnt_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_3, S0=>wcnt_sub_15, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>co5_6); + + af_set_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, + COUT=>co6_6); + + af_set_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + WCNT(13) <= fcount_13; + WCNT(14) <= fcount_14; + WCNT(15) <= fcount_15; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst new file mode 100644 index 0000000..4204e1d --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:41:29 + diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn new file mode 100644 index 0000000..8bd1ced --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn @@ -0,0 +1,4721 @@ +(edif fifo_36x4k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 41 31) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + 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0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc new file mode 100644 index 0000000..86d40cd --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x4k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:41:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold 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z|G$>%U=^Y;4C8qJJ2*F?l+salN-1SAj57?w7{f3O!*B+rl(JA(>MUHyxd>%@*5|p2 zucR#1^V$7+pXc4Z^~PR<`ZH>s`m1odLH!+jP3oVRZc_ioG($5nZK2uJ8(U~Dv$oNE zZne=uVeO#BVC|y#CF!80)U!RboLT#5CAYe0wXzP-TCjSkkywYQnOc3+%B&;QF0EtK zsjLC&2I~a%6YCTWQfr8Yg>{BTrFD+Rl{G?>U|pbTVqKz#+!~|D!n#6FrFD&-D{F#Y ef^~ylGwT+;WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_12, B=>rptr_12, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, + DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, + DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, + DOB0=>mdout1_0_0); + + pdp_ram_0_1_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_0_17, DOB7=>mdout1_0_16, + DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, DOB4=>mdout1_0_13, + DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, DOB1=>mdout1_0_10, + DOB0=>mdout1_0_9); + + pdp_ram_0_2_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_0_26, DOB7=>mdout1_0_25, + DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, DOB4=>mdout1_0_22, + DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, DOB1=>mdout1_0_19, + DOB0=>mdout1_0_18); + + pdp_ram_0_3_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_0_35, DOB7=>mdout1_0_34, + DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, DOB4=>mdout1_0_31, + DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, DOB1=>mdout1_0_28, + DOB0=>mdout1_0_27); + + pdp_ram_1_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, + DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, + DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, + DOB0=>mdout1_1_0); + + pdp_ram_1_1_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_1_17, DOB7=>mdout1_1_16, + DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, DOB4=>mdout1_1_13, + DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, DOB1=>mdout1_1_10, + DOB0=>mdout1_1_9); + + pdp_ram_1_2_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_1_26, DOB7=>mdout1_1_25, + DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, DOB4=>mdout1_1_22, + DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, DOB1=>mdout1_1_19, + DOB0=>mdout1_1_18); + + pdp_ram_1_3_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_1_35, DOB7=>mdout1_1_34, + DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, DOB4=>mdout1_1_31, + DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, DOB1=>mdout1_1_28, + DOB0=>mdout1_1_27); + + FF_82: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_81: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_80: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_79: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_78: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_77: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_76: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_75: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_74: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_73: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_72: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_71: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_70: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_69: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_68: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_67: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_66: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_65: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_64: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_63: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_62: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_61: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_60: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_59: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_58: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_57: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_56: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_55: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_54: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_53: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_52: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_51: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_50: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_49: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_48: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_47: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_46: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_45: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_44: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_43: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_42: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_41: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_40: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_39: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_38: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_37: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_36: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_35: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_34: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_33: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_32: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_31: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_30: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_29: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_12); + + FF_28: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_27: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_26: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_25: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_24: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_23: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_22: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_21: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_20: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_19: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_18: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_17: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_16: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_12); + + FF_15: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_14: FD1P3DX + port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff2); + + FF_13: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + bdcnt_bctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5, S0=>ifcount_12, S1=>open, COUT=>co6); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1); + + e_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2); + + g_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_3); + + w_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>open, + COUT=>co6_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_4); + + r_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>open, + COUT=>co6_2); + + mux_35: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff2, + Z=>Q(0)); + + mux_34: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff2, + Z=>Q(1)); + + mux_33: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff2, + Z=>Q(2)); + + mux_32: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff2, + Z=>Q(3)); + + mux_31: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff2, + Z=>Q(4)); + + mux_30: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff2, + Z=>Q(5)); + + mux_29: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff2, + Z=>Q(6)); + + mux_28: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff2, + Z=>Q(7)); + + mux_27: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff2, + Z=>Q(8)); + + mux_26: MUX21 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, SD=>rptr_11_ff2, + Z=>Q(9)); + + mux_25: MUX21 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, SD=>rptr_11_ff2, + Z=>Q(10)); + + mux_24: MUX21 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, SD=>rptr_11_ff2, + Z=>Q(11)); + + mux_23: MUX21 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, SD=>rptr_11_ff2, + Z=>Q(12)); + + mux_22: MUX21 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, SD=>rptr_11_ff2, + Z=>Q(13)); + + mux_21: MUX21 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, SD=>rptr_11_ff2, + Z=>Q(14)); + + mux_20: MUX21 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, SD=>rptr_11_ff2, + Z=>Q(15)); + + mux_19: MUX21 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, SD=>rptr_11_ff2, + Z=>Q(16)); + + mux_18: MUX21 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, SD=>rptr_11_ff2, + Z=>Q(17)); + + mux_17: MUX21 + port map (D0=>mdout1_0_18, D1=>mdout1_1_18, SD=>rptr_11_ff2, + Z=>Q(18)); + + mux_16: MUX21 + port map (D0=>mdout1_0_19, D1=>mdout1_1_19, SD=>rptr_11_ff2, + Z=>Q(19)); + + mux_15: MUX21 + port map (D0=>mdout1_0_20, D1=>mdout1_1_20, SD=>rptr_11_ff2, + Z=>Q(20)); + + mux_14: MUX21 + port map (D0=>mdout1_0_21, D1=>mdout1_1_21, SD=>rptr_11_ff2, + Z=>Q(21)); + + mux_13: MUX21 + port map (D0=>mdout1_0_22, D1=>mdout1_1_22, SD=>rptr_11_ff2, + Z=>Q(22)); + + mux_12: MUX21 + port map (D0=>mdout1_0_23, D1=>mdout1_1_23, SD=>rptr_11_ff2, + Z=>Q(23)); + + mux_11: MUX21 + port map (D0=>mdout1_0_24, D1=>mdout1_1_24, SD=>rptr_11_ff2, + Z=>Q(24)); + + mux_10: MUX21 + port map (D0=>mdout1_0_25, D1=>mdout1_1_25, SD=>rptr_11_ff2, + Z=>Q(25)); + + mux_9: MUX21 + port map (D0=>mdout1_0_26, D1=>mdout1_1_26, SD=>rptr_11_ff2, + Z=>Q(26)); + + mux_8: MUX21 + port map (D0=>mdout1_0_27, D1=>mdout1_1_27, SD=>rptr_11_ff2, + Z=>Q(27)); + + mux_7: MUX21 + port map (D0=>mdout1_0_28, D1=>mdout1_1_28, SD=>rptr_11_ff2, + Z=>Q(28)); + + mux_6: MUX21 + port map (D0=>mdout1_0_29, D1=>mdout1_1_29, SD=>rptr_11_ff2, + Z=>Q(29)); + + mux_5: MUX21 + port map (D0=>mdout1_0_30, D1=>mdout1_1_30, SD=>rptr_11_ff2, + Z=>Q(30)); + + mux_4: MUX21 + port map (D0=>mdout1_0_31, D1=>mdout1_1_31, SD=>rptr_11_ff2, + Z=>Q(31)); + + mux_3: MUX21 + port map (D0=>mdout1_0_32, D1=>mdout1_1_32, SD=>rptr_11_ff2, + Z=>Q(32)); + + mux_2: MUX21 + port map (D0=>mdout1_0_33, D1=>mdout1_1_33, SD=>rptr_11_ff2, + Z=>Q(33)); + + mux_1: MUX21 + port map (D0=>mdout1_0_34, D1=>mdout1_1_34, SD=>rptr_11_ff2, + Z=>Q(34)); + + mux_0: MUX21 + port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff2, + Z=>Q(35)); + + precin_inst389: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_11, A1=>wcnt_sub_msb, B0=>rptr_11, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, + COUT=>co6_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>co6_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>co5_6); + + af_set_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_12, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst new file mode 100644 index 0000000..5adc24e --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:40:02 + diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn new file mode 100644 index 0000000..f005697 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn @@ -0,0 +1,2868 @@ +(edif fifo_36x512_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 40 4) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI35 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI0 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port CER + (direction INPUT)) + (port OCER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO35 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO0 + (direction OUTPUT))))) + (cell fifo_36x512_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(8:0)") 9) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(9:0)") 10) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x512_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b001")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE + (string "OUTREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string "36"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + 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0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc new file mode 100644 index 0000000..c0b44aa --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x512_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:40:02 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual 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b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd new file mode 100644 index 0000000..c76aa9d --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd @@ -0,0 +1,949 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc + +-- Wed Mar 18 14:40:04 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_36x512_oreg is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(8 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(9 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_36x512_oreg; + +architecture Structure of fifo_36x512_oreg is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal rptr_9: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co4: std_logic; + signal co3: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4_1: std_logic; + signal co3_3: std_logic; + signal wcount_9: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_2: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal rptr_6: std_logic; + signal rptr_5: std_logic; + signal wcount_6: std_logic; + signal wcount_5: std_logic; + signal co2_5: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal rptr_8: std_logic; + signal rptr_7: std_logic; + signal wcount_8: std_logic; + signal wcount_7: std_logic; + signal co3_5: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_msb: std_logic; + signal co4_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x512_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>wptr_8, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5, + ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1, + ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>rptr_8, + ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4, + ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, + ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, + ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi, + OCER=>scuba_vhi, CLKR=>Clock, CSR2=>scuba_vlo, + CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17), + DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), + DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), + DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), + DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), + DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), + DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), + DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), + DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18)); + + FF_62: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_61: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_60: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_59: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_58: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_57: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_56: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_55: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_54: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_53: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_52: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_51: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_50: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_49: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_48: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_47: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_46: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_45: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_44: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_43: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_42: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_41: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_40: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_39: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_38: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_37: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_36: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_35: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_34: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_33: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_32: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_31: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_30: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_29: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_28: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_27: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_26: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_25: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_24: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_23: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_22: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_21: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_20: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_19: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_18: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_17: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_16: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_15: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_14: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_13: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_12: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_11: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_2); + + precin_inst272: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_3); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>wcnt_sub_9, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst new file mode 100644 index 0000000..a9a39ca --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst @@ -0,0 +1,3 @@ +Date=03/18/2015 +Time=14:41:45 + diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn new file mode 100644 index 0000000..9a9857b --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn @@ -0,0 +1,6047 @@ +(edif fifo_36x8k_oreg + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 18 14 41 46) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell MUX41 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port D2 + (direction INPUT)) + (port D3 + (direction INPUT)) + (port SD1 + (direction INPUT)) + (port SD2 + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + (port ADA3 + (direction INPUT)) + (port ADA2 + (direction INPUT)) + (port ADA1 + (direction INPUT)) + (port ADA0 + (direction INPUT)) + (port CEA + (direction INPUT)) + (port OCEA + (direction INPUT)) + (port CLKA + (direction INPUT)) + (port WEA + (direction INPUT)) + (port CSA2 + (direction INPUT)) + (port CSA1 + (direction INPUT)) + (port CSA0 + (direction INPUT)) + (port RSTA + (direction INPUT)) + (port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + (port ADB2 + (direction INPUT)) + (port ADB1 + (direction INPUT)) + (port ADB0 + (direction INPUT)) + (port CEB + (direction INPUT)) + (port OCEB + (direction INPUT)) + (port CLKB + (direction INPUT)) + (port WEB + (direction INPUT)) + (port CSB2 + (direction INPUT)) + (port CSB1 + (direction INPUT)) + (port CSB0 + (direction INPUT)) + (port RSTB + (direction INPUT)) + (port DOA17 + (direction OUTPUT)) + (port DOA16 + (direction OUTPUT)) + (port DOA15 + (direction OUTPUT)) + (port DOA14 + (direction OUTPUT)) + (port DOA13 + (direction OUTPUT)) + (port DOA12 + (direction OUTPUT)) + (port DOA11 + (direction OUTPUT)) + (port DOA10 + (direction OUTPUT)) + (port DOA9 + (direction OUTPUT)) + (port DOA8 + (direction OUTPUT)) + (port DOA7 + (direction OUTPUT)) + (port DOA6 + (direction OUTPUT)) + (port DOA5 + (direction OUTPUT)) + (port DOA4 + (direction OUTPUT)) + (port DOA3 + (direction OUTPUT)) + (port DOA2 + (direction OUTPUT)) + (port DOA1 + (direction OUTPUT)) + (port DOA0 + (direction OUTPUT)) + (port DOB17 + (direction OUTPUT)) + (port DOB16 + (direction OUTPUT)) + (port DOB15 + (direction OUTPUT)) + (port DOB14 + (direction OUTPUT)) + (port DOB13 + (direction OUTPUT)) + (port DOB12 + (direction OUTPUT)) + (port DOB11 + (direction OUTPUT)) + (port DOB10 + (direction OUTPUT)) + (port DOB9 + (direction OUTPUT)) + (port DOB8 + (direction OUTPUT)) + (port DOB7 + (direction OUTPUT)) + (port DOB6 + (direction OUTPUT)) + (port DOB5 + (direction OUTPUT)) + (port DOB4 + (direction OUTPUT)) + (port DOB3 + (direction OUTPUT)) + (port DOB2 + (direction OUTPUT)) + (port DOB1 + (direction OUTPUT)) + (port DOB0 + (direction OUTPUT))))) + (cell fifo_36x8k_oreg + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(35:0)") 36) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(12:0)") 13) + (direction INPUT)) + (port (array (rename Q "Q(35:0)") 36) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(13:0)") 14) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_15 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_1_14 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_2_13 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_0_3_12 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b000")) + (property CSDECODE_A + (string "0b000")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_0_11 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_1_10 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_2_9 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_1_3_8 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b001")) + (property CSDECODE_A + (string "0b001")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_0_7 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_1_6 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_2_5 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_2_3_4 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b010")) + (property CSDECODE_A + (string "0b010")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_0_3 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_1_2 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_2_1 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance pdp_ram_3_3_0 + (viewRef view1 + (cellRef DP16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_36x8k_oreg.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_B + (string "0b011")) + (property CSDECODE_A + (string "0b011")) + (property WRITEMODE_B + (string "NORMAL")) + (property WRITEMODE_A + (string "NORMAL")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE_B + (string "OUTREG")) + (property REGMODE_A + (string "OUTREG")) + (property DATA_WIDTH_B + (string "9")) + (property DATA_WIDTH_A + (string "9"))) + (instance FF_90 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_89 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_88 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_87 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_86 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_85 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_84 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_83 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_82 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_81 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_80 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_79 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_78 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_77 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_76 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_75 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_74 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_73 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_72 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_71 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_70 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_69 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_68 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_67 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_66 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_65 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_64 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_63 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_62 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_61 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_60 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_59 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_58 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_57 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_56 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_55 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_54 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_53 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_52 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_51 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_50 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_49 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_48 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_47 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_46 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_45 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_44 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_43 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_42 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_41 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_40 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_39 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_38 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_37 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_36 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_35 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_34 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_33 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef 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(instanceRef pdp_ram_1_2_9)) + (portRef CSA2 (instanceRef pdp_ram_1_2_9)) + (portRef WEB (instanceRef pdp_ram_1_2_9)) + (portRef ADB2 (instanceRef pdp_ram_1_2_9)) + (portRef ADA2 (instanceRef pdp_ram_1_2_9)) + (portRef ADB1 (instanceRef pdp_ram_1_2_9)) + (portRef ADA1 (instanceRef pdp_ram_1_2_9)) + (portRef ADB0 (instanceRef pdp_ram_1_2_9)) + (portRef ADA0 (instanceRef pdp_ram_1_2_9)) + (portRef DIB17 (instanceRef pdp_ram_1_2_9)) + (portRef DIA17 (instanceRef pdp_ram_1_2_9)) + (portRef DIB16 (instanceRef pdp_ram_1_2_9)) + (portRef DIA16 (instanceRef pdp_ram_1_2_9)) + (portRef DIB15 (instanceRef pdp_ram_1_2_9)) + (portRef DIA15 (instanceRef pdp_ram_1_2_9)) + (portRef DIB14 (instanceRef pdp_ram_1_2_9)) + (portRef DIA14 (instanceRef pdp_ram_1_2_9)) + (portRef DIB13 (instanceRef pdp_ram_1_2_9)) + (portRef DIA13 (instanceRef pdp_ram_1_2_9)) + (portRef DIB12 (instanceRef pdp_ram_1_2_9)) + (portRef DIA12 (instanceRef pdp_ram_1_2_9)) + (portRef DIB11 (instanceRef pdp_ram_1_2_9)) + (portRef DIA11 (instanceRef pdp_ram_1_2_9)) + (portRef DIB10 (instanceRef pdp_ram_1_2_9)) + (portRef DIA10 (instanceRef pdp_ram_1_2_9)) + (portRef DIB9 (instanceRef pdp_ram_1_2_9)) + (portRef DIA9 (instanceRef pdp_ram_1_2_9)) + (portRef DIB8 (instanceRef pdp_ram_1_2_9)) + (portRef DIB7 (instanceRef pdp_ram_1_2_9)) + (portRef DIB6 (instanceRef pdp_ram_1_2_9)) + (portRef DIB5 (instanceRef pdp_ram_1_2_9)) + (portRef DIB4 (instanceRef pdp_ram_1_2_9)) + (portRef DIB3 (instanceRef pdp_ram_1_2_9)) + (portRef DIB2 (instanceRef pdp_ram_1_2_9)) + (portRef DIB1 (instanceRef pdp_ram_1_2_9)) + (portRef DIB0 (instanceRef pdp_ram_1_2_9)) + (portRef CSB2 (instanceRef pdp_ram_1_3_8)) + (portRef CSA2 (instanceRef pdp_ram_1_3_8)) + (portRef WEB (instanceRef pdp_ram_1_3_8)) + (portRef ADB2 (instanceRef pdp_ram_1_3_8)) + (portRef ADA2 (instanceRef pdp_ram_1_3_8)) + (portRef ADB1 (instanceRef pdp_ram_1_3_8)) + (portRef ADA1 (instanceRef pdp_ram_1_3_8)) + (portRef ADB0 (instanceRef pdp_ram_1_3_8)) + (portRef ADA0 (instanceRef pdp_ram_1_3_8)) + (portRef DIB17 (instanceRef pdp_ram_1_3_8)) + (portRef DIA17 (instanceRef pdp_ram_1_3_8)) + (portRef DIB16 (instanceRef pdp_ram_1_3_8)) + (portRef DIA16 (instanceRef pdp_ram_1_3_8)) + (portRef DIB15 (instanceRef pdp_ram_1_3_8)) + (portRef DIA15 (instanceRef pdp_ram_1_3_8)) + (portRef DIB14 (instanceRef pdp_ram_1_3_8)) + (portRef DIA14 (instanceRef pdp_ram_1_3_8)) + (portRef DIB13 (instanceRef pdp_ram_1_3_8)) + (portRef DIA13 (instanceRef pdp_ram_1_3_8)) + (portRef DIB12 (instanceRef pdp_ram_1_3_8)) + (portRef DIA12 (instanceRef pdp_ram_1_3_8)) + (portRef DIB11 (instanceRef pdp_ram_1_3_8)) + (portRef DIA11 (instanceRef pdp_ram_1_3_8)) + (portRef DIB10 (instanceRef pdp_ram_1_3_8)) + (portRef DIA10 (instanceRef pdp_ram_1_3_8)) + (portRef DIB9 (instanceRef pdp_ram_1_3_8)) + (portRef DIA9 (instanceRef pdp_ram_1_3_8)) + (portRef DIB8 (instanceRef pdp_ram_1_3_8)) + (portRef DIB7 (instanceRef pdp_ram_1_3_8)) + (portRef DIB6 (instanceRef pdp_ram_1_3_8)) + (portRef DIB5 (instanceRef pdp_ram_1_3_8)) + (portRef DIB4 (instanceRef pdp_ram_1_3_8)) + (portRef DIB3 (instanceRef pdp_ram_1_3_8)) + (portRef DIB2 (instanceRef pdp_ram_1_3_8)) + (portRef DIB1 (instanceRef pdp_ram_1_3_8)) + (portRef DIB0 (instanceRef pdp_ram_1_3_8)) + (portRef CSB2 (instanceRef pdp_ram_2_0_7)) + (portRef CSA2 (instanceRef pdp_ram_2_0_7)) + (portRef WEB (instanceRef pdp_ram_2_0_7)) + (portRef ADB2 (instanceRef pdp_ram_2_0_7)) + (portRef ADA2 (instanceRef pdp_ram_2_0_7)) + (portRef ADB1 (instanceRef pdp_ram_2_0_7)) + (portRef ADA1 (instanceRef pdp_ram_2_0_7)) + (portRef ADB0 (instanceRef pdp_ram_2_0_7)) + (portRef ADA0 (instanceRef pdp_ram_2_0_7)) + (portRef DIB17 (instanceRef pdp_ram_2_0_7)) + (portRef DIA17 (instanceRef pdp_ram_2_0_7)) + (portRef DIB16 (instanceRef pdp_ram_2_0_7)) + (portRef DIA16 (instanceRef pdp_ram_2_0_7)) + (portRef DIB15 (instanceRef pdp_ram_2_0_7)) + (portRef DIA15 (instanceRef pdp_ram_2_0_7)) + (portRef DIB14 (instanceRef pdp_ram_2_0_7)) + (portRef DIA14 (instanceRef pdp_ram_2_0_7)) + (portRef DIB13 (instanceRef pdp_ram_2_0_7)) + (portRef DIA13 (instanceRef pdp_ram_2_0_7)) + (portRef DIB12 (instanceRef pdp_ram_2_0_7)) + (portRef DIA12 (instanceRef pdp_ram_2_0_7)) + (portRef DIB11 (instanceRef pdp_ram_2_0_7)) + (portRef DIA11 (instanceRef pdp_ram_2_0_7)) + (portRef DIB10 (instanceRef pdp_ram_2_0_7)) + (portRef DIA10 (instanceRef pdp_ram_2_0_7)) + (portRef DIB9 (instanceRef pdp_ram_2_0_7)) + (portRef DIA9 (instanceRef pdp_ram_2_0_7)) + (portRef DIB8 (instanceRef pdp_ram_2_0_7)) + (portRef DIB7 (instanceRef pdp_ram_2_0_7)) + (portRef DIB6 (instanceRef pdp_ram_2_0_7)) + (portRef DIB5 (instanceRef pdp_ram_2_0_7)) + (portRef DIB4 (instanceRef pdp_ram_2_0_7)) + (portRef DIB3 (instanceRef pdp_ram_2_0_7)) + (portRef DIB2 (instanceRef pdp_ram_2_0_7)) + (portRef DIB1 (instanceRef pdp_ram_2_0_7)) + (portRef DIB0 (instanceRef pdp_ram_2_0_7)) + (portRef CSB2 (instanceRef pdp_ram_2_1_6)) + (portRef CSA2 (instanceRef pdp_ram_2_1_6)) + (portRef WEB (instanceRef pdp_ram_2_1_6)) + (portRef ADB2 (instanceRef pdp_ram_2_1_6)) + (portRef ADA2 (instanceRef pdp_ram_2_1_6)) + (portRef ADB1 (instanceRef pdp_ram_2_1_6)) + (portRef ADA1 (instanceRef pdp_ram_2_1_6)) + (portRef ADB0 (instanceRef pdp_ram_2_1_6)) + (portRef ADA0 (instanceRef pdp_ram_2_1_6)) + (portRef DIB17 (instanceRef pdp_ram_2_1_6)) + (portRef DIA17 (instanceRef pdp_ram_2_1_6)) + (portRef DIB16 (instanceRef pdp_ram_2_1_6)) + (portRef DIA16 (instanceRef pdp_ram_2_1_6)) + (portRef DIB15 (instanceRef pdp_ram_2_1_6)) + (portRef DIA15 (instanceRef pdp_ram_2_1_6)) + (portRef DIB14 (instanceRef pdp_ram_2_1_6)) + (portRef DIA14 (instanceRef pdp_ram_2_1_6)) + (portRef DIB13 (instanceRef pdp_ram_2_1_6)) + (portRef DIA13 (instanceRef pdp_ram_2_1_6)) + (portRef DIB12 (instanceRef pdp_ram_2_1_6)) + (portRef DIA12 (instanceRef pdp_ram_2_1_6)) + (portRef DIB11 (instanceRef pdp_ram_2_1_6)) + (portRef DIA11 (instanceRef pdp_ram_2_1_6)) + (portRef DIB10 (instanceRef pdp_ram_2_1_6)) + (portRef DIA10 (instanceRef pdp_ram_2_1_6)) + (portRef DIB9 (instanceRef pdp_ram_2_1_6)) + (portRef DIA9 (instanceRef pdp_ram_2_1_6)) + (portRef DIB8 (instanceRef pdp_ram_2_1_6)) + (portRef DIB7 (instanceRef pdp_ram_2_1_6)) + (portRef DIB6 (instanceRef pdp_ram_2_1_6)) + (portRef DIB5 (instanceRef pdp_ram_2_1_6)) + (portRef DIB4 (instanceRef pdp_ram_2_1_6)) + (portRef DIB3 (instanceRef pdp_ram_2_1_6)) + (portRef DIB2 (instanceRef pdp_ram_2_1_6)) + (portRef DIB1 (instanceRef pdp_ram_2_1_6)) + (portRef DIB0 (instanceRef pdp_ram_2_1_6)) + (portRef CSB2 (instanceRef pdp_ram_2_2_5)) + (portRef CSA2 (instanceRef pdp_ram_2_2_5)) + (portRef WEB (instanceRef pdp_ram_2_2_5)) + (portRef ADB2 (instanceRef pdp_ram_2_2_5)) + (portRef ADA2 (instanceRef pdp_ram_2_2_5)) + (portRef ADB1 (instanceRef pdp_ram_2_2_5)) + (portRef ADA1 (instanceRef pdp_ram_2_2_5)) + (portRef ADB0 (instanceRef pdp_ram_2_2_5)) + (portRef ADA0 (instanceRef pdp_ram_2_2_5)) + (portRef DIB17 (instanceRef pdp_ram_2_2_5)) + (portRef DIA17 (instanceRef pdp_ram_2_2_5)) + (portRef DIB16 (instanceRef pdp_ram_2_2_5)) + (portRef DIA16 (instanceRef pdp_ram_2_2_5)) + (portRef DIB15 (instanceRef pdp_ram_2_2_5)) + (portRef DIA15 (instanceRef pdp_ram_2_2_5)) + (portRef DIB14 (instanceRef pdp_ram_2_2_5)) + (portRef DIA14 (instanceRef pdp_ram_2_2_5)) + (portRef DIB13 (instanceRef pdp_ram_2_2_5)) + (portRef DIA13 (instanceRef pdp_ram_2_2_5)) + (portRef DIB12 (instanceRef pdp_ram_2_2_5)) + (portRef DIA12 (instanceRef pdp_ram_2_2_5)) + (portRef DIB11 (instanceRef pdp_ram_2_2_5)) + (portRef DIA11 (instanceRef pdp_ram_2_2_5)) + (portRef DIB10 (instanceRef pdp_ram_2_2_5)) + (portRef DIA10 (instanceRef pdp_ram_2_2_5)) + (portRef DIB9 (instanceRef pdp_ram_2_2_5)) + (portRef DIA9 (instanceRef pdp_ram_2_2_5)) + (portRef DIB8 (instanceRef pdp_ram_2_2_5)) + (portRef DIB7 (instanceRef pdp_ram_2_2_5)) + (portRef DIB6 (instanceRef pdp_ram_2_2_5)) + (portRef DIB5 (instanceRef pdp_ram_2_2_5)) + (portRef DIB4 (instanceRef pdp_ram_2_2_5)) + (portRef DIB3 (instanceRef pdp_ram_2_2_5)) + (portRef DIB2 (instanceRef pdp_ram_2_2_5)) + (portRef DIB1 (instanceRef pdp_ram_2_2_5)) + (portRef DIB0 (instanceRef pdp_ram_2_2_5)) + (portRef CSB2 (instanceRef pdp_ram_2_3_4)) + (portRef CSA2 (instanceRef pdp_ram_2_3_4)) + (portRef WEB (instanceRef pdp_ram_2_3_4)) + (portRef ADB2 (instanceRef pdp_ram_2_3_4)) + (portRef ADA2 (instanceRef pdp_ram_2_3_4)) + (portRef ADB1 (instanceRef pdp_ram_2_3_4)) + (portRef ADA1 (instanceRef pdp_ram_2_3_4)) + (portRef ADB0 (instanceRef pdp_ram_2_3_4)) + (portRef ADA0 (instanceRef pdp_ram_2_3_4)) + (portRef DIB17 (instanceRef pdp_ram_2_3_4)) + (portRef DIA17 (instanceRef pdp_ram_2_3_4)) + (portRef DIB16 (instanceRef pdp_ram_2_3_4)) + (portRef DIA16 (instanceRef pdp_ram_2_3_4)) + (portRef DIB15 (instanceRef pdp_ram_2_3_4)) + (portRef DIA15 (instanceRef pdp_ram_2_3_4)) + (portRef DIB14 (instanceRef pdp_ram_2_3_4)) + (portRef DIA14 (instanceRef pdp_ram_2_3_4)) + (portRef DIB13 (instanceRef pdp_ram_2_3_4)) + (portRef DIA13 (instanceRef pdp_ram_2_3_4)) + (portRef DIB12 (instanceRef pdp_ram_2_3_4)) + (portRef DIA12 (instanceRef pdp_ram_2_3_4)) + (portRef DIB11 (instanceRef pdp_ram_2_3_4)) + (portRef DIA11 (instanceRef pdp_ram_2_3_4)) + (portRef DIB10 (instanceRef pdp_ram_2_3_4)) + (portRef DIA10 (instanceRef pdp_ram_2_3_4)) + (portRef DIB9 (instanceRef pdp_ram_2_3_4)) + (portRef DIA9 (instanceRef pdp_ram_2_3_4)) + (portRef DIB8 (instanceRef pdp_ram_2_3_4)) + (portRef DIB7 (instanceRef pdp_ram_2_3_4)) + (portRef DIB6 (instanceRef pdp_ram_2_3_4)) + (portRef DIB5 (instanceRef pdp_ram_2_3_4)) + (portRef DIB4 (instanceRef pdp_ram_2_3_4)) + (portRef DIB3 (instanceRef pdp_ram_2_3_4)) + (portRef DIB2 (instanceRef pdp_ram_2_3_4)) + (portRef DIB1 (instanceRef pdp_ram_2_3_4)) + (portRef DIB0 (instanceRef pdp_ram_2_3_4)) + (portRef CSB2 (instanceRef pdp_ram_3_0_3)) + (portRef CSA2 (instanceRef pdp_ram_3_0_3)) + (portRef WEB (instanceRef pdp_ram_3_0_3)) + (portRef ADB2 (instanceRef pdp_ram_3_0_3)) + (portRef ADA2 (instanceRef pdp_ram_3_0_3)) + (portRef ADB1 (instanceRef pdp_ram_3_0_3)) + (portRef ADA1 (instanceRef pdp_ram_3_0_3)) + (portRef ADB0 (instanceRef pdp_ram_3_0_3)) + (portRef ADA0 (instanceRef pdp_ram_3_0_3)) + (portRef DIB17 (instanceRef pdp_ram_3_0_3)) + (portRef DIA17 (instanceRef pdp_ram_3_0_3)) + (portRef DIB16 (instanceRef pdp_ram_3_0_3)) + (portRef DIA16 (instanceRef pdp_ram_3_0_3)) + (portRef DIB15 (instanceRef pdp_ram_3_0_3)) + (portRef DIA15 (instanceRef pdp_ram_3_0_3)) + (portRef DIB14 (instanceRef pdp_ram_3_0_3)) + (portRef DIA14 (instanceRef pdp_ram_3_0_3)) + (portRef DIB13 (instanceRef pdp_ram_3_0_3)) + (portRef DIA13 (instanceRef pdp_ram_3_0_3)) + (portRef DIB12 (instanceRef pdp_ram_3_0_3)) + (portRef DIA12 (instanceRef pdp_ram_3_0_3)) + (portRef DIB11 (instanceRef pdp_ram_3_0_3)) + (portRef DIA11 (instanceRef pdp_ram_3_0_3)) + (portRef DIB10 (instanceRef pdp_ram_3_0_3)) + (portRef DIA10 (instanceRef pdp_ram_3_0_3)) + (portRef DIB9 (instanceRef pdp_ram_3_0_3)) + (portRef DIA9 (instanceRef pdp_ram_3_0_3)) + (portRef DIB8 (instanceRef pdp_ram_3_0_3)) + (portRef DIB7 (instanceRef pdp_ram_3_0_3)) + (portRef DIB6 (instanceRef pdp_ram_3_0_3)) + (portRef DIB5 (instanceRef pdp_ram_3_0_3)) + (portRef DIB4 (instanceRef pdp_ram_3_0_3)) + (portRef DIB3 (instanceRef pdp_ram_3_0_3)) + (portRef DIB2 (instanceRef pdp_ram_3_0_3)) + (portRef DIB1 (instanceRef pdp_ram_3_0_3)) + (portRef DIB0 (instanceRef pdp_ram_3_0_3)) + (portRef CSB2 (instanceRef pdp_ram_3_1_2)) + (portRef CSA2 (instanceRef pdp_ram_3_1_2)) + (portRef WEB (instanceRef pdp_ram_3_1_2)) + (portRef ADB2 (instanceRef pdp_ram_3_1_2)) + (portRef ADA2 (instanceRef pdp_ram_3_1_2)) + (portRef ADB1 (instanceRef pdp_ram_3_1_2)) + (portRef ADA1 (instanceRef pdp_ram_3_1_2)) + (portRef ADB0 (instanceRef pdp_ram_3_1_2)) + (portRef ADA0 (instanceRef pdp_ram_3_1_2)) + (portRef DIB17 (instanceRef pdp_ram_3_1_2)) + (portRef DIA17 (instanceRef pdp_ram_3_1_2)) + (portRef DIB16 (instanceRef pdp_ram_3_1_2)) + (portRef DIA16 (instanceRef pdp_ram_3_1_2)) + (portRef DIB15 (instanceRef pdp_ram_3_1_2)) + (portRef DIA15 (instanceRef pdp_ram_3_1_2)) + (portRef DIB14 (instanceRef pdp_ram_3_1_2)) + (portRef DIA14 (instanceRef pdp_ram_3_1_2)) + (portRef DIB13 (instanceRef pdp_ram_3_1_2)) + (portRef DIA13 (instanceRef pdp_ram_3_1_2)) + (portRef DIB12 (instanceRef pdp_ram_3_1_2)) + (portRef DIA12 (instanceRef pdp_ram_3_1_2)) + (portRef DIB11 (instanceRef pdp_ram_3_1_2)) + (portRef DIA11 (instanceRef pdp_ram_3_1_2)) + (portRef DIB10 (instanceRef pdp_ram_3_1_2)) + (portRef DIA10 (instanceRef pdp_ram_3_1_2)) + (portRef DIB9 (instanceRef pdp_ram_3_1_2)) + (portRef DIA9 (instanceRef pdp_ram_3_1_2)) + (portRef DIB8 (instanceRef pdp_ram_3_1_2)) + (portRef DIB7 (instanceRef pdp_ram_3_1_2)) + (portRef DIB6 (instanceRef pdp_ram_3_1_2)) + (portRef DIB5 (instanceRef pdp_ram_3_1_2)) + (portRef DIB4 (instanceRef pdp_ram_3_1_2)) + (portRef DIB3 (instanceRef pdp_ram_3_1_2)) + (portRef DIB2 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fifo_36x8k_oreg + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc new file mode 100644 index 0000000..eac07d5 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_36x8k_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/18/2015 +Time=14:41:45 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=8192 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd new file mode 100644 index 0000000000000000000000000000000000000000..ff7f458294f28db429d52c69a5aed37dd3c88377 GIT binary patch literal 244357 zcmeFa2bdJq@;=-R2nN(q@v4{_K}5uz-ar&#HjvYhRm2@62$Dv`oW`7W6chzRt6V{L z)lny`td65%00c)bA{fVn81I-B)Av@L(>>k2y?pvSe}4Ds-F}{huD9N*bE^7ucXgOP znQSg!q7-*kc-c*f&BOViGrI`8xubLVJP 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zX%~2%ilol)x)exV;B^=33UA*WT{n39XGpuk>zO9)X0DkgNxQ>4u1MO$JdaD-?Fnx{ zoNh08C)bhohBruDcX)%vCE$(7vAPeu@k!FY@Xjfcdcd1pAngZls~MH5r1+hMWJu!?bQQ7??3SmSfMCxe=^O-! z0%;5@Se=5Pcbaq_f<8&oR0Ms+O+%0pcRqrX;;c?ba7rEN z0tADLqze%Y6*mLH>Ebd7&djlT5rWZa(o6*7;-rfaj2F5D!Gt2+ECiEsq~9Z$k|te> zV4Ad>jo<>I%Mi>cvU)iJ`AHp{gJ70yaRq|e((XzGbA+x!aHVWu%+*M@tCIriJq?-}kn1;I+8TM?`(vN|8Z!#UDz2p&t5atI32ZUKVTDZ1OuP1F$}wh+Nuo3zNBy2+C6 zFei3Wq{ZfJn9ve)t}IfB-HD+7`}{6*`Y}tl6v3-0(%t5auFx`b8az^nEl2Q(0vHIL<+I{5q7glE6nFQXGwoVI85HhN`xblbPpgLEp8RUadmVL zBD9L6hY(IGkRC>Op14O4P8atm!c30U#}HnUAw7;zemlpWKzN0?0>W&X)h7{NpCmnn zaBiIRG{Sjxq-PN3#662}p}5rumlRoj4&mJe((?%K&5>R}xI)|-gsa4@MfgaD)pZD; zNR!qhd^$;b5#e*h@)sYlJzesWsZW5;vz9P;;_WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_15: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, + DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, + DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, + DOB0=>mdout1_0_0); + + pdp_ram_0_1_14: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17, + DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14, + DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11, + DOB1=>mdout1_0_10, DOB0=>mdout1_0_9); + + pdp_ram_0_2_13: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_26, + DOB7=>mdout1_0_25, DOB6=>mdout1_0_24, DOB5=>mdout1_0_23, + DOB4=>mdout1_0_22, DOB3=>mdout1_0_21, DOB2=>mdout1_0_20, + DOB1=>mdout1_0_19, DOB0=>mdout1_0_18); + + pdp_ram_0_3_12: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_35, + DOB7=>mdout1_0_34, DOB6=>mdout1_0_33, DOB5=>mdout1_0_32, + DOB4=>mdout1_0_31, DOB3=>mdout1_0_30, DOB2=>mdout1_0_29, + DOB1=>mdout1_0_28, DOB0=>mdout1_0_27); + + pdp_ram_1_0_11: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, + DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, + DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, + DOB0=>mdout1_1_0); + + pdp_ram_1_1_10: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17, + DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14, + DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11, + DOB1=>mdout1_1_10, DOB0=>mdout1_1_9); + + pdp_ram_1_2_9: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_26, + DOB7=>mdout1_1_25, DOB6=>mdout1_1_24, DOB5=>mdout1_1_23, + DOB4=>mdout1_1_22, DOB3=>mdout1_1_21, DOB2=>mdout1_1_20, + DOB1=>mdout1_1_19, DOB0=>mdout1_1_18); + + pdp_ram_1_3_8: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_35, + DOB7=>mdout1_1_34, DOB6=>mdout1_1_33, DOB5=>mdout1_1_32, + DOB4=>mdout1_1_31, DOB3=>mdout1_1_30, DOB2=>mdout1_1_29, + DOB1=>mdout1_1_28, DOB0=>mdout1_1_27); + + pdp_ram_2_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_2_8, DOB7=>mdout1_2_7, + DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, DOB4=>mdout1_2_4, + DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, DOB1=>mdout1_2_1, + DOB0=>mdout1_2_0); + + pdp_ram_2_1_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17, + DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14, + DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11, + DOB1=>mdout1_2_10, DOB0=>mdout1_2_9); + + pdp_ram_2_2_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_26, + DOB7=>mdout1_2_25, DOB6=>mdout1_2_24, DOB5=>mdout1_2_23, + DOB4=>mdout1_2_22, DOB3=>mdout1_2_21, DOB2=>mdout1_2_20, + DOB1=>mdout1_2_19, DOB0=>mdout1_2_18); + + pdp_ram_2_3_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_35, + DOB7=>mdout1_2_34, DOB6=>mdout1_2_33, DOB5=>mdout1_2_32, + DOB4=>mdout1_2_31, DOB3=>mdout1_2_30, DOB2=>mdout1_2_29, + DOB1=>mdout1_2_28, DOB0=>mdout1_2_27); + + pdp_ram_3_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, + OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset, + DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open, + DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open, + DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, + DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open, + DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open, + DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open, + DOB9=>open, DOB8=>mdout1_3_8, DOB7=>mdout1_3_7, + DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, DOB4=>mdout1_3_4, + DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, DOB1=>mdout1_3_1, + DOB0=>mdout1_3_0); + + pdp_ram_3_1_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15), + DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12), + DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17, + DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14, + DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11, + DOB1=>mdout1_3_10, DOB0=>mdout1_3_9); + + pdp_ram_3_2_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(26), DIA7=>Data(25), DIA6=>Data(24), + DIA5=>Data(23), DIA4=>Data(22), DIA3=>Data(21), + DIA2=>Data(20), DIA1=>Data(19), DIA0=>Data(18), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_26, + DOB7=>mdout1_3_25, DOB6=>mdout1_3_24, DOB5=>mdout1_3_23, + DOB4=>mdout1_3_22, DOB3=>mdout1_3_21, DOB2=>mdout1_3_20, + DOB1=>mdout1_3_19, DOB0=>mdout1_3_18); + + pdp_ram_3_3_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(35), DIA7=>Data(34), DIA6=>Data(33), + DIA5=>Data(32), DIA4=>Data(31), DIA3=>Data(30), + DIA2=>Data(29), DIA1=>Data(28), DIA0=>Data(27), + ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7, + ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3, + ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo, + ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i, + CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12, + CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo, + DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo, + DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo, + DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo, + DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo, + DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo, + DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10, + ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, + ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, + ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_35, + DOB7=>mdout1_3_34, DOB6=>mdout1_3_33, DOB5=>mdout1_3_32, + DOB4=>mdout1_3_31, DOB3=>mdout1_3_30, DOB2=>mdout1_3_29, + DOB1=>mdout1_3_28, DOB0=>mdout1_3_27); + + FF_90: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_89: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_88: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_87: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_86: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_85: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_84: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_83: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_82: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_81: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_80: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_79: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_78: FD1P3DX + port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_12); + + FF_77: FD1P3DX + port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_13); + + FF_76: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_75: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_74: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_73: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_72: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_71: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_70: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_69: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_68: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_67: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_66: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_65: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_64: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_63: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_62: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_12); + + FF_61: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_13); + + FF_60: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_59: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_58: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_57: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_56: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_55: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_54: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_53: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_52: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_51: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_50: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_49: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_48: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_12); + + FF_47: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_13); + + FF_46: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_45: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_44: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_43: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_42: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_41: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_40: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_39: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_38: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_37: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_36: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_35: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_34: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_12); + + FF_33: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_13); + + FF_32: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_31: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_30: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_29: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_28: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_27: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_26: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_25: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_24: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_23: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_22: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_21: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_20: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_12); + + FF_19: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_13); + + FF_18: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_17: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_16: FD1P3DX + port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_11_ff2); + + FF_15: FD1P3DX + port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + Q=>rptr_12_ff2); + + FF_14: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_13: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5); + + bdcnt_bctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1); + + e_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12, + B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2); + + g_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, + B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5_3); + + w_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_4); + + r_ctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_2); + + mux_35: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(0)); + + mux_34: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(1)); + + mux_33: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(2)); + + mux_32: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(3)); + + mux_31: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(4)); + + mux_30: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(5)); + + mux_29: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(6)); + + mux_28: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(7)); + + mux_27: MUX41 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(8)); + + mux_26: MUX41 + port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, + D3=>mdout1_3_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(9)); + + mux_25: MUX41 + port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, + D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(10)); + + mux_24: MUX41 + port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, + D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(11)); + + mux_23: MUX41 + port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, + D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(12)); + + mux_22: MUX41 + port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, + D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(13)); + + mux_21: MUX41 + port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, + D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(14)); + + mux_20: MUX41 + port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, + D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(15)); + + mux_19: MUX41 + port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, + D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(16)); + + mux_18: MUX41 + port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, + D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(17)); + + mux_17: MUX41 + port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, + D3=>mdout1_3_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(18)); + + mux_16: MUX41 + port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, + D3=>mdout1_3_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(19)); + + mux_15: MUX41 + port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, + D3=>mdout1_3_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(20)); + + mux_14: MUX41 + port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, + D3=>mdout1_3_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(21)); + + mux_13: MUX41 + port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, + D3=>mdout1_3_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(22)); + + mux_12: MUX41 + port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, + D3=>mdout1_3_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(23)); + + mux_11: MUX41 + port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, + D3=>mdout1_3_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(24)); + + mux_10: MUX41 + port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, + D3=>mdout1_3_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(25)); + + mux_9: MUX41 + port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, + D3=>mdout1_3_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(26)); + + mux_8: MUX41 + port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, + D3=>mdout1_3_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(27)); + + mux_7: MUX41 + port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, + D3=>mdout1_3_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(28)); + + mux_6: MUX41 + port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, + D3=>mdout1_3_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(29)); + + mux_5: MUX41 + port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, + D3=>mdout1_3_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(30)); + + mux_4: MUX41 + port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, + D3=>mdout1_3_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(31)); + + mux_3: MUX41 + port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, + D3=>mdout1_3_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(32)); + + mux_2: MUX41 + port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, + D3=>mdout1_3_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(33)); + + mux_1: MUX41 + port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, + D3=>mdout1_3_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(34)); + + mux_0: MUX41 + port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, + D3=>mdout1_3_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, + Z=>Q(35)); + + precin_inst474: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_3); + + wcnt_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>wcnt_sub_13, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>co2_6); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, + COUT=>co3_6); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, + COUT=>co4_6); + + af_set_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, + COUT=>co5_6); + + af_set_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + WCNT(6) <= fcount_6; + WCNT(7) <= fcount_7; + WCNT(8) <= fcount_8; + WCNT(9) <= fcount_9; + WCNT(10) <= fcount_10; + WCNT(11) <= fcount_11; + WCNT(12) <= fcount_12; + WCNT(13) <= fcount_13; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/PLL/PLL.sbx b/lattice/ecp5/PLL/PLL.sbx new file mode 100644 index 0000000..5cdb2e4 --- /dev/null +++ b/lattice/ecp5/PLL/PLL.sbx @@ -0,0 +1,661 @@ + + + + LATTICE + LOCAL + PLL + 1.0 + + + Diamond_Synthesis + synthesis + + + Diamond_Simulation + simulation + + + + + + + + pll_in200_out100_CLKI + pll_in200_out100_CLKI + + in + + + + pll_in200_out100.CLKI + + + + + pll_in200_out100_CLKOP + pll_in200_out100_CLKOP + + out + + + + pll_in200_out100.CLKOP + + + + + pll_in200_out100_CLKOS + pll_in200_out100_CLKOS + + out + + + + pll_in200_out100.CLKOS + + + + + pll_in200_out100_LOCK + pll_in200_out100_LOCK + + out + + + + pll_in200_out100.LOCK + + + + + + + LFE5UM-85F-8MG285C + synplify + 2015-03-17.15:29:30 + 2015-03-17.15:44:52 + 3.4.0.80 + VHDL + + true + false + false + true + false + false + false + false + false + false + false + + + + + + + + LATTICE + LOCAL + PLL + 1.0 + + + pll_in200_out100 + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.7 + + + Diamond_Simulation + simulation + + ./pll_in200_out100/pll_in200_out100.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_in200_out100/pll_in200_out100.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + CLKI + CLKI + + in + + + + true + + + + + CLKOP + CLKOP + + out + + + + CLKOS + CLKOS + + out + + + + LOCK + LOCK + + out + + + + + + synplify + 2015-03-17.15:44:52 + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + IO:2;PLL:1;DLL:0 + + + + CLKI + IO + + Inst1_IB + true + true + false + IO + true + + + + CLKI~ + IO + + true + false + IO + true + + + + pll_in200_out100 + GXPLL + + true + false + GXPLL + + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CSFBGA285 + + + PartName + LFE5UM-85F-8MG285C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + C + + + + CoreName + PLL + + + CoreRevision + 5.7 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 03/17/2015 + + + ModuleName + pll_in200_out100 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 15:42:59 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 1 + + + CLKI_DIV + 2 + + + CLKI_FREQ + 200 + + + CLKOP_ACTUAL_FREQ + 100.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 6 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 100.00 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + DISABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 200.000000 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 1 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 100.00 + + + CLKOS_MUXB + ENABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + None + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + None + + + PLLRST_ENA + DISABLED + + + PLL_BW + 8.185 + + + PLL_LOCK_MODE + ENABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 1 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 600.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 + + + + + GXPLL + 1 + + true + true + GXPLL + + pll_in200_out100 + + + IO + 1 + + true + true + IO + + CLKI + CLKI~ + + + pll + 0 + + true + false + PLL + + CLKI + CLKI~ + pll_in200_out100 + + + + + + + + + pll_in200_out100_CLKI + pll_in200_out100_CLKI + + + sys_yes + + + + + + + pll_in200_out100_CLKOP + pll_in200_out100_CLKOP + + + + + pll_in200_out100_CLKOS + pll_in200_out100_CLKOS + + + + + pll_in200_out100_LOCK + pll_in200_out100_LOCK + + + + + + diff --git a/lattice/ecp5/PLL/archv/pll_in200_out100.zip b/lattice/ecp5/PLL/archv/pll_in200_out100.zip new file mode 100644 index 0000000000000000000000000000000000000000..c8b86e5fb849eaae15486cc04382dab9d5363983 GIT binary patch literal 136545 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z>G9Ei57*@WD$5t(Kqm$xO&%3s#+tgyHUQ?JC*Y6~%WUfkk9L`TA*Wzjt`ZvD3$2%M z0pmz!?*Z(tux|i%)!0oCmX@IKPLB-^MlwZadxi|aV5lP_n39_25>i$K(jf#=83a~V!Yp$J z%jaQmp#`uI>gpnyOKBz%;4+xSI>2I+%(KP|caas?U25sQv}wAw1JSmbsc#w(kWWY2 zSyj5a+KDL$;<^;>UULP93eeR`j`!?pj_-oi9IxNi9A6u&x#ikgj_;7way)?7aE*01 zZyios%ds!}_aKEmV4v&i8mva2aCLGwYAd)bxtr~NjyJEazDlp)n&iHQbo9~QvO(^< zT0h6*N>{h5Jr2WpG%Hffewl9r9INyB@bl1@zd$Udt9)iUsln62OfbN+2Cwa!fpau)@a^)2pjn zZP=`Fbi0Zl{_^e4ZO0EbyGcjlVV92`=K$C=hpU zw_+o?YYqM-CvQODZZ%@l@cCLKI, O=>buf_CLKI); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 6, CLKFB_DIV=> 1, + CLKI_DIV=> 2, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>buf_CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd b/lattice/ecp5/PLL/pll_in200_out100/pll_in200_out100_ngd.asd new file mode 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+SC<)V=RM"bCO63klQ#A3$LM_D NO_GLF"=RH"#QM0Q4_A +">SS +SSR +S)S)SSS +S +SC<)V=RM"bCO63kl u]Xp3pp#_$MLODN F_LGH"R=p"up#QM0"_j>S +SSRSS +SSRSS +SSRSS +SqS +SqS +SqS +SqSS"/ +SSSS +SSR +SqSS +SSR"/ +SSSS +SqS +SqS +SqSS +SSR"/ +SSS"/ +SSS"/ +SSS +SqSS +SSR"/ +SSSS +SqSS"/ +SSSS +SSR +SqS +SqS"/ +SSSSSS/S<)>CV +/S<7>CV +]sC + +@ diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt new file mode 100644 index 0000000..085ef99 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/licbug.txt @@ -0,0 +1 @@ +MainAppInit 50 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr new file mode 100644 index 0000000..b4a79ee --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.areasrr @@ -0,0 +1,16 @@ +---------------------------------------------------------------------- +Report for cell pll_in200_out100.structure + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 1 + Cell usage: + cell count Res Usage(%) + EHXPLLL 1 100.0 + GSR 1 100.0 + IB 1 100.0 + PUR 1 100.0 + VHI 1 100.0 + VLO 1 100.0 + + TOTAL 6 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn new file mode 100644 index 0000000..e7f7754 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn @@ -0,0 +1,236 @@ +(edif pll_in200_out100 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2015 3 17 15 43 13) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "J-2014.09-SP2, mapper maprc, Build 2453R")) + ) + ) + (library ecp5um + (edifLevel 0) + (technology (numberDefinition )) + (cell EHXPLLL (cellType GENERIC) + (view syn_black_box (viewType NETLIST) + (interface + (port CLKI (direction INPUT)) + (port CLKFB (direction INPUT)) + (port PHASESEL1 (direction INPUT)) + (port PHASESEL0 (direction INPUT)) + (port PHASEDIR (direction INPUT)) + (port PHASESTEP (direction INPUT)) + (port PHASELOADREG (direction INPUT)) + (port STDBY (direction INPUT)) + (port PLLWAKESYNC (direction INPUT)) + (port RST (direction INPUT)) + (port ENCLKOP (direction INPUT)) + (port ENCLKOS (direction INPUT)) + (port ENCLKOS2 (direction INPUT)) + (port ENCLKOS3 (direction INPUT)) + (port CLKOP (direction OUTPUT)) + (port CLKOS (direction OUTPUT)) + (port CLKOS2 (direction OUTPUT)) + (port CLKOS3 (direction OUTPUT)) + (port LOCK (direction OUTPUT)) + (port INTLOCK (direction OUTPUT)) + (port REFCLK (direction OUTPUT)) + (port CLKINTFB (direction OUTPUT)) + ) + (property CLKI_DIV (integer 1)) + (property CLKFB_DIV (integer 1)) + (property CLKOP_DIV (integer 8)) + (property CLKOS_DIV (integer 8)) + (property CLKOS2_DIV (integer 8)) + (property CLKOS3_DIV (integer 8)) + (property CLKOP_ENABLE (string "ENABLED")) + (property CLKOS_ENABLE (string "DISABLED")) + (property CLKOS2_ENABLE (string "DISABLED")) + (property CLKOS3_ENABLE (string "DISABLED")) + (property CLKOP_CPHASE (integer 0)) + (property CLKOS_CPHASE (integer 0)) + (property CLKOS2_CPHASE (integer 0)) + (property CLKOS3_CPHASE (integer 0)) + (property CLKOP_FPHASE (integer 0)) + (property CLKOS_FPHASE (integer 0)) + (property CLKOS2_FPHASE (integer 0)) + (property CLKOS3_FPHASE (integer 0)) + (property FEEDBK_PATH (string "CLKOP")) + (property CLKOP_TRIM_POL (string "RISING")) + (property CLKOP_TRIM_DELAY (integer 0)) + (property CLKOS_TRIM_POL (string "RISING")) + (property CLKOS_TRIM_DELAY (integer 0)) + (property OUTDIVIDER_MUXA (string "DIVA")) + (property OUTDIVIDER_MUXB (string "DIVB")) + (property OUTDIVIDER_MUXC (string "DIVC")) + (property OUTDIVIDER_MUXD (string "DIVD")) + (property PLL_LOCK_MODE (integer 0)) + (property PLL_LOCK_DELAY (integer 200)) + (property STDBY_ENABLE (string "DISABLED")) + (property REFIN_RESET (string "DISABLED")) + (property SYNC_ENABLE (string "DISABLED")) + (property INT_LOCK_STICKY (string "ENABLED")) + (property DPHASE_SOURCE (string "DISABLED")) + (property PLLRST_ENA (string "DISABLED")) + (property INTFB_WAKE (string "DISABLED")) + (property orig_inst_of (string "EHXPLLL")) + ) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell pll_in200_out100 (cellType GENERIC) + (view structure (viewType NETLIST) + (interface + (port CLKI (direction INPUT)) + (port CLKOP (direction OUTPUT)) + (port CLKOS (direction OUTPUT)) + (port LOCK (direction OUTPUT)) + ) + (contents + (instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance Inst1_IB (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + (property IO_TYPE (string "LVDS")) + ) + (instance PLLInst_0 (viewRef syn_black_box (cellRef EHXPLLL (libraryRef ecp5um))) + (property INTFB_WAKE (string "DISABLED")) + (property PLLRST_ENA (string "DISABLED")) + (property DPHASE_SOURCE (string "DISABLED")) + (property STDBY_ENABLE (string "DISABLED")) + (property PLL_LOCK_MODE (integer 0)) + (property OUTDIVIDER_MUXD (string "DIVD")) + (property OUTDIVIDER_MUXC (string "DIVC")) + (property OUTDIVIDER_MUXB (string "DIVB")) + (property OUTDIVIDER_MUXA (string "DIVA")) + (property CLKOS_TRIM_DELAY (integer 0)) + (property CLKOS_TRIM_POL (string "FALLING")) + (property CLKOP_TRIM_DELAY (integer 0)) + (property CLKOP_TRIM_POL (string "FALLING")) + (property FEEDBK_PATH (string "CLKOP")) + (property CLKOS3_FPHASE (integer 0)) + (property CLKOS2_FPHASE (integer 0)) + (property CLKOS_FPHASE (integer 0)) + (property CLKOP_FPHASE (integer 0)) + (property CLKOS3_CPHASE (integer 0)) + (property CLKOS2_CPHASE (integer 0)) + (property CLKOS_CPHASE (integer 0)) + (property CLKOP_CPHASE (integer 5)) + (property CLKOS3_ENABLE (string "DISABLED")) + (property CLKOS2_ENABLE (string "DISABLED")) + (property CLKOS_ENABLE (string "ENABLED")) + (property CLKOP_ENABLE (string "ENABLED")) + (property CLKOS3_DIV (integer 1)) + (property CLKOS2_DIV (integer 1)) + (property CLKOS_DIV (integer 1)) + (property CLKOP_DIV (integer 6)) + (property CLKFB_DIV (integer 1)) + (property CLKI_DIV (integer 2)) + (property LPF_RESISTOR (string "72")) + (property ICP_CURRENT (string "9")) + (property FREQUENCY_PIN_CLKI (string "200.000000")) + (property FREQUENCY_PIN_CLKOP (string "100.000000")) + (property FREQUENCY_PIN_CLKOS (string "200.000000")) + ) + (net CLKI (joined + (portRef CLKI) + (portRef I (instanceRef Inst1_IB)) + )) + (net CLKOP (joined + (portRef CLKOP (instanceRef PLLInst_0)) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOP) + )) + (net CLKOS (joined + (portRef CLKOS (instanceRef PLLInst_0)) + (portRef CLKOS) + )) + (net LOCK (joined + (portRef LOCK (instanceRef PLLInst_0)) + (portRef LOCK) + )) + (net CLKOS2 (joined + (portRef CLKOS2 (instanceRef PLLInst_0)) + )) + (net CLKOS3 (joined + (portRef CLKOS3 (instanceRef PLLInst_0)) + )) + (net INTLOCK (joined + (portRef INTLOCK (instanceRef PLLInst_0)) + )) + (net CLKINTFB (joined + (portRef CLKINTFB (instanceRef PLLInst_0)) + )) + (net buf_CLKI (joined + (portRef O (instanceRef Inst1_IB)) + (portRef CLKI (instanceRef PLLInst_0)) + )) + (net REFCLK (joined + (portRef REFCLK (instanceRef PLLInst_0)) + )) + (net GND (joined + (portRef Z (instanceRef GND_0)) + (portRef ENCLKOS3 (instanceRef PLLInst_0)) + (portRef ENCLKOS2 (instanceRef PLLInst_0)) + (portRef ENCLKOS (instanceRef PLLInst_0)) + (portRef ENCLKOP (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)) + (portRef PLLWAKESYNC (instanceRef PLLInst_0)) + (portRef STDBY (instanceRef PLLInst_0)) + (portRef PHASELOADREG (instanceRef PLLInst_0)) + (portRef PHASESTEP (instanceRef PLLInst_0)) + (portRef PHASEDIR (instanceRef PLLInst_0)) + (portRef PHASESEL0 (instanceRef PLLInst_0)) + (portRef PHASESEL1 (instanceRef PLLInst_0)) + )) + (net VCC (joined + (portRef Z (instanceRef VCC_0)) + (portRef GSR (instanceRef GSR_INST)) + )) + ) + (property NGD_DRC_MASK (integer 1)) + (property dont_touch (integer 1)) + (property orig_inst_of (string "pll_in200_out100")) + ) + ) + ) + (design pll_in200_out100 (cellRef pll_in200_out100 (libraryRef work)) + (property PART (string "lfe5um_25f-6") )) +) diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.fse new file mode 100644 index 0000000..e69de29 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm new file mode 100644 index 0000000..db9de8a --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.htm @@ -0,0 +1,9 @@ + + + syntmp/pll_in200_out100_srr.htm log file + + + + + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj new file mode 100644 index 0000000..1131742 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj @@ -0,0 +1,46 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj +#-- Written on Tue Mar 17 15:43:11 2015 + + +#device options +set_option -technology ecp5um +set_option -part LFE5UM-85F +set_option -speed_grade 8 + +#use verilog 2001 standard option +set_option -vlog_std v2001 + +#map options +set_option -frequency 100 +set_option -fanout_limit 50 +set_option -disable_io_insertion true +set_option -retiming false +set_option -pipe false +set_option -pipe false +set_option -force_gsr false + +#simulation options +set_option -write_verilog true +set_option -write_vhdl true + +#timing analysis options + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#-- add_file options +add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" +add_file -constraint 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b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf new file mode 100644 index 0000000..15854e8 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf @@ -0,0 +1,373 @@ +#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014 +#install: /opt/synopsys/J-2014.09-SP2 +#OS: Linux +#Hostname: depc363 + +#Implementation: syn_results + +Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +Running on host :depc363 +Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns +@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. +VHDL syntax check successful! +@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box +Post processing for ecp5um.vhi.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box +Post processing for ecp5um.ib.syn_black_box +Post processing for work.pll_in200_out100.structure +@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:12 2015 + +###########################################################] +Pre-mapping Report + +Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc +@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt +Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +@S |Clock Summary +**************** + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------- +System 100.0 MHz 10.000 system system_clkgroup +================================================================= + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:13 2015 + +###########################################################] +Map & Optimize Report + +Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +------------------------------------------------------------ + + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing EDIF Netlist and constraint files +J-2014.09-SP2 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Mar 17 15:43:14 2015 +# + + +Top view: pll_in200_out100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 +============================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 +=============================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKOP + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - +CLKOP Net - - - - 2 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +================================================================================= + + + +##### END OF TIMING REPORT #####] + + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +--------------------------------------- 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Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +Running on host :depc363 +Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns +@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. +VHDL syntax check successful! +@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box +Post processing for ecp5um.vhi.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box +Post processing for ecp5um.ib.syn_black_box +Post processing for work.pll_in200_out100.structure +@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:12 2015 + +###########################################################] +Pre-mapping Report + +Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc +@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt +Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +@S |Clock Summary +**************** + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------- +System 100.0 MHz 10.000 system system_clkgroup +================================================================= + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:13 2015 + +###########################################################] +Map & Optimize Report + +Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +------------------------------------------------------------ + + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing EDIF Netlist and constraint files +J-2014.09-SP2 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Mar 17 15:43:14 2015 +# + + +Top view: pll_in200_out100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 +============================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 +=============================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKOP + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - +CLKOP Net - - - - 2 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +================================================================================= + + + +##### END OF TIMING REPORT #####] + + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 1 + + +Details: +EHXPLLL: 1 +GSR: 1 +IB: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:14 2015 + +###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs new file mode 100644 index 0000000000000000000000000000000000000000..57d784a7e92807440912f5797ecfa3f72def1659 GIT binary patch literal 5590 zcmV;{6)EZ;iwFP!000001AJ25j}kEuf9J25Ku9zJx?gaCCl!4-b8_Us=gn@nu=To~ zO*<7g;g5HUcP47$Qzz-~bK2>23cW*8l3q{MlqYS}Xfm3>PLa``;NmoqvVazjLBW^G zL3#)2a#Q4+G=nTjmyA9Pwl`X88o<5~jkeFq&7cn2P^9nhJHsQRSTJRa{owSuC3v%a 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zx9n^1F`u!@xRg+=MJ);5lO{09@)BNz= z)Q^$Ay3ep#we!cw!1|<Ece zAFuXO&CU0(ckcIe=j}7+!mf>R^67ZlULQ-Zt>G!&L)7fS(T8VoqIUL_`UURa$d-ST z9UAOrSqSZZ<6Z9>JhXGL{V&qRRI|eRjcj=?Q~lM)y0_kAvoIc@n=|K_vxWJ(Rd4?Q z#y*pB75+3%@fs5snfHqNz1*Ms|9>{lXPYgDW47>~^vpAl`1-@xw{?B$YI=n2LiH>& zJsp3%9>*RSnejC4YOvTI)y*?LD6<0;c$O+3O6&rm+PJ~RrS zl(<#&eATyJ7vJHqxL4%*UEe$oU5!-(j=CAOF&w!c>!H`hX-p{{eSxbt%)hv>f^30@ k@t^vBePQ!o00030|Kf5`-~s>u0RR630A8gjhkY#o0A2n@&;S4c literal 0 HcmV?d00001 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm new file mode 100644 index 0000000..89d3c09 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vhm @@ -0,0 +1,139 @@ +-- +-- Written by Synplicity +-- Product Version "J-2014.09-SP2" +-- Program "Synplify Pro", Mapper "maprc, Build 2453R" +-- Tue Mar 17 15:43:14 2015 +-- + +-- +-- Written by Synplify Pro version Build 2453R +-- Tue Mar 17 15:43:14 2015 +-- + +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library synplify; +use synplify.components.all; +library pmi; +use pmi.pmi_components.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_in200_out100 is +port( + CLKI : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic); +end pll_in200_out100; + +architecture beh of pll_in200_out100 is + signal CLKOP_0 : std_logic ; + signal CLKOS2 : std_logic ; + signal CLKOS3 : std_logic ; + signal INTLOCK : std_logic ; + signal CLKINTFB : std_logic ; + signal BUF_CLKI : std_logic ; + signal REFCLK : std_logic ; + signal GND : std_logic ; + signal VCC : std_logic ; + component EHXPLLL + port( + CLKI : in std_logic; + CLKFB : in std_logic; + PHASESEL1 : in std_logic; + PHASESEL0 : in std_logic; + PHASEDIR : in std_logic; + PHASESTEP : in std_logic; + PHASELOADREG : in std_logic; + STDBY : in std_logic; + PLLWAKESYNC : in std_logic; + RST : in std_logic; + ENCLKOP : in std_logic; + ENCLKOS : in std_logic; + ENCLKOS2 : in std_logic; + ENCLKOS3 : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + CLKOS2 : out std_logic; + CLKOS3 : out std_logic; + LOCK : out std_logic; + INTLOCK : out std_logic; + REFCLK : out std_logic; + CLKINTFB : out std_logic ); + end component; +begin +GND_0: VLO port map ( + Z => GND); +VCC_0: VHI port map ( + Z => VCC); +PUR_INST: PUR port map ( + PUR => VCC); +GSR_INST: GSR port map ( + GSR => VCC); +INST1_IB: IB port map ( + I => CLKI, + O => BUF_CLKI); +PLLINST_0: EHXPLLL + generic map( + CLKI_DIV => 2, + CLKFB_DIV => 1, + CLKOP_DIV => 6, + CLKOS_DIV => 1, + CLKOS2_DIV => 1, + CLKOS3_DIV => 1, + CLKOP_ENABLE => "ENABLED", + CLKOS_ENABLE => "ENABLED", + CLKOS2_ENABLE => "DISABLED", + CLKOS3_ENABLE => "DISABLED", + CLKOP_CPHASE => 5, + CLKOS_CPHASE => 0, + CLKOS2_CPHASE => 0, + CLKOS3_CPHASE => 0, + CLKOP_FPHASE => 0, + CLKOS_FPHASE => 0, + CLKOS2_FPHASE => 0, + CLKOS3_FPHASE => 0, + FEEDBK_PATH => "CLKOP", + CLKOP_TRIM_POL => "FALLING", + CLKOP_TRIM_DELAY => 0, + CLKOS_TRIM_POL => "FALLING", + CLKOS_TRIM_DELAY => 0, + OUTDIVIDER_MUXA => "DIVA", + OUTDIVIDER_MUXB => "DIVB", + OUTDIVIDER_MUXC => "DIVC", + OUTDIVIDER_MUXD => "DIVD", + PLL_LOCK_MODE => 0, + STDBY_ENABLE => "DISABLED", + DPHASE_SOURCE => "DISABLED", + PLLRST_ENA => "DISABLED", + INTFB_WAKE => "DISABLED" + ) + port map ( + CLKI => BUF_CLKI, + CLKFB => CLKOP_0, + PHASESEL1 => GND, + PHASESEL0 => GND, + PHASEDIR => GND, + PHASESTEP => GND, + PHASELOADREG => GND, + STDBY => GND, + PLLWAKESYNC => GND, + RST => GND, + ENCLKOP => GND, + ENCLKOS => GND, + ENCLKOS2 => GND, + ENCLKOS3 => GND, + CLKOP => CLKOP_0, + CLKOS => CLKOS, + CLKOS2 => CLKOS2, + CLKOS3 => CLKOS3, + LOCK => LOCK, + INTLOCK => INTLOCK, + REFCLK => REFCLK, + CLKINTFB => CLKINTFB); +CLKOP <= CLKOP_0; +end beh; + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm new file mode 100644 index 0000000..2c7d22b --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.vm @@ -0,0 +1,120 @@ +// +// Written by Synplify Pro +// Product Version "J-2014.09-SP2" +// Program "Synplify Pro", Mapper "maprc, Build 2453R" +// Tue Mar 17 15:43:14 2015 +// +// Source file index table: +// Object locations will have the form : +// file 0 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd " +// file 1 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd " +// file 2 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd " +// file 3 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd " +// file 4 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd " +// file 5 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd " +// file 6 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd " +// file 7 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd " +// file 8 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd " +// file 9 "\/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd " +// file 10 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc " + +`timescale 100 ps/100 ps +module pll_in200_out100 ( + CLKI, + CLKOP, + CLKOS, + LOCK +) +; +input CLKI ; +output CLKOP ; +output CLKOS ; +output LOCK ; +wire CLKI ; +wire CLKOP ; +wire CLKOS ; +wire LOCK ; +wire CLKOS2 ; +wire CLKOS3 ; +wire INTLOCK ; +wire CLKINTFB ; +wire buf_CLKI ; +wire REFCLK ; +wire GND ; +wire VCC ; + VLO GND_0 ( + .Z(GND) +); + VHI VCC_0 ( + .Z(VCC) +); + PUR PUR_INST ( + .PUR(VCC) +); + GSR GSR_INST ( + .GSR(VCC) +); +// @8:52 + IB Inst1_IB ( + .I(CLKI), + .O(buf_CLKI) +); +// @8:61 + EHXPLLL PLLInst_0 ( + .CLKI(buf_CLKI), + .CLKFB(CLKOP), + .PHASESEL1(GND), + .PHASESEL0(GND), + .PHASEDIR(GND), + .PHASESTEP(GND), + .PHASELOADREG(GND), + .STDBY(GND), + .PLLWAKESYNC(GND), + .RST(GND), + .ENCLKOP(GND), + .ENCLKOS(GND), + .ENCLKOS2(GND), + .ENCLKOS3(GND), + .CLKOP(CLKOP), + .CLKOS(CLKOS), + .CLKOS2(CLKOS2), + .CLKOS3(CLKOS3), + .LOCK(LOCK), + .INTLOCK(INTLOCK), + .REFCLK(REFCLK), + .CLKINTFB(CLKINTFB) +); +defparam PLLInst_0.CLKI_DIV = 2; +defparam PLLInst_0.CLKFB_DIV = 1; +defparam PLLInst_0.CLKOP_DIV = 6; +defparam PLLInst_0.CLKOS_DIV = 1; +defparam PLLInst_0.CLKOS2_DIV = 1; +defparam PLLInst_0.CLKOS3_DIV = 1; +defparam PLLInst_0.CLKOP_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS_ENABLE = "ENABLED"; +defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED"; +defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED"; +defparam PLLInst_0.CLKOP_CPHASE = 5; +defparam PLLInst_0.CLKOS_CPHASE = 0; +defparam PLLInst_0.CLKOS2_CPHASE = 0; +defparam PLLInst_0.CLKOS3_CPHASE = 0; +defparam PLLInst_0.CLKOP_FPHASE = 0; +defparam PLLInst_0.CLKOS_FPHASE = 0; +defparam PLLInst_0.CLKOS2_FPHASE = 0; +defparam PLLInst_0.CLKOS3_FPHASE = 0; +defparam PLLInst_0.FEEDBK_PATH = "CLKOP"; +defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOP_TRIM_DELAY = 0; +defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING"; +defparam PLLInst_0.CLKOS_TRIM_DELAY = 0; +defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA"; +defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB"; +defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC"; +defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD"; +defparam PLLInst_0.PLL_LOCK_MODE = 0; +defparam PLLInst_0.STDBY_ENABLE = "DISABLED"; +defparam PLLInst_0.DPHASE_SOURCE = "DISABLED"; +defparam PLLInst_0.PLLRST_ENA = "DISABLED"; +defparam PLLInst_0.INTFB_WAKE = "DISABLED"; +endmodule /* pll_in200_out100 */ + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf new file mode 100644 index 0000000..15716ec --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_synplify.lpf @@ -0,0 +1,20 @@ +# +# Logical Preferences generated for Lattice by Synplify maprc, Build 2453R. +# + +# Period Constraints + + +# Output Constraints + +# Input Constraints + +# Point-to-point Delay Constraints + + + +# Block Path Constraints + +BLOCK ASYNCPATHS; + +# End of generated Logical Preferences. diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt new file mode 100644 index 0000000..97483f5 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt @@ -0,0 +1,67 @@ +#-- Synopsys, Inc. +#-- Version J-2014.09-SP2 +#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt +#-- Written on Tue Mar 17 15:43:11 2015 + + +#project files +add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" +add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc" + + + +#implementation: "syn_results" +impl -add syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_in200_out100" + +# mapper_options +set_option -frequency 100 +set_option -write_verilog 1 +set_option -write_vhdl 1 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -RWCheckOnRam 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./pll_in200_out100.edn" + +#set log file +set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" +impl -active "syn_results" diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs b/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs new file mode 100644 index 0000000..02b31aa --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs @@ -0,0 +1,65 @@ +#-- Synopsys, Inc. +#-- Version J-2014.09-SP2 +#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs + +#project files +add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" +add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc" + + + +#implementation: "syn_results" +impl -add /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 + +#device options +set_option -technology ecp5um +set_option -part LFE5UM_25F +set_option -package MG285C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "pll_in200_out100" + +# mapper_options +set_option -frequency 100 +set_option -write_verilog 1 +set_option -write_vhdl 1 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 50 +set_option -disable_io_insertion 1 +set_option -retiming 0 +set_option -pipe 0 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -RWCheckOnRam 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn" + +#set log file +set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf" +impl -active "syn_results" diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap new file mode 100644 index 0000000..14f4991 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/map.srr.rptmap @@ -0,0 +1 @@ +./synlog/pll_in200_out100_fpga_mapper.srr,map.srr,Map Log diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr new file mode 100644 index 0000000..929e022 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr @@ -0,0 +1,47 @@ +Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +Running on host :depc363 +Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns +@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. +VHDL syntax check successful! +@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box +Post processing for ecp5um.ehxplll.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box +Post processing for ecp5um.vlo.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box +Post processing for ecp5um.vhi.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box +Post processing for ecp5um.ib.syn_black_box +Post processing for work.pll_in200_out100.structure +@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:11 2015 + +###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap new file mode 100644 index 0000000..8315622 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr.rptmap @@ -0,0 +1 @@ +./synlog/pll_in200_out100_compiler.srr,pll_in200_out100_compiler.srr,Compile Log diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr new file mode 100644 index 0000000..600fb8e --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr @@ -0,0 +1,257 @@ +Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ +------------------------------------------------------------ + + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +#### START OF CLOCK OPTIMIZATION REPORT #####[ + +0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + + + +##### END OF CLOCK OPTIMIZATION REPORT ######] + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + +Writing EDIF Netlist and constraint files +J-2014.09-SP2 +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) + +Writing Verilog Simulation files + +Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) + +Writing VHDL Simulation files + +Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Mar 17 15:43:14 2015 +# + + +Top view: pll_in200_out100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 10.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +---------------------------------------------------------------------------------------------------------------- +System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup +================================================================================================================ +@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +--------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +--------------------------------------------------------------------------------------------------------- +System System | 10.000 10.000 | No paths - | No paths - | No paths - +========================================================================================================= + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000 +============================================================================== + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000 +=============================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 10.000 + - Setup time: 0.000 + + Clock delay at ending point: 0.000 (ideal) + + Estimated clock delay at ending point: 0.000 + = Required time: 10.000 + + - Propagation time: 0.000 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (critical) : 10.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKOP + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +--------------------------------------------------------------------------------- +PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 - +CLKOP Net - - - - 2 +PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - +================================================================================= + + + +##### END OF TIMING REPORT #####] + + +Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + + +Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB) + +--------------------------------------- +Resource Usage Report +Part: lfe5um_25f-6 + +Register bits: 0 of 24288 (0%) +PIC Latch: 0 +I/O cells: 1 + + +Details: +EHXPLLL: 1 +GSR: 1 +IB: 1 +PUR: 1 +VHI: 1 +VLO: 1 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:14 2015 + +###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min new file mode 100644 index 0000000..f1b7379 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr_Min @@ -0,0 +1,116 @@ + + +@S |##### START OF TIMING REPORT #####[ +# Timing Report written on Tue Mar 17 15:43:14 2015 +# + + +Top view: pll_in200_out100 +Requested Frequency: 100.0 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc + +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. + +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. + + + +Performance Summary +******************* + + +Worst slack in design: 0.000 + +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +--------------------------------------------------------------------------------------------------------------- +System 100.0 MHz 100.0 MHz 10.000 10.000 0.000 system system_clkgroup +=============================================================================================================== + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +-------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +-------------------------------------------------------------------------------------------------------- +System System | 0.000 0.000 | No paths - | No paths - | No paths - +======================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------- +PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 0.000 +============================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +------------------------------------------------------------------------------ +PLLInst_0 System EHXPLLL CLKFB CLKOP 0.000 0.000 +============================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Propagation time: 0.000 + + Clock delay at starting point: 0.000 (ideal) +-0.000 + - Requested Period: 0.000 + - Hold time: 0.000 + - Clock delay at ending point: 0.000 (ideal) +0.000 + = Slack (critical) : 0.000 + + Number of logic level(s): 0 + Starting point: PLLInst_0 / CLKOP + Ending point: PLLInst_0 / CLKFB + The start point is clocked by System [rising] + The end point is clocked by System [rising] + +Instance / Net Pin Pin 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b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_multi_srs_gen.srr @@ -0,0 +1,9 @@ +Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014 +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:12 2015 + +###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr new file mode 100644 index 0000000..391303f --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr @@ -0,0 +1,49 @@ +Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55 +Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. +Product Version J-2014.09-SP2 + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) + +Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc +@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt +Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100 + +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) + + + +@S |Clock Summary +**************** + +Start Requested Requested Clock Clock +Clock Frequency Period Type Group +----------------------------------------------------------------- +System 100.0 MHz 10.000 system system_clkgroup +================================================================= + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Tue Mar 17 15:43:13 2015 + +###########################################################] diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.szr new file mode 100644 index 0000000000000000000000000000000000000000..bbfc77c192f23862a9f92d136213149bd7ed43da GIT binary patch literal 2174 zcmV-^2!Zz>iwFP!0000017wXo3&JoIMfd)SEZxKxEiO*QkF7|N?x9VeZ6wVLFNvV| zEQHmQWAv~SRM6%hC zcmDWelxJLezYZ@h>hlKx0RR8QS6y!#Hx_-?{EBWl57ojWQkJaDDw{>5%c1E+B;{LJ zeF%zyC>IV$*5iVa+!*=sd&jQ3jk|f-)>{HLI2sP`2hTb8vUW*=Hm^KaqU6jl<;%B> zSJP40T}?tY8t=K0I@;5=<=49eZD(vNg%cVCR%|cv-S>Jg(5OoJTzgSMiOgs(H@<9h zr4X`lC3?}n$5>^PYmJIG$pMeKi(KvVI{}Wp;M=8XRlC>@FEbab)g`x_fdiG9ECPY?6fVN+i+EyFbP^|RrcOq;0y>?kzaCO_;V-%~LmWb<0fy`R@4nK=+ z62iJlsOohiC3^L9!?qb zx%J?aoyb#iv=Sa#xu!2uRJHW*c{~_GRV&bZgAJ&}I~U_V^9<^pUb%N5wv4|}%hn9r?Lu7g%vYByu#9J?02p`N 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:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns +@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100. +@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box +@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box +@N|Running in 64-bit mode + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml new file mode 100644 index 0000000..26e4c2a --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_compiler.srr + Synopsys HDL Compiler + + + Completed + + + + 10 + /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_notes.txt + + + 1 + /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt + + + 0 + /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_errors.txt + + + - + + + 00h:00m:00s + + + - + + + 1426603391 + + + \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt new file mode 100644 index 0000000..46bf347 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_compiler_warnings.txt @@ -0,0 +1,2 @@ +@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ... + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml new file mode 100644 index 0000000..4a0f6ea --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_area_report.xml @@ -0,0 +1,26 @@ + + + + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_resourceusage.rpt +Resource Usage + + +0 + + +1 + + +0 + + +0 + + +0 + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt new file mode 100644 index 0000000..0ac2949 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt @@ -0,0 +1,11 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. +@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack +@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. +@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. +@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml new file mode 100644 index 0000000..bace87f --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_opt_report.xml @@ -0,0 +1,14 @@ + + + + +0 / 0 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_combined_clk.rpt +START OF CLOCK OPTIMIZATION REPORT + + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml new file mode 100644 index 0000000..aa39edd --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr +Synopsys Lattice Technology Mapper + + +Completed + + + +11 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt + + + +1 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt + + + +0 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt + + + +0h:00m:01s + + +0h:00m:01s + + +143MB + + +1426603394 + + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml new file mode 100644 index 0000000..5d08600 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_timing_report.xml @@ -0,0 +1,23 @@ + + + + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr +START OF TIMING REPORT + + +Clock Name +Req Freq +Est Freq +Slack + + +System +100.0 MHz +NA +10.000 + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt new file mode 100644 index 0000000..97bd277 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt @@ -0,0 +1 @@ +@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt new file mode 100644 index 0000000..e69de29 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt new file mode 100644 index 0000000..4081b54 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt @@ -0,0 +1,2 @@ +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml new file mode 100644 index 0000000..2f16611 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_runstatus.xml @@ -0,0 +1,46 @@ + + + + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr +Synopsys Lattice Technology Pre-mapping + + +Completed + + + +2 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_notes.txt + + + +0 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt + + + +0 + +/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt + + + +0h:00m:00s + + +0h:00m:00s + + +140MB + + +1426603393 + + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_warnings.txt new file mode 100644 index 0000000..e69de29 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..0d78634f322a904e7bd0c9466498c0a42777589f GIT binary patch literal 3672 zcmeH}={wX77sr2=$PzQiz6{y-jN4KYF_wtIP-F`kBBt#7AfeD8`@T=sp)7-;LX(KG zMk;%mvP`%|gL&rp8=kk%xjyH6uJhu1o$H)eClzjGdX8O~9RPrH=4QsW^a`dY=UFDY zzNFTs(+e}w@P;7(v}Qz8ZL;Y-#M8|71^^^;13(%*Pw1w20|1DL008n+0MJ_p0HM(! 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    +
+#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
+#install: /opt/synopsys/J-2014.09-SP2
+#OS: Linux 
+#Hostname: depc363
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+Running on host :depc363
+Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N: :  | Running in 64-bit mode 
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : pll_in200_out100.vhd(12) | Top entity is set to pll_in200_out100.
+VHDL syntax check successful!
+@N:CD630 : pll_in200_out100.vhd(12) | Synthesizing work.pll_in200_out100.structure 
+@N:CD630 : ecp5um.vhd(2081) | Synthesizing ecp5um.ehxplll.syn_black_box 
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:CD630 : ecp5um.vhd(830) | Synthesizing ecp5um.vlo.syn_black_box 
+Post processing for ecp5um.vlo.syn_black_box
+@N:CD630 : ecp5um.vhd(823) | Synthesizing ecp5um.vhi.syn_black_box 
+Post processing for ecp5um.vhi.syn_black_box
+@N:CD630 : ecp5um.vhd(998) | Synthesizing ecp5um.ib.syn_black_box 
+Post processing for ecp5um.ib.syn_black_box
+Post processing for work.pll_in200_out100.structure
+@W:CL168 : pll_in200_out100.vhd(55) | Pruning instance scuba_vhi_inst -- not in use ... 
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:11 2015
+
+###########################################################]
+Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
+@N: :  | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:12 2015
+
+###########################################################]
+Pre-mapping Report
+
+Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+Linked File: pll_in200_out100_scck.rpt
+Printing clock  summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file 
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed:	0
+Number of ICG latches not removed:	0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in200_out100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+@S |Clock Summary
+****************
+
+Start      Requested     Requested     Clock      Clock          
+Clock      Frequency     Period        Type       Group          
+-----------------------------------------------------------------
+System     100.0 MHz     10.000        system     system_clkgroup
+=================================================================
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:13 2015
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
+Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+Product Version J-2014.09-SP2
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N:MF248 :  | Running in 64-bit mode. 
+@N:MF666 :  | Clock conversion enabled  
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+------------------------------------------------------------
+
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
+
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+Writing EDIF Netlist and constraint files
+J-2014.09-SP2
+@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+@W:MT246 : pll_in200_out100.vhd(61) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+@S |##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Mar 17 15:43:14 2015
+#
+
+
+Top view:               pll_in200_out100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
+                       
+@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 
+
+@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 
+
+
+
+Performance Summary 
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+@N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+Worst Path Information
+View Worst Path in Analyst
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       1
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+IB:             1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Mar 17 15:43:14 2015
+
+###########################################################]
+
+
    diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm new file mode 100644 index 0000000..8c7cd79 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_toc.htm @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml new file mode 100644 index 0000000..3addc49 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html new file mode 100644 index 0000000..275f5ce --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/syntmp/statusReport.html @@ -0,0 +1,110 @@ + + + Project Status Summary Page + + + + + +
    + + + + + + + + + +
    Project Settings
    Project Name pll_in200_out100 Implementation Name syn_results
    Top Module pll_in200_out100 Pipelining 0
    Retiming 0 Resource Sharing 1
    Fanout Guide 50 Disable I/O Insertion 1
    Clock Conversion 1 FSM Compiler 1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete1010-00m:00s-17.03.2015
    15:43
    (premap)Complete2000m:00s0m:00s140MB17.03.2015
    15:43
    (fpga_mapper)Complete11100m:01s0m:01s143MB17.03.2015
    15:43
    Multi-srs GeneratorComplete00m:00s17.03.2015
    15:43
    +
    + + + + + + + + + + + + + + + + +
    Area Summary
    Register bits 0I/O cells 1
    Block RAMs +(v_ram) 0DSPs +(dsp_used) 0
    ORCA LUTs +(total_luts) 0

    + + + + + + + + +
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    System100.0 MHzNA10.000
    +
    + + + + + + +
    Optimizations Summary
    Combined Clock Conversion 0 / 0

    +
    +
    + \ No newline at end of file diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/.cckTransfer new file mode 100644 index 0000000000000000000000000000000000000000..c567c7ca4781deab32d9d8ac15506d0889f3f084 GIT binary patch literal 39 pcmb2|=3oE==Ah8fPz{Y!`kuaejTcvHe$1R{xiW@t9Z2&3e*nIR3?l#l literal 0 HcmV?d00001 diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info new file mode 100644 index 0000000..37bc105 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/_mh_info @@ -0,0 +1 @@ +|1| diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep new file mode 100644 index 0000000..524f434 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdep @@ -0,0 +1,28 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427 +#CUR:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":1426603391 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":1416503391 +0 "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work pll_in200_out100 structure 0 +module work pll_in200_out100 0 + + +# Configuration files used diff --git a/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig new file mode 100644 index 0000000..ff57353 --- /dev/null +++ b/lattice/ecp5/PLL/pll_in200_out100/syn_results/synwork/layer0.fdeporig @@ -0,0 +1,24 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-layerid|0|-top|pll_in200_out100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"/opt/synopsys/J-2014.09-SP2/linux_a_64/c_vhdl":1416524537 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/location.map":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd":1416524427 +#CUR:"/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd":1416524427 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