From f56fd311ef15d9762f2f9626b8cd3c0d65624699 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 2 Dec 2021 08:12:43 +0100 Subject: [PATCH] still link problems --- cts/trb3sc_cts.vhd | 64 ++++- tdctemplate/config.vhd | 1 + tdctemplate/config_16_sfp_kel.vhd | 157 ++++++++++++ tdctemplate/config_compile_gsi.pl | 19 +- tdctemplate/nodes_tdctemplate.txt | 1 - tdctemplate/tdc_release | 1 + tdctemplate/trb3sc_tdctemplate.prj | 20 +- tdctemplate/trb3sc_tdctemplate.vhd | 393 +++++++++++++++++------------ 8 files changed, 463 insertions(+), 193 deletions(-) create mode 120000 tdctemplate/config.vhd create mode 100644 tdctemplate/config_16_sfp_kel.vhd delete mode 120000 tdctemplate/nodes_tdctemplate.txt create mode 120000 tdctemplate/tdc_release diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 7469369..3cd6906 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -242,6 +242,13 @@ architecture trb3sc_arch of trb3sc_cts is begin +THE_TIME_COUNTER_PROC: process( clk_full_osc ) +begin + if( rising_edge(clk_full_osc) ) then + time_counter <= time_counter + 1; + end if; +end process THE_TIME_COUNTER_PROC; + --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- @@ -382,17 +389,52 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate end process THE_SYNC_PROC; --HDR_IO(10 downto 1) <= (others => '0'); - HDR_IO(10) <= clear_i; --debug_i(4); - HDR_IO(9) <= reset_i; --debug_i(3); - HDR_IO(8) <= debug_i(2); - HDR_IO(7) <= debug_i(1); - HDR_IO(6) <= debug_i(0); - HDR_IO(5) <= tx_pll_lol_qd_b_i; - HDR_IO(4) <= link_tx_ready_i; - HDR_IO(3) <= sync_tx_quad_i; - HDR_IO(2) <= tx_pcs_rst_ch_c_i; - HDR_IO(1) <= rst_qd_c_i; + HDR_IO(10) <= '0'; + HDR_IO(9) <= '0'; + HDR_IO(8) <= '0'; + HDR_IO(7) <= '0'; + HDR_IO(6) <= '0'; + HDR_IO(5) <= '0'; + HDR_IO(4) <= '0'; + HDR_IO(3) <= '0'; + HDR_IO(2) <= rx_dlm_i; + HDR_IO(1) <= tx_dlm_i; + TEST_LINE(0) <= debug_i(16); + TEST_LINE(1) <= debug_i(17); + TEST_LINE(2) <= debug_i(18); + TEST_LINE(3) <= debug_i(19); + TEST_LINE(4) <= debug_i(20); + TEST_LINE(5) <= debug_i(5); + TEST_LINE(6) <= debug_i(6); + TEST_LINE(7) <= debug_i(7); + TEST_LINE(8) <= debug_i(8); + TEST_LINE(9) <= debug_i(21); + TEST_LINE(10) <= debug_i(10); + TEST_LINE(11) <= debug_i(11); + TEST_LINE(12) <= tx_pll_lol_qd_b_i; + TEST_LINE(13) <= rst_qd_c_i; + TEST_LINE(14) <= tx_pcs_rst_ch_c_i; + TEST_LINE(15) <= sync_tx_quad_i; + +-- DEBUG_OUT(5) <= send_steady_idle_int; +-- DEBUG_OUT(4) <= toggle_idle; +-- DEBUG_OUT(3 downto 0) <= state_bits; + +-- DEBUG_OUT(0) <= SFP_LOS_IN; +-- DEBUG_OUT(1) <= RX_LOS_IN; +-- DEBUG_OUT(2) <= RX_CDR_LOL_IN; +-- DEBUG_OUT(3) <= rx_pcs_rst_i; +-- DEBUG_OUT(4) <= rx_serdes_rst_i; +-- DEBUG_OUT(5) <= link_rx_ready_i; +-- DEBUG_OUT(6) <= link_half_done_i; +-- DEBUG_OUT(7) <= link_full_done_i; +-- DEBUG_OUT(8) <= LINK_TX_READY_IN; +-- DEBUG_OUT(9) <= is_wap_zero_i; +-- DEBUG_OUT(10) <= reset_rx_fsm_i; +-- DEBUG_OUT(11) <= reset_i; +-- DEBUG_OUT(15 downto 12) <= rx_fsm_state; + destroy_link_i <= common_ctrl_reg(88); end generate; @@ -1000,7 +1042,7 @@ end generate; end generate; RJ_IO(0) <= cts_trigger_out; - + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd new file mode 120000 index 0000000..1bdb29d --- /dev/null +++ b/tdctemplate/config.vhd @@ -0,0 +1 @@ +config_16_sfp_kel.vhd \ No newline at end of file diff --git a/tdctemplate/config_16_sfp_kel.vhd b/tdctemplate/config_16_sfp_kel.vhd new file mode 100644 index 0000000..06a4626 --- /dev/null +++ b/tdctemplate/config_16_sfp_kel.vhd @@ -0,0 +1,157 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + + constant USE_RETRANSMISSION : integer := c_NO; + + --pinout to be used - don't forget to change config_compile.pl as well + -- 0: 32 Pin AddOn + -- 1: 4conn AddOn + -- 2: 2x KEL on board + -- 3: ADA AddOn (plus test on KEL) + -- 4: every fourth channel on ADA + + constant PINOUT : integer := 2; + +--TDC settings + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 17; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 1000; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_CALIBRATION_200MHZ : integer := c_NO; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CF"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"72"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 3; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + +--input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 36; + +--trigger generation only on 'fast' channels from Padiwa + constant TRIG_GEN_FAST_CHANNELS : integer := c_NO; + + constant USE_GBE : integer := c_NO; + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"85",x"0a", + x"86",x"0a", + x"87",x"0a", + others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500B000"; --Change depening on pinout + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(6 downto 0) := std_logic_vector(to_unsigned(PINOUT,7)); + t(7) := '1'; + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(28 downto 28) := std_logic_vector(to_unsigned(3-SERDES_NUM,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/tdctemplate/config_compile_gsi.pl b/tdctemplate/config_compile_gsi.pl index f874c48..7ef1463 100644 --- a/tdctemplate/config_compile_gsi.pl +++ b/tdctemplate/config_compile_gsi.pl @@ -1,15 +1,18 @@ TOPNAME => "trb3sc_tdctemplate", -lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/opt/lattice/diamond/3.6_x64/', -#synplify_path => '/opt/synplicity/J-2014.09-SP2', -synplify_path => '/opt/synplicity/K-2015.09', -#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", -synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", - -nodelist_file => 'nodes_gsi_template.txt', +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/R-2020.09-SP1', +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier", +nodelist_file => 'nodelist.txt', +pinout_file => 'trb3sc_padiwa', +par_options => '../par.p2t', + include_TDC => 1, +include_GBE => 0, firefox_open => 0, twr_number_of_errors => 20, +no_ltxt2ptxt => 0, #if there is no serdes being used + diff --git a/tdctemplate/nodes_tdctemplate.txt b/tdctemplate/nodes_tdctemplate.txt deleted file mode 120000 index ac11978..0000000 --- a/tdctemplate/nodes_tdctemplate.txt +++ /dev/null @@ -1 +0,0 @@ -../scripts/nodes_tdctemplate.txt \ No newline at end of file diff --git a/tdctemplate/tdc_release b/tdctemplate/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/tdctemplate/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 5b88f31..e737c79 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -181,16 +181,16 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" #Media interface -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 79fc1b5..2379684 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -12,81 +12,65 @@ use work.tdc_components.all; use work.trb_net16_hub_func.all; use work.version.all; use work.trb_net_gbe_components.all; -use work.med_sync_define.all; +use work.med_sync_define_RS.all; entity trb3sc_tdctemplate is port( - CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE - CLK_CORE_PCLK : in std_logic; --Main Oscillator - CLK_EXT_PLL_LEFT : in std_logic; --External Clock - - - TRIG_LEFT : in std_logic; --Trigger Input - - --Backplane, all lines --- BACK_GPIO : inout std_logic_vector(15 downto 0); --- BACK_LVDS : inout std_logic_vector(1 downto 0); --- BACK_3V3 : inout std_logic_vector(3 downto 0); + CLK_SUPPL_PCLK : in std_logic; -- 125 MHz for GbE + CLK_CORE_PCLK : in std_logic; -- Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; -- External Clock + TRIG_LEFT : in std_logic; -- Trigger Input --Backplane for slaves on trbv3scbp1 BACK_GPIO : inout std_logic_vector(3 downto 0); - --AddOn Connector - 32 Pin AddOn - INP : in std_logic_vector(95 downto 0); - DAC_OUT_SDO : out std_logic_vector(6 downto 1); - DAC_OUT_SCK : out std_logic_vector(6 downto 1); - DAC_OUT_CS : out std_logic_vector(6 downto 1); - DAC_IN_SDI : in std_logic_vector(6 downto 1); - - TEST_SIG_OUT : out std_logic_vector(7 downto 0); - FEETEMP : inout std_logic_vector(3 downto 0); - + INP : in std_logic_vector(95 downto 0); + DAC_OUT_SDO : out std_logic_vector(6 downto 1); + DAC_OUT_SCK : out std_logic_vector(6 downto 1); + DAC_OUT_CS : out std_logic_vector(6 downto 1); + DAC_IN_SDI : in std_logic_vector(6 downto 1); + TEST_SIG_OUT : out std_logic_vector(7 downto 0); + FEETEMP : inout std_logic_vector(3 downto 0); --Additional IO - HDR_IO : inout std_logic_vector(10 downto 1); - RJ_IO : inout std_logic_vector(3 downto 0); + HDR_IO : inout std_logic_vector(10 downto 1); + RJ_IO : inout std_logic_vector(3 downto 0); -- SPARE_IN : in std_logic_vector(1 downto 0); - --LED - LED_GREEN : out std_logic; - LED_YELLOW : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_RJ_GREEN : out std_logic_vector(1 downto 0); - LED_RJ_RED : out std_logic_vector(1 downto 0); - LED_WHITE : out std_logic_vector(1 downto 0); - LED_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_SFP_RED : out std_logic_vector(1 downto 0); - + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_WHITE : out std_logic_vector(1 downto 0); + LED_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_SFP_RED : out std_logic_vector(1 downto 0); --SFP - SFP_LOS : in std_logic_vector(1 downto 0); - SFP_MOD0 : in std_logic_vector(1 downto 0); - SFP_MOD1 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - SFP_MOD2 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - SFP_TX_DIS : out std_logic_vector(1 downto 0) := (others => '0'); - + SFP_LOS : in std_logic_vector(1 downto 0); + SFP_MOD0 : in std_logic_vector(1 downto 0); + SFP_MOD1 : inout std_logic_vector(1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector(1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector(1 downto 0) := (others => '0'); --Serdes switch - PCSSW_ENSMB : out std_logic; - PCSSW_EQ : out std_logic_vector(3 downto 0); - PCSSW_PE : out std_logic_vector(3 downto 0); - PCSSW : out std_logic_vector(7 downto 0); - + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector(3 downto 0); + PCSSW_PE : out std_logic_vector(3 downto 0); + PCSSW : out std_logic_vector(7 downto 0); --ADC - ADC_CLK : out std_logic; - ADC_CS : out std_logic; - ADC_DIN : out std_logic; - ADC_DOUT : in std_logic; - + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; --Flash, 1-wire, Reload - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_IN : out std_logic; - FLASH_OUT : in std_logic; - PROGRAMN : out std_logic; - ENPIRION_CLOCK : out std_logic; - TEMPSENS : inout std_logic; - + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); + TEST_LINE : out std_logic_vector(15 downto 0) -- Flex connector + ); attribute syn_useioff : boolean; @@ -100,18 +84,20 @@ entity trb3sc_tdctemplate is --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- --SFP D0,B3(D1) D0: GbE, B3: TrbNet - - + end entity; architecture trb3sc_arch of trb3sc_tdctemplate is attribute syn_keep : boolean; attribute syn_preserve : boolean; - signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal clear_i : std_logic; + signal clk_sys : std_logic; + signal clk_full : std_logic; + signal clk_full_osc : std_logic; + signal clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); @@ -121,33 +107,35 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); --READOUT - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx, bus_master_out, busfee_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx, bus_master_in, busfee_tx : CTRLBUS_TX; - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal sed_error_i : std_logic; + signal sed_error_i : std_logic; signal bus_master_active : std_logic; - signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal spi_cs : std_logic_vector(15 downto 0); + signal spi_mosi : std_logic_vector(15 downto 0); + signal spi_miso : std_logic_vector(15 downto 0); + signal spi_clk : std_logic_vector(15 downto 0); - signal timer : TIMERS; - signal lcd_data : std_logic_vector(511 downto 0); - signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal trig_gen_out_i : std_logic_vector(3 downto 0); - signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; --TDC - signal hit_in_i : std_logic_vector(64 downto 1); - signal logic_analyser_i : std_logic_vector(15 downto 0); + signal hit_in_i : std_logic_vector(64 downto 1); + signal logic_analyser_i : std_logic_vector(15 downto 0); attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -158,6 +146,21 @@ architecture trb3sc_arch of trb3sc_tdctemplate is attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; + signal tx_pll_lol_qd_b_i : std_logic; + signal rst_qd_c_i : std_logic; + signal tx_pcs_rst_ch_c_i : std_logic; + signal sync_tx_quad_i : std_logic; + signal link_tx_ready_i : std_logic; + signal tx_reset_i : std_logic; + signal tx_clock_avail_i : std_logic; + signal debug_i : std_logic_vector(31 downto 0); + signal rx_dlm_i : std_logic; + signal word_sync_i : std_logic; + signal master_clk_i : std_logic; + + signal tx_reset_state : std_logic_vector(3 downto 0); + signal master_reset_i : std_logic; + begin --------------------------------------------------------------------------- @@ -171,91 +174,170 @@ begin NET_CLK_HALF_IN => med2int(0).clk_half, RESET_FROM_NET => med2int(0).stat_op(13), SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, - FULL_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - REF_CLK_OUT => clk_full_osc, + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, - ENPIRION_CLOCK => ENPIRION_CLOCK, - LED_RED_OUT => LED_RJ_RED, - LED_GREEN_OUT => LED_RJ_GREEN, - DEBUG_OUT => debug_clock_reset - ); + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); -gen_cal125 : if USE_CALIBRATION_200MHZ = c_NO generate +gen_cal125 : if (USE_CALIBRATION_200MHZ = c_NO) generate pll_calibration : entity work.pll_in125_out33 port map ( CLK => CLK_SUPPL_PCLK, CLKOP => clk_cal, - LOCK => open); + LOCK => open + ); end generate; -gen_cal200 : if USE_CALIBRATION_200MHZ = c_YES generate +gen_cal200 : if (USE_CALIBRATION_200MHZ = c_YES) generate pll_calibration : entity work.pll_in200_out33 port map ( CLK => CLK_SUPPL_PCLK, CLKOP => clk_cal, - LOCK => open); + LOCK => open + ); end generate; --- GSR_N <= reset_i; - + --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- - THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS generic map( - SERDES_NUM => SERDES_NUM, - IS_SYNC_SLAVE => c_YES - ) + SIM_MODE => 0, + IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE), + IS_WAP_ZERO => 1 + ) port map( - CLK_REF_FULL => med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - + -- Clocks and reset + CLK_REF_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => master_reset_i, --reset_i, + CLEAR => master_reset_i, --clear_i, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => open, + MEDIA_MED2INT(1) => open, + MEDIA_MED2INT(2) => open, + MEDIA_MED2INT(3) => med2int(0), + MEDIA_INT2MED(0) => open, + MEDIA_INT2MED(1) => open, + MEDIA_INT2MED(2) => open, + MEDIA_INT2MED(3) => int2med(0), + -- Sync operation + RX_DLM_OUT(0) => open, + RX_DLM_OUT(1) => open, + RX_DLM_OUT(2) => open, + RX_DLM_OUT(3) => rx_dlm_i, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, -- DLM komma ping + TX_DLM_WORD_IN => x"aa", + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", + WORD_SYNC_IN => word_sync_i, -- downlink synced to uplink + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, -- downlink uses upling clock + MASTER_CLK_OUT => master_clk_i, + MASTER_RESET_OUT => master_reset_i, --open, + DESTROY_LINK_IN(0) => '0', + DESTROY_LINK_IN(1) => '0', + DESTROY_LINK_IN(2) => '0', + DESTROY_LINK_IN(3) => '0', + LINK_TX_READY_IN => link_tx_ready_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, + TX_RESET_OUT => tx_reset_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + RST_QUAD_IN => rst_qd_c_i, + RST_TX_PCS_IN => tx_pcs_rst_ch_c_i, --SFP Connection - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, + SD_PRSNT_N_IN(0) => '1', + SD_LOS_IN(0) => '1', + SD_TXDIS_OUT(0) => open, + SD_PRSNT_N_IN(1) => '1', + SD_LOS_IN(1) => '1', + SD_TXDIS_OUT(1) => open, + SD_PRSNT_N_IN(2) => '1', + SD_LOS_IN(2) => '1', + SD_TXDIS_OUT(2) => open, + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + SD_LOS_IN(3) => SFP_LOS(1), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open - ); + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => debug_i + ); SFP_TX_DIS(0) <= '0' when USE_GBE = 1 else '1'; + + tx_clock_avail_i <= not tx_reset_i; -- change ports! - gen_sfp_con : if SERDES_NUM = 3 generate - sfp_los_i <= SFP_LOS(1); - sfp_prsnt_i <= SFP_MOD0(1); - SFP_TX_DIS(1) <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; + THE_MAIN_TX_RESET: main_tx_reset_RS + generic map( + SIM_MODE => 0 + ) + port map( + CLEAR => clear_i, + LOCALCLK => clk_full_osc, + TX_PLL_LOL_QD_A_IN => '0', + TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, + TX_PLL_LOL_QD_C_IN => '0', + TX_PLL_LOL_QD_D_IN => '0', + TX_CLOCK_AVAIL_IN => tx_clock_avail_i, -- for testing... + RST_QD_C_OUT => rst_qd_c_i, + TX_PCS_RST_CH_C_OUT => tx_pcs_rst_ch_c_i, + SYNC_TX_QUAD_OUT => sync_tx_quad_i, + LINK_TX_READY_OUT => link_tx_ready_i, + STATE_OUT => tx_reset_state --open + ); + + --HDR_IO(10 downto 1) <= (others => '0'); + HDR_IO(10) <= master_reset_i; + HDR_IO(9) <= clear_i; + HDR_IO(8) <= tx_pll_lol_qd_b_i; + HDR_IO(7) <= tx_clock_avail_i; + HDR_IO(6) <= rst_qd_c_i; + HDR_IO(5) <= tx_pcs_rst_ch_c_i; + HDR_IO(4) <= tx_reset_state(3); --sync_tx_quad_i; + HDR_IO(3) <= tx_reset_state(2); --'0'; + HDR_IO(2) <= tx_reset_state(1); --rx_dlm_i; + HDR_IO(1) <= tx_reset_state(0); --'0'; + + TEST_LINE <= debug_i(15 downto 0); +-- TEST_LINE(0) <= tx_pll_lol_qd_b_i; +-- TEST_LINE(1) <= rst_qd_c_i; +-- TEST_LINE(2) <= tx_pcs_rst_ch_c_i; +-- TEST_LINE(3) <= sync_tx_quad_i; +-- TEST_LINE(4) <= link_tx_ready_i; +-- TEST_LINE(5) <= debug_i(4); -- rx_los +-- TEST_LINE(6) <= debug_i(3); -- rx_cdr_lol +-- TEST_LINE(7) <= debug_i(0); -- link_rx_ready +-- TEST_LINE(8) <= debug_i(1); -- link_half_done +-- TEST_LINE(9) <= debug_i(2); -- link_full_done +-- TEST_LINE(10) <= tx_reset_i; +-- TEST_LINE(11) <= debug_i(5); -- SFP_LOS_IN +-- TEST_LINE(12) <= '0'; +-- TEST_LINE(13) <= '0'; +-- TEST_LINE(14) <= '0'; +-- TEST_LINE(15) <= '0'; + --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- @@ -278,21 +360,19 @@ end generate; port map( -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_EN => '1', - CLK_125 => CLK_SUPPL_PCLK, - CLEAR_N => GSR_N, + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + CLK_125 => CLK_SUPPL_PCLK, + CLEAR_N => GSR_N, -- Media direction port MEDIA_MED2INT => med2int(0), MEDIA_INT2MED => int2med(0), - --Timing trigger in TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - + -- Readout + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, --Slow Control Port REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 @@ -361,7 +441,7 @@ end generate; SPI_MISO_IN => spi_miso, SPI_CLK_OUT => spi_clk, --Header - HEADER_IO => HDR_IO, + HEADER_IO => open, --HDR_IO, ADDITIONAL_REG => open, --LCD LCD_DATA_IN => lcd_data, @@ -386,8 +466,6 @@ end generate; DEBUG_OUT => open ); - - --------------------------------------------------------------------------- -- Switches --------------------------------------------------------------------------- @@ -522,17 +600,6 @@ end generate; end if; end process; - ---TEST_LINE <= med2int(0).dataready & int2med(0).dataready & med2int(0).data(6 downto 0) & int2med(0).data(6 downto 0); --- TEST_LINE <= med_stat_debug(15 downto 0); - TEST_LINE(0) <= med2int(0).stat_op(13); - TEST_LINE(1) <= med2int(0).stat_op(15); - TEST_LINE(2) <= clear_i; - TEST_LINE(3) <= reset_i; - TEST_LINE(4) <= time_counter(26); - TEST_LINE(5) <= BACK_GPIO(1); - TEST_LINE(6) <= sfp_txdis_i; - TEST_LINE(7) <= med2int(0).stat_op(9); ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- -- 2.43.0