From f61e19fe2549925f1264cb024e7bba2acf58043b Mon Sep 17 00:00:00 2001
From: Ingo Froehlich <ingo@nomail.fake>
Date: Thu, 25 Jan 2018 16:02:59 +0100
Subject: [PATCH] async ram, IF

---
 machxo3/flash/generic_flash_ctrl.vhd | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 70b8627..3e8a27f 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -46,7 +46,8 @@ entity generic_flash_ctrl is
            DATA_BUS_WIDTH   : integer := 16
            );
   port(
-    CLK   : in  std_logic;
+    CLK_l : in  std_logic; --local clock
+    CLK_f : in  std_logic; --flash clock
     RESET : in  std_logic;
 
     -- SPI/UART in host direction
@@ -152,8 +153,8 @@ begin
       DataInB   => flashram_data_i,
       AddressA  => ram_addr_i,
       AddressB  => flashram_addr_i,
-      ClockA    => CLK,
-      ClockB    => CLK,
+      ClockA    => CLK_l,
+      ClockB    => CLK_f,
       ClockEnA  => '1',
       ClockEnB  => flashram_cen_i,
       WrA       => ram_write_i,
@@ -166,7 +167,7 @@ begin
 
   THE_FLASH : UFM_WB
     port map(
-      clk_i     => CLK,
+      clk_i     => CLK_f,
       rst_n     => not RESET,
       cmd       => flash_command,
       ufm_page  => flash_page,
@@ -191,7 +192,7 @@ begin
   LOC_BUSY_OUT  <= SPI_BUSY_IN;
   
 PROC_SELECTOR : process begin
-  wait until rising_edge(CLK);
+  wait until rising_edge(clk_l);
 
   reg_LOC_DATA_OUT  <= SPI_DATA_IN;
   reg_LOC_ADDR_OUT  <= SPI_ADDR_IN;
@@ -202,14 +203,19 @@ PROC_SELECTOR : process begin
     reg_SPI_READY_OUT <= LOC_READY_IN;
   end if;
   
-  
   ram_write_i <= '0';
   ram_data_i <= x"00";
-  if (burst_counter = "0000") then
+  if (burst_counter = "0000" and out_delay = "000") then
     spi_ram_addr_i <= x"0";
+  else
+    spi_ram_addr_i <= spi_ram_addr_i;
   end if;
-  spi_flash_go <= '0';
 
+  if (flash_busy = '1') then
+    spi_flash_go <= '0';
+  end if;
+  
+    
   if (clean_master_start_reg = '1') then
     master_start_reg <= '0';
   end if;
@@ -367,9 +373,9 @@ flash_go <= master_flash_go when master_running = '1' else spi_flash_go;
 flash_page <= master_flash_page when master_running = '1' else spi_flash_page;
 flash_command <= master_flash_command when master_running = '1' else spi_flash_command;
 
-state_machine :  process (CLK)
+state_machine :  process (clk_f)
 begin
-  if rising_edge(CLK) then
+  if rising_edge(clk_f) then
     master_flash_go  <= '0';
     master_WRITE_OUT <= '0';
     clean_master_start_reg <= '0';
-- 
2.43.0