From f683c3756c086d9ae5f8cf05f9565598e3ccbcb0 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 7 Jul 2014 17:29:54 +0200 Subject: [PATCH] ADC: More nxyter like CLK usage...not tested yet --- ADC/trb3_periph_adc.vhd | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index d7c48cb..a1d3b8a 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -225,7 +225,7 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) @@ -241,7 +241,8 @@ begin --------------------------------------------------------------------------- THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_GPLL_RIGHT, + CLK => CLK_PCLK_RIGHT, + RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock @@ -262,7 +263,7 @@ begin USE_CTC => c_NO ) port map( - CLK => clk_200_i, + CLK => CLK_PCLK_RIGHT, SYSCLK => clk_100_i, RESET => reset_i, CLEAR => clear_i, -- 2.43.0