From f6b3ffabfb561486fe5540d0827dbfaf4e106ea3 Mon Sep 17 00:00:00 2001 From: Hadaq in Frankfurt Date: Wed, 20 Mar 2013 20:47:54 +0100 Subject: [PATCH] added testbench with sensor simulation. hopefully fixed READ_ERROR issue on STAT outputs (jtag_tdo_compare_counttotal_noram_m10.vhd). bn --- soft/toolbox/jtag_atomic/chains.ini.chain0 | 1 + .../jtag_atomic/jtagmonitor_lastcounters.ini | 34 +- .../jtag_atomic/jtagmonitor_usechainsini4.pl | 10 +- vhdl/.gitignore | 9 + vhdl/code/jtag_cmd_m26c.vhd | 10 +- ...ag_mux_buffer_tms_tdi_out_and_metainfo.vhd | 12 +- .../jtag_tdo_compare_counttotal_noram_m10.vhd | 261 ++--- ...jtag_cmd_m26c_test_regvaluesfrominput2.vhd | 1039 +++++++++++++++++ ...cmd_m26c_test_regvaluesfrominput2_test.vhd | 77 ++ vhdl/code/tb/jtag_simulation_constants.vhd | 11 + vhdl/code/tb/jtag_tap_mi26_hard.vhd | 492 ++++++++ vhdl/sim/sim_jtag_cmd_m26c.prj.mpf | 128 +- 12 files changed, 1865 insertions(+), 219 deletions(-) create mode 100644 vhdl/.gitignore create mode 100644 vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd create mode 100644 vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd create mode 100644 vhdl/code/tb/jtag_simulation_constants.vhd create mode 100644 vhdl/code/tb/jtag_tap_mi26_hard.vhd diff --git a/soft/toolbox/jtag_atomic/chains.ini.chain0 b/soft/toolbox/jtag_atomic/chains.ini.chain0 index e5fa19a..02012c8 100644 --- a/soft/toolbox/jtag_atomic/chains.ini.chain0 +++ b/soft/toolbox/jtag_atomic/chains.ini.chain0 @@ -3,6 +3,7 @@ RAMtrbnetAddr=0xa000 CMDreg_trbnetAddr=0xa120 RAMbase_trbnetAddr=0xa121 DATAreg_trbnetAddr=0xa122 +STAT_NIBBLEStrbnetAddr=0x008d STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa163 STATUS2RAM3BtrbnetAddr=0xa170 CONFsignals_trbnetAddr=0xb020 diff --git a/soft/toolbox/jtag_atomic/jtagmonitor_lastcounters.ini b/soft/toolbox/jtag_atomic/jtagmonitor_lastcounters.ini index 2b7fc73..8ff8f94 100644 --- a/soft/toolbox/jtag_atomic/jtagmonitor_lastcounters.ini +++ b/soft/toolbox/jtag_atomic/jtagmonitor_lastcounters.ini @@ -1,17 +1,17 @@ -[chain1] -JNR3_sensor1_rerrors=1 -JNR3_sensor1_werrors=1 -JNR3_sensor1_run=6 -JNR3_sensor1_datach=1 -JNR2_sensor2_rerrors=1 -JNR2_sensor2_werrors=1 -JNR2_sensor2_run=6 -JNR2_sensor2_datach=1 -JNR1_sensor3_rerrors=1 -JNR1_sensor3_werrors=1 -JNR1_sensor3_run=6 -JNR1_sensor3_datach=1 -JNR0_sensor4_rerrors=1 -JNR0_sensor4_werrors=1 -JNR0_sensor4_run=6 -JNR0_sensor4_datach=1 +[newchain1] +JNR3_sensor5_rerrors=12 +JNR3_sensor5_werrors=12 +JNR3_sensor5_run=4 +JNR3_sensor5_datach=6 +JNR2_sensor6_rerrors=12 +JNR2_sensor6_werrors=12 +JNR2_sensor6_run=4 +JNR2_sensor6_datach=6 +JNR1_sensor7_rerrors=12 +JNR1_sensor7_werrors=12 +JNR1_sensor7_run=4 +JNR1_sensor7_datach=6 +JNR0_sensor8_rerrors=12 +JNR0_sensor8_werrors=12 +JNR0_sensor8_run=4 +JNR0_sensor8_datach=6 diff --git a/soft/toolbox/jtag_atomic/jtagmonitor_usechainsini4.pl b/soft/toolbox/jtag_atomic/jtagmonitor_usechainsini4.pl index 3da19d5..25acf8c 100755 --- a/soft/toolbox/jtag_atomic/jtagmonitor_usechainsini4.pl +++ b/soft/toolbox/jtag_atomic/jtagmonitor_usechainsini4.pl @@ -82,6 +82,14 @@ while (1){ my $cmd_reg_addr = hex(substr($settings{'CMDreg_trbnetAddr'},2)); my $status2_ram3b_baseaddr_reg_addr = hex(substr($settings{'STATUS2RAM3BBASEADDRREGtrbnetAddr'},2)); my $status2_ram3b_addr = hex(substr($settings{'STATUS2RAM3BtrbnetAddr'},2)); + my $stat_nibbles_addr = hex(substr($settings{'STAT_NIBBLEStrbnetAddr'},2)); + # get status of last run: + my $nibbles = trb_register_read(($fpga_addr), ($stat_nibbles_addr)); + my $k=0, $v=0; + ($k, $v) = each %$nibbles; + my $last_run_successful = '(Last Run OK: '. substr(sprintf("%X", $v), 6, 1) . ')'; + + my @sensors; my @vert_list1; my @vert_list2; @@ -209,7 +217,7 @@ while (1){ elsif($botherrors == 1) { syslog("WARNING", "Only WRITE_ERROR and READ_ERROR $chain between runs $minlastruncounter and $maxruncounter. Power off?"); } - $status_str .= Hmon::MakeTitle(8,5,$chain,1); + $status_str .= Hmon::MakeTitle(8,5,$chain . $last_run_successful,1); my @table = [\@status_table_row1,\@status_table_row2]; $status_str .= colored_table(@table) . "
"; #print $status_str; diff --git a/vhdl/.gitignore b/vhdl/.gitignore new file mode 100644 index 0000000..6d8af6e --- /dev/null +++ b/vhdl/.gitignore @@ -0,0 +1,9 @@ +code/*.swp +code/*.bak +code/tb/*.bak +code/transcript +sim/sim_jtag_cmd_m26c.prj.cr.mti +sim/transcript +sim/vsim.wlf +sim/work/ + diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd index 716af7f..46bf572 100644 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ b/vhdl/code/jtag_cmd_m26c.vhd @@ -242,7 +242,7 @@ component jtag_mux_buffer_tms_tdi_out_and_metainfo is RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); RD_ENABLE_JTAG_CLOCK_IN : in std_logic; RD_LAST_TCK_CYCLE_IN : in std_logic; - RD_EXPECTED_TDO_OUT : in std_logic; + RD_EXPECTED_TDO_IN : in std_logic; -- write registers inputs WR_TMS_IN : in std_logic; @@ -254,7 +254,7 @@ component jtag_mux_buffer_tms_tdi_out_and_metainfo is WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0); WR_ENABLE_JTAG_CLOCK_IN : in std_logic; WR_LAST_TCK_CYCLE_IN : in std_logic; - WR_EXPECTED_TDO_OUT : in std_logic; + WR_EXPECTED_TDO_IN : in std_logic; -- test chain inputs TC_TMS_IN : in std_logic; @@ -1924,7 +1924,7 @@ the_jtag_mux_buffer_tms_tdi_out_and_metainfo : jtag_mux_buffer_tms_tdi_out_and_m RD_CHIPNUM_IN => jtag_read_chipnum, RD_ENABLE_JTAG_CLOCK_IN => jtag_read_enable_jtag_clock, RD_LAST_TCK_CYCLE_IN => jtag_read_last_tck_cycle, - RD_EXPECTED_TDO_OUT => jtag_read_expected_tdo, + RD_EXPECTED_TDO_IN => jtag_read_expected_tdo, -- write registers inputs WR_TMS_IN => jtag_write_tms, WR_TDI_IN => jtag_write_tdi, @@ -1935,7 +1935,7 @@ the_jtag_mux_buffer_tms_tdi_out_and_metainfo : jtag_mux_buffer_tms_tdi_out_and_m WR_REGNUM_IN => jtag_write_regnum, WR_ENABLE_JTAG_CLOCK_IN => jtag_write_enable_jtag_clock, WR_LAST_TCK_CYCLE_IN => jtag_write_last_tck_cycle, - WR_EXPECTED_TDO_OUT => jtag_write_expected_tdo, + WR_EXPECTED_TDO_IN => jtag_write_expected_tdo, -- test chain inputs TC_TMS_IN => jtag_bypassreg_tms, TC_TDI_IN => jtag_bypassreg_tdi, @@ -2778,7 +2778,7 @@ begin else ram1b_select_next <= '0'; end if; - ram2_select_next <= '0'; -- tdo_compare_count + ram2_select_next <= '0'; -- tdo_compare_count m26cs_state_next <= M26CSS_WRITE1_BEGIN; end if; when M26CSS_WRITE1_BEGIN => diff --git a/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd b/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd index cc12b49..273917c 100755 --- a/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd +++ b/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd @@ -33,7 +33,7 @@ entity jtag_mux_buffer_tms_tdi_out_and_metainfo is RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); RD_ENABLE_JTAG_CLOCK_IN : in std_logic; RD_LAST_TCK_CYCLE_IN : in std_logic; - RD_EXPECTED_TDO_OUT : in std_logic; + RD_EXPECTED_TDO_IN : in std_logic; -- write registers inputs WR_TMS_IN : in std_logic; @@ -45,7 +45,7 @@ entity jtag_mux_buffer_tms_tdi_out_and_metainfo is WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0); WR_ENABLE_JTAG_CLOCK_IN : in std_logic; WR_LAST_TCK_CYCLE_IN : in std_logic; - WR_EXPECTED_TDO_OUT : in std_logic; + WR_EXPECTED_TDO_IN : in std_logic; -- test chain inputs TC_TMS_IN : in std_logic; @@ -122,7 +122,7 @@ begin end if; end process; -COMB_MAIN: process(JTAG_SET_DATA_IN, RD_ENABLE_JTAG_CLOCK_IN, WR_ENABLE_JTAG_CLOCK_IN, TC_ENABLE_JTAG_CLOCK_IN, RD_TMS_IN, RD_TDI_IN, RD_IS_DR_BIT_IN, RD_IS_FIRSTBIT_IN, RD_IS_LASTBIT_IN, RD_CHIPNUM_IN, RD_LAST_TCK_CYCLE_IN, RD_EXPECTED_TDO_OUT, WR_TMS_IN, WR_TDI_IN, WR_IS_DR_BIT_IN, WR_IS_FIRSTBIT_IN, WR_IS_LASTBIT_IN, WR_CHIPNUM_IN, WR_REGNUM_IN, WR_LAST_TCK_CYCLE_IN, WR_EXPECTED_TDO_OUT, TC_TMS_IN, TC_TDI_IN, TC_LAST_TCK_CYCLE_IN, tdi, tms,is_dr_bit,is_firstbit,is_lastbit,chipnum,regnum,enable_jtag_clock,last_tck_cycle,expected_tdo) -- INSERTLABEL: sensitivity list +COMB_MAIN: process(JTAG_SET_DATA_IN, RD_ENABLE_JTAG_CLOCK_IN, WR_ENABLE_JTAG_CLOCK_IN, TC_ENABLE_JTAG_CLOCK_IN, RD_TMS_IN, RD_TDI_IN, RD_IS_DR_BIT_IN, RD_IS_FIRSTBIT_IN, RD_IS_LASTBIT_IN, RD_CHIPNUM_IN, RD_LAST_TCK_CYCLE_IN, RD_EXPECTED_TDO_IN, WR_TMS_IN, WR_TDI_IN, WR_IS_DR_BIT_IN, WR_IS_FIRSTBIT_IN, WR_IS_LASTBIT_IN, WR_CHIPNUM_IN, WR_REGNUM_IN, WR_LAST_TCK_CYCLE_IN, WR_EXPECTED_TDO_IN, TC_TMS_IN, TC_TDI_IN, TC_LAST_TCK_CYCLE_IN, tdi, tms,is_dr_bit,is_firstbit,is_lastbit,chipnum,regnum,enable_jtag_clock,last_tck_cycle,expected_tdo) -- INSERTLABEL: sensitivity list begin tms_next <= tms; tdi_next <= tdi; @@ -147,7 +147,7 @@ begin regnum_next <= (others => '0'); enable_jtag_clock_next <= RD_ENABLE_JTAG_CLOCK_IN; last_tck_cycle_next <= RD_LAST_TCK_CYCLE_IN; - expected_tdo_next <= RD_EXPECTED_TDO_OUT; + expected_tdo_next <= RD_EXPECTED_TDO_IN; elsif(WR_ENABLE_JTAG_CLOCK_IN = '1') then tms_next <= WR_TMS_IN; tdi_next <= WR_TDI_IN; @@ -159,7 +159,7 @@ begin regnum_next <= unsigned(WR_REGNUM_IN) + 1; enable_jtag_clock_next <= WR_ENABLE_JTAG_CLOCK_IN; last_tck_cycle_next <= WR_LAST_TCK_CYCLE_IN; - expected_tdo_next <= WR_EXPECTED_TDO_OUT; + expected_tdo_next <= WR_EXPECTED_TDO_IN; elsif(TC_ENABLE_JTAG_CLOCK_IN = '1') then tms_next <= TC_TMS_IN; tdi_next <= TC_TDI_IN; @@ -185,4 +185,4 @@ begin end if; end if; end process; -end architecture; \ No newline at end of file +end architecture; diff --git a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd b/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd index 4926bc1..5107718 100644 --- a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd +++ b/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd @@ -1,130 +1,131 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - --- counts for one register of one chip: --- sampling errors : those cases in which not all sampled values are equal. --- matches : sampled value = expected value --- differences : sampled value /= expected value --- --- the following equation should hold: --- matches+differences = register size --- RAM2: stores for each register --- MCOUNT = number of bits for which the sampled value --- matches the expected value --- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value --- does not match the expected value --- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value --- (not all sampled values equal) --- this should of course be 0 --- - - -entity jtag_tdo_compare_counttotal_noram_m10 is - generic ( - numcounts : integer := 3; - se_counter_width : integer := 32; -- sampling error counter width - diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc) - -- sample_pulse3 delayed by one clock cycle - SAMPLE_PULSE3_D1_IN : in std_logic; - -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?) - ENABLE_COUNTERS_IN : in std_logic; - - TDO_EXPECTED_IN : in std_logic; - TDO_SAMPLED_IN : in std_logic; - TDO_SAMPLING_ERROR_IN : in std_logic; - BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); - END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); - - -- should be zero if timing is good - SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0); - COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0); - LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0) - - ); -end entity; - -architecture jtag_tdo_compare_counttotal_noram_m10_arch of jtag_tdo_compare_counttotal_noram_m10 is - --- state machine for main controlling state machine for TDO sampling: - signal count_i_errors_occured : std_logic_vector(numcounts-1 downto 0); - --signal count_i_lookingforerrors : std_logic_vector(numcounts-1 downto 0); - - signal sampling_error_count : unsigned(se_counter_width-1 downto 0); - - signal counts : unsigned(numcounts*diff_counter_width-1 downto 0); - signal SAMPLE_PULSE3_D2 : std_logic; -begin -COUNTS_OUT <= std_logic_vector(counts); -SAMPLING_ERRORS_COUNT_OUT <= std_logic_vector(sampling_error_count); -LAST_VALUES_OUT <= count_i_errors_occured; - -ALL_PROC : process (CLK_IN) -variable i : integer; -begin - if (rising_edge(CLK_IN)) then - for i in 0 to numcounts-1 loop - if(ENABLE_COUNTERS_IN = '1') then - if(SAMPLE_PULSE3_D2 = '1') then -- when this pulse arrives, the tdo-input from the last chip has been sampled - if(not(TDO_SAMPLED_IN = TDO_EXPECTED_IN)) then - --if(count_i_lookingforerrors(i) = '1') then - -- remember that an error has occured since begin signal - count_i_errors_occured(i) <= '1'; - --end if; - end if; - end if; - end if; - - if(BEGIN_COUNT_I_IN(i) = '1') then - -- reset states if begin signal received - --count_i_lookingforerrors(i) <= '1'; - count_i_errors_occured(i) <= '0'; - end if; - if(END_COUNT_I_IN(i) = '1') then - -- on end signal update counter - if(count_i_errors_occured(i) = '1') then - -- increment count - counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) + 1; - end if; - end if; - end loop; - if(RESET_IN = '1') then - count_i_errors_occured <= (others => '0'); - --count_i_lookingforerrors <= (others => '0'); - counts <= (others => '0'); - end if; - end if; -end process; - -SAMPLING_ERRORS : process (CLK_IN) -variable i : integer; -begin - if (rising_edge(CLK_IN)) then - if(SAMPLE_PULSE3_D2 = '1') then - if(TDO_SAMPLING_ERROR_IN = '1') then - sampling_error_count <= sampling_error_count + 1; - end if; - end if; - -- delayed pulse - SAMPLE_PULSE3_D2 <= SAMPLE_PULSE3_D1_IN; - if(RESET_IN = '1') then - sampling_error_count <= (others => '0'); - end if; - end if; - -end process; - - -end architecture; +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +-- use work.trb_net16_hub_func.all; +--use work.version.all; +use work.jtag_constants.all; + +-- counts for one register of one chip: +-- sampling errors : those cases in which not all sampled values are equal. +-- matches : sampled value = expected value +-- differences : sampled value /= expected value +-- +-- the following equation should hold: +-- matches+differences = register size +-- RAM2: stores for each register +-- MCOUNT = number of bits for which the sampled value +-- matches the expected value +-- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value +-- does not match the expected value +-- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value +-- (not all sampled values equal) +-- this should of course be 0 +-- + + +entity jtag_tdo_compare_counttotal_noram_m10 is + generic ( + numcounts : integer := 3; + se_counter_width : integer := 32; -- sampling error counter width + diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc) + -- sample_pulse3 delayed by one clock cycle + SAMPLE_PULSE3_D1_IN : in std_logic; + -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?) + ENABLE_COUNTERS_IN : in std_logic; + + TDO_EXPECTED_IN : in std_logic; + TDO_SAMPLED_IN : in std_logic; + TDO_SAMPLING_ERROR_IN : in std_logic; + BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); + END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); + + -- should be zero if timing is good + SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0); + COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0); + LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0) + + ); +end entity; + +architecture jtag_tdo_compare_counttotal_noram_m10_arch of jtag_tdo_compare_counttotal_noram_m10 is + +-- state machine for main controlling state machine for TDO sampling: + signal count_i_errors_occured : std_logic_vector(numcounts-1 downto 0); + signal count_i_lookingforerrors : std_logic_vector(numcounts-1 downto 0); + + signal sampling_error_count : unsigned(se_counter_width-1 downto 0); + + signal counts : unsigned(numcounts*diff_counter_width-1 downto 0); + signal SAMPLE_PULSE3_D2 : std_logic; +begin +COUNTS_OUT <= std_logic_vector(counts); +SAMPLING_ERRORS_COUNT_OUT <= std_logic_vector(sampling_error_count); +LAST_VALUES_OUT <= count_i_errors_occured; + +ALL_PROC : process (CLK_IN) +variable i : integer; +begin + if (rising_edge(CLK_IN)) then + for i in 0 to numcounts-1 loop + if(ENABLE_COUNTERS_IN = '1') then + if(SAMPLE_PULSE3_D2 = '1') then -- when this pulse arrives, the tdo-input from the last chip has been sampled + if(not(TDO_SAMPLED_IN = TDO_EXPECTED_IN)) then + if(count_i_lookingforerrors(i) = '1') then + -- remember that an error has occured since begin signal + count_i_errors_occured(i) <= '1'; + end if; + end if; + end if; + end if; + + if(BEGIN_COUNT_I_IN(i) = '1') then + -- reset states if begin signal received + count_i_lookingforerrors(i) <= '1'; + count_i_errors_occured(i) <= '0'; + end if; + if(END_COUNT_I_IN(i) = '1') then + -- on end signal update counter + count_i_lookingforerrors(i) <= '0'; -- stop looking for errors + if(count_i_errors_occured(i) = '1') then + -- increment count + counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) + 1; + end if; + end if; + end loop; + if(RESET_IN = '1') then + count_i_errors_occured <= (others => '0'); + --count_i_lookingforerrors <= (others => '0'); + counts <= (others => '0'); + end if; + end if; +end process; + +SAMPLING_ERRORS : process (CLK_IN) +variable i : integer; +begin + if (rising_edge(CLK_IN)) then + if(SAMPLE_PULSE3_D2 = '1') then + if(TDO_SAMPLING_ERROR_IN = '1') then + sampling_error_count <= sampling_error_count + 1; + end if; + end if; + -- delayed pulse + SAMPLE_PULSE3_D2 <= SAMPLE_PULSE3_D1_IN; + if(RESET_IN = '1') then + sampling_error_count <= (others => '0'); + end if; + end if; + +end process; + + +end architecture; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd new file mode 100644 index 0000000..fd4ba37 --- /dev/null +++ b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd @@ -0,0 +1,1039 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +--USE IEEE.std_logic_ARITH.ALL; +--USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.numeric_std.ALL; +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +-- use work.trb_net16_hub_func.all; +--use work.version.all; +use work.jtag_constants.all; +use work.jtag_simulation_constants.all; + +-- use TAP MI26 HARD +entity jtag_cmd_m26c_test_regvaluesfrominput2 is +generic( + numregs : integer := 11; + maxreglen : integer := 1152; + -- instruction_codes : instrArray := (0 => "10000", 1 => "10001", 2 => "10010", others => (others => '1')); -- in the given order these are the instruction codes of the registers to be programmed by the JTAG-Chain-Controller + --drlen : drlenArray := (0 => 32, 1=> 8, 2=> 1024, others => 32); -- length of the registers (same order as instruction_codes) + instruction_codes : instrArray := (0 => "01111", --BIAS_GEN + 1 => "10000", --LINE0_PATTERN_REG + 2 => "10001", --DIS_DISCRI + 3 => "10010", --SEQ_PIX_REG + 4 => "10011", --CTRL_PIX_REG + 5 => "10100", --LINE1_PATTERN_REG + 6 => "10101", --SEQ_SUZE_REG + 7 => "10110", --HEADER_TRAILER_REG + 8 => "10111", --CTRL_SUZE_REG + 9 => "11101", --RO_MODE1 + 10 => "11110", --RO_MODE0 + others => (others => '1')); + drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, others => 0); + + numchips : integer := 3 +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + REGISTERS_IN : in std_logic_vector(numchips*numregs*maxreglen-1 downto 0); + TRIGGER_IN : in std_logic + ); +end entity; + + +architecture arch of jtag_cmd_m26c_test_regvaluesfrominput2 is +component CRC_32 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + CRC_OUT : out std_logic_vector(31 downto 0); + CRC_match : out std_logic + ); +end component; +-- +component jtag_cmd_m26c is + generic( + MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.) + MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. + MAX_REGLEN : integer := 4095; -- naximum register length. + + WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED. + + READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set + + JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips + JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26 + JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send. + + RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit. +-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; -- + JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width + JTAG_TDO_EXPECTED_MAXDELAY : integer := 3 -- set range to 0..value for delay of expected TDO value +); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + JTAG_TMS_OUT : out std_logic; + JTAG_TCK_OUT : out std_logic; + JTAG_TDI_OUT : out std_logic; + JTAG_TDO_IN : in std_logic; + + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_ADDR_IN : in std_logic_vector(8 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + + BUS_DATAREADY_OUT : out std_logic; + BUS_NO_MORE_DATA_OUT : out std_logic; + BUS_WRITE_ACK_OUT : out std_logic; + BUS_UNKNOWN_ADDR_OUT : out std_logic; + + RUN_REQUEST_IN : in std_logic; + WRITE_ONCE_REQUEST_IN : in std_logic; + MY_STATUS_OUT : out std_logic_vector(8 downto 0); + --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); + --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); + IDLE_OUT : out std_logic; + PROG_JTAG_FINISHED_OUT:out std_logic; + READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); + WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); + DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); + SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); + RUN_COUNTER_OUT : out std_logic_vector(31 downto 0); + + STARTED_OUT : out std_logic; + LAST_RUN_SUCCESSFUL_OUT : out std_logic; + LAST_DATA_CHANGED_OUT : out std_logic; + LAST_WRITE_ERRORS_OUT : out std_logic; + LAST_READ_ERRORS_OUT : out std_logic; + CRC_ERROR_OUT : out std_logic + + --BUS_TIMEOUT_IN : in std_logic; + ); +end component; +--component jtag_cmd_m26c is +-- port( +-- CLK_IN : in std_logic; +-- RESET_IN : in std_logic; +-- +-- JTAG_TMS_OUT : out std_logic; +-- JTAG_TCK_OUT : out std_logic; +-- JTAG_TDI_OUT : out std_logic; +-- JTAG_TDO_IN : in std_logic; +-- +-- BUS_DATA_IN : in std_logic_vector(31 downto 0); +-- BUS_DATA_OUT : out std_logic_vector(31 downto 0); +-- BUS_ADDR_IN : in std_logic_vector(8 downto 0); +-- BUS_READ_IN : in std_logic; +-- BUS_WRITE_IN : in std_logic; +-- BUS_DATAREADY_OUT : out std_logic; +-- BUS_NO_MORE_DATA_OUT : out std_logic; +-- BUS_WRITE_ACK_OUT : out std_logic; +-- BUS_UNKNOWN_ADDR_OUT : out std_logic; +-- OFF_SPILL_IN : in std_logic; +-- MY_STATUS_OUT : out std_logic_vector(8 downto 0); +-- --MON_FIFO_DATA_OUT : out std_logic_vector(511 downto 0); +-- --MON_FIFO_WRITE_OUT : out std_logic_vector(15 downto 0); +-- +-- IDLE_OUT : out std_logic; +-- PROG_JTAG_FINISHED_OUT:out std_logic +-- ); +--end component; +component jtag_tap_mi26_hard is +port( + TCK_EMU: in std_logic; + TMS_EMU: in std_logic; + TDI_EMU: in std_logic; + TDO_EMU: out std_logic; + TRSTB_EMU: in std_logic; + + REGISTERS_OUT: out std_logic_vector(12*maxreglen-1 downto 0) + ); +end component; + +--signal clk_in, reset_in : std_logic; +--signal REGISTERS_IN : std_logic_vector(numchips*numregs*maxreglen-1 downto 0); +constant numchips_ld : integer := 2; + +signal jtag_tms_out, jtag_tck_out, jtag_tdi_out, jtag_tdo_in, trstb : std_logic; +signal bus_data_in : std_logic_vector(31 downto 0); +signal bus_data_out : std_logic_vector(31 downto 0); +signal bus_addr_in : std_logic_vector(15 downto 0); +signal bus_read_in : std_logic; +signal bus_write_in : std_logic; +signal bus_dataready_out : std_logic; +signal bus_no_more_data_out : std_logic; +signal bus_write_ack_out : std_logic; +signal bus_unknown_addr_out : std_logic; +signal trigger_jtag_write : std_logic; +signal prog_jtag_finished_out : std_logic; +signal idle_out : std_logic; +constant RAM_JTAG_REGISTERS_DEPTH : integer := 11; + +signal phase : unsigned(11 downto 0); +signal chip : unsigned(numchips_ld-1 downto 0); +signal ramcounter : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); +signal regpointer : std_logic_vector(7 downto 0); +signal regu : unsigned(3 downto 0); +signal wordu : unsigned(7 downto 0); +signal statuscounter : std_logic_vector(4 downto 0); +signal crc32_1_clk_en : std_logic; +signal crc32_reset_in : std_logic; +signal crc32_1_data_in : std_logic_vector(31 downto 0); +signal crc32_1_crc_out : std_logic_vector(31 downto 0); +signal a,b : std_logic_vector(3 downto 0); +signal ergebnis : std_logic_vector(7 downto 0); +signal jtag1_out : std_logic; +signal jtag2_out : std_logic; +signal jtag3_in : std_logic; +signal broken : std_logic; +type REG_ARRAY is array (numregs-1 downto 0) of std_logic_vector(maxreglen-1 downto 0); +type SENSORREGS is array (numchips-1 downto 0) of REG_ARRAY; +signal sensor_registers : SENSORREGS; + +type TAP_REGISTERS_ARRAY is array (numchips-1 downto 0) of std_logic_vector(12*maxreglen-1 downto 0); +signal tap_registers : TAP_REGISTERS_ARRAY; +signal registers_match : std_logic; -- contains result of asynchronous check, if registers input to the JTAG-Chain-Controller match + -- the output registers of the simulated MIMOSA-26 sensors +signal crc32_match_out : std_logic; +--signal data_in, ready_for_cmd_out, data_out, data_arrived_out : std_logic; +begin +crc32_1: CRC_32 port map( + CLK => clk_in, + RESET => crc32_reset_in, + CLK_EN => crc32_1_clk_en, + DATA_IN => crc32_1_data_in, + CRC_OUT => crc32_1_crc_out, + CRC_match => crc32_match_out + ); +jtag_test1 : jtag_cmd_m26c port map( CLK_IN => clk_in, + RESET_IN => reset_in, + JTAG_TMS_OUT => jtag_tms_out, + JTAG_TCK_OUT => jtag_tck_out, + JTAG_TDI_OUT => jtag_tdi_out, + JTAG_TDO_IN => jtag_tdo_in, + BUS_DATA_IN => bus_data_in, + BUS_DATA_OUT => bus_data_out, + BUS_ADDR_IN => bus_addr_in(8 downto 0), + BUS_READ_IN => bus_read_in, + BUS_WRITE_IN => bus_write_in, + BUS_DATAREADY_OUT => bus_dataready_out, + BUS_NO_MORE_DATA_OUT => bus_no_more_data_out, + BUS_WRITE_ACK_OUT => bus_write_ack_out, + BUS_UNKNOWN_ADDR_OUT => bus_unknown_addr_out, + RUN_REQUEST_IN => trigger_jtag_write, + WRITE_ONCE_REQUEST_IN => '0', + IDLE_OUT => idle_out, + PROG_JTAG_FINISHED_OUT => prog_jtag_finished_out +); +tap1: jtag_tap_mi26_hard +-- default_ir => "01110" -- ID_CODE +port map (TCK_EMU => jtag_tck_out, + TMS_EMU => jtag_tms_out, + TDI_EMU => jtag_tdi_out, + TDO_EMU => jtag1_out, + TRSTB_EMU => trstb, + REGISTERS_OUT => tap_registers(2) +); +tap2: jtag_tap_mi26_hard +port map (TCK_EMU => jtag_tck_out, + TMS_EMU => jtag_tms_out, + TDI_EMU => jtag1_out, + TDO_EMU => jtag2_out, + TRSTB_EMU => trstb, + REGISTERS_OUT => tap_registers(1) +); +tap3: jtag_tap_mi26_hard +port map (TCK_EMU => jtag_tck_out, + TMS_EMU => jtag_tms_out, + TDI_EMU => jtag2_out, + TDO_EMU => jtag_tdo_in, + TRSTB_EMU => trstb, + REGISTERS_OUT => tap_registers(0) +); +--top1 : top port map( TCK_EMU => jtag_tck_out, +-- TMS_EMU => jtag_tms_out, +-- TDI_EMU => jtag_tdi_out, +-- TDO_EMU => jtag1_out, +-- TRSTB_EMU => trstb +--); +--top2 : top port map( TCK_EMU => jtag_tck_out, +-- TMS_EMU => jtag_tms_out, +-- TDI_EMU => jtag1_out, +-- TDO_EMU => jtag2_out, +-- TRSTB_EMU => trstb +--); +--top3 : top port map( TCK_EMU => jtag_tck_out, +-- TMS_EMU => jtag_tms_out, +-- TDI_EMU => jtag3_in, +-- TDO_EMU => jtag_tdo_in, +-- TRSTB_EMU => trstb +--); +-- psl EVENTUALLY_REGISTERS_MATCH: assert (eventually! registers_match = '1') @(rising_edge(CLK_IN)); +-- psl EVENTUALLY_REGISTERS_MATCH_AND_FINISHED: assert (eventually! (registers_match = '1' and prog_jtag_finished_out = '1')) @(rising_edge(CLK_IN)); + +jtag3_in <= jtag2_out when broken = '0' else '0'; +-- sensor_registers +SENSOR_REGISTERS_FROM_INPUT : process(REGISTERS_IN) +begin + SENSORLOOP: for si in 0 to numchips-1 loop + REGLOOP: for regi in 0 to numregs-1 loop + sensor_registers(si)(regi) <= REGISTERS_IN(si*maxreglen*numregs+(regi+1)*maxreglen-1 downto si*maxreglen*numregs+regi*maxreglen); + end loop; + end loop; +end process; + +compare_registers : process(sensor_registers, tap_registers) +variable deviation : std_logic; +begin + deviation := '0'; + SENSORLOOP: for si in 0 to numchips-1 loop + REGLOOP: for regi in 0 to numregs-1 loop + -- for bits in 0 to drlen(regi)-1 + if(sensor_registers(si)(regi)(drlen(regi)-1 downto 0) /= tap_registers(si)(regi*maxreglen+drlen(regi)-1 downto regi*maxreglen)) then + deviation := '1'; + else + -- this is purposefully wrong to test verification + -- deviation := '1'; + end if; + end loop; + end loop; + registers_match <= not deviation; + --wait for 100ns; +end process; + + +stimulus_statemachine : process (CLK_IN) +begin + if(rising_edge(CLK_IN)) then + phase <= phase + 1; + case phase is + when x"000" => + if( not(TRIGGER_IN = '1')) then + phase <= phase; + + end if; + when x"001" => + trstb <= '1'; + + when x"002" => + trstb <= '0'; + + when x"003" => + chip <= (others => '0'); + when x"004" => + --CHIPLOOP: for i in 0 to numchips-1 loop + if (not(chip < numchips)) then + phase <= x"005"; + else + phase <= x"100"; -- chiploop + end if; + when x"100" => + ramcounter <= (others => '0'); + bus_data_in(31 downto numchips_ld) <= (others => '0'); + bus_data_in(numchips_ld - 1 downto 0) <= std_logic_vector(chip); -- select ram1a window + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_RAM_BASEADDR; + when x"101" => + bus_write_in <= '1'; + when x"102" => + crc32_reset_in <= '1'; + when x"103" => + crc32_reset_in <= '0'; + when x"104" => + bus_write_in <= '0'; + when x"105" => + when x"106" => + when x"107" => + when x"108" => + bus_data_in(31 downto 0) <= x"0005" & std_logic_vector(to_unsigned(numregs,16)); -- line 1: numregs (lower 16 bits) and irlen (higher 16 bits) + crc32_1_data_in <= x"0005" & std_logic_vector(to_unsigned(numregs,16)); + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"109" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"10A" => + crc32_1_clk_en <= '0'; + when x"10B" => + when x"10C" => + bus_write_in <= '0'; + when x"10D" => + when x"10E" => + when x"10F" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + when x"110" => + bus_data_in(31 downto 0) <= x"4D323601"; -- line 2 + crc32_1_data_in <= x"4D323601"; + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"111" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"112" => + crc32_1_clk_en <= '0'; + when x"113" => + when x"114" => + bus_write_in <= '0'; + when x"115" => + when x"116" => + when x"117" => + --wait until rising_edge(bus_write_ack_out); + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + -- header pointer+len CRC IRs + -- there are 2 + 2*numregs +1 +(numregs+1) + -- = 3*numregs+4 + -- words in front of the DRs section + regpointer <= std_logic_vector(to_unsigned(3*numregs+4, 8)); -- max 8kbit with 32 bit words ==> 8 address bits + regu <= (others => '0'); + when x"118" => + --REGLOOP1: for regi in 0 to numregs-1 loop + if (not (regu < numregs)) then + phase <= x"119"; + else + phase <= x"200"; -- REGLOOP1 + end if; + when x"200" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= regpointer; -- pointer + crc32_1_data_in(31 downto 8) <= (others => '0'); + crc32_1_data_in(7 downto 0) <= regpointer; + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"201" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"202" => + crc32_1_clk_en <= '0'; + when x"203" => + when x"204" => + bus_write_in <= '0'; + when x"205" => + when x"206" => + when x"207" => + --wait until rising_edge(bus_write_ack_out); + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + regpointer <= std_logic_vector(unsigned(regpointer) + (drlen(to_integer(regu))+31)/32); + when x"208" => + bus_data_in(31 downto 0) <= std_logic_vector(to_unsigned(drlen(to_integer(regu)),32)); -- length + crc32_1_data_in <= std_logic_vector(to_unsigned(drlen(to_integer(regu)),32)); + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"209" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"20A" => + crc32_1_clk_en <= '0'; + when x"20B" => + when x"20C" => + bus_write_in <= '0'; + when x"20D" => + when x"20E" => + when x"20F" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + regu <= regu + 1; + phase <= x"118"; + --end loop; + + when x"119" => + bus_data_in(31 downto 0) <= crc32_1_crc_out; -- CRC x"51ED658E"; -- line 25 + crc32_1_data_in <= crc32_1_crc_out; + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"11A" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"11B" => + crc32_1_clk_en <= '0'; + when x"11C" => + when x"11D" => + bus_write_in <= '0'; + when x"11E" => + when x"11F" => + when x"120" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + regu <= (others => '0'); + when x"121" => + -- REGLOOP2: for regi in 0 to numregs-1 loop + if (not (regu < numregs)) then + phase <= x"122"; + else + phase <= x"300"; -- REGLOOP2 + end if; + when x"300" => + bus_data_in(31 downto IRLEN) <= (others => '0'); + bus_data_in(IRLEN-1 downto 0) <= instruction_codes(to_integer(regu)); -- IR regi + crc32_1_data_in(31 downto IRLEN) <= (others => '0'); + crc32_1_data_in(IRLEN-1 downto 0) <= instruction_codes(to_integer(regu)); + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"301" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"302" => + crc32_1_clk_en <= '0'; + when x"303" => + when x"304" => + bus_write_in <= '0'; + when x"305" => + when x"306" => + when x"307" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + when x"308" => + -- REGLOOP2: for regi in 0 to numregs-1 loop + --end loop; + regu <= regu + 1; + phase <= x"121"; + when x"122" => + -- Bypass Register IR + bus_data_in(31 downto 0) <= x"0000001F"; -- line 37 + crc32_1_data_in <= x"0000001F"; + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"123" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"124" => + crc32_1_clk_en <= '0'; + when x"125" => + when x"126" => + bus_write_in <= '0'; + when x"127" => + when x"128" => + when x"129" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + regu <= (others => '0'); + when x"12A" => + when x"12B" => + -- REGLOOP3: for regi in 0 to numregs-1 loop + if (not (regu < numregs)) then + phase <= x"12C"; + else + phase <= x"400"; -- REGLOOP3 + wordu <= (others => '0'); + end if; + when x"400" => + -- WORDLOOP: for wi in 0 to (drlen(regi)-1)/32 loop + if (not (wordu < (drlen(to_integer(regu))-1)/32+1)) then + phase <= x"401"; + else + phase <= x"500"; -- WORDLOOP + end if; + when x"500" => + -- data registers + -- loop over words + bus_data_in(31 downto 0) <= sensor_registers(to_integer(chip))(to_integer(regu))(32*(to_integer(wordu)+1)-1 downto 32*to_integer(wordu)); -- DR regi, word wi, sensor i + crc32_1_data_in(31 downto 0) <= sensor_registers(to_integer(chip))(to_integer(regu))(32*(to_integer(wordu)+1)-1 downto 32*to_integer(wordu)); + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"501" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"502" => + crc32_1_clk_en <= '0'; + when x"503" => + when x"504" => + bus_write_in <= '0'; + when x"505" => + when x"506" => + when x"507" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + when x"508" => + when x"509" => + --end loop; + wordu <= wordu + 1; + phase <= x"400"; + when x"401" => + --end loop; + regu <= regu + 1; + phase <= x"12B"; + when x"12C" => + -- write CRC + bus_data_in(31 downto 0) <= crc32_1_crc_out; + crc32_1_data_in <= crc32_1_crc_out; + bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); + bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); + when x"12D" => + bus_write_in <= '1'; + crc32_1_clk_en <= '1'; --wait for 15 ns; + when x"12E" => + crc32_1_clk_en <= '0'; + when x"12F" => + when x"130" => + bus_write_in <= '0'; + when x"131" => + when x"132" => + when x"133" => + ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); + when x"134" => + when x"135" => + chip <= chip + 1; + phase <= x"004"; + -- end loop; + + + when x"005" => + when x"006" => + -- continue: CHIPSLOOP done + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(numchips,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"007" => + bus_write_in <= '1'; + when x"008" => + when x"009" => + when x"00A" => + bus_write_in <= '0'; + when x"00B" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_NUMCHIPS_CONFIGURED; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"00C" => + bus_write_in <= '1'; + when x"00D" => + when x"00E" => + when x"00F" => + bus_write_in <= '0'; + when x"010" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(10,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"011" => + bus_write_in <= '1'; + when x"012" => + when x"013" => + when x"014" => + bus_write_in <= '0'; + --when x"014" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"015" => + bus_write_in <= '1'; + when x"016" => + when x"017" => + when x"018" => + bus_write_in <= '0'; + when x"019" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER; + when x"01A" => + bus_write_in <= '1'; + when x"01B" => + when x"01C" => + when x"01D" => + bus_write_in <= '0'; + when x"01E" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME1; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"01F" => + bus_write_in <= '1'; + when x"020" => + when x"021" => + when x"022" => + bus_write_in <= '0'; + when x"023" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(0,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"024" => + bus_write_in <= '1'; + when x"025" => + when x"026" => + when x"027" => + bus_write_in <= '0'; + when x"028" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME2; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"029" => + bus_write_in <= '1'; + when x"02A" => + when x"02B" => + when x"02C" => + bus_write_in <= '0'; + when x"02D" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"02E" => + bus_write_in <= '1'; + when x"02F" => + when x"030" => + when x"031" => + bus_write_in <= '0'; + when x"032" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME1; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"033" => + bus_write_in <= '1'; + when x"034" => + when x"035" => + when x"036" => + bus_write_in <= '0'; + when x"037" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(6,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"038" => + bus_write_in <= '1'; + when x"039" => + when x"03A" => + when x"03B" => + bus_write_in <= '0'; + when x"03C" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME2; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"03D" => + bus_write_in <= '1'; + when x"03E" => + when x"03F" => + when x"040" => + bus_write_in <= '0'; + when x"041" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(7,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"042" => + bus_write_in <= '1'; + when x"043" => + when x"044" => + when x"045" => + bus_write_in <= '0'; + when x"046" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME3; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"047" => + bus_write_in <= '1'; + when x"048" => + when x"049" => + when x"04A" => + bus_write_in <= '0'; + when x"04B" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(9,8)); + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; + when x"04C" => + bus_write_in <= '1'; + when x"04D" => + when x"04E" => + when x"04F" => + bus_write_in <= '0'; + phase <= x"05A"; + when x"05A" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SET_DATA_TIME; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"05B" => + bus_write_in <= '1'; + when x"05C" => + when x"05D" => + when x"05E" => + bus_write_in <= '0'; + when x"05F" => + + +-- -- REMOVE sensor 2 (last sensor in chain from end) +-- wait for 100 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= x"02"; -- select sensor +-- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); +-- bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_write_in <= '1'; +-- wait for 30 ns; +-- bus_write_in <= '0'; +-- +-- wait for 100 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= M26C_CMD_REMOVE_SENSOR; +-- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); +-- bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_write_in <= '1'; +-- wait for 30 ns; +-- bus_write_in <= '0'; + + when x"060" => + bus_data_in(31 downto 8) <= (others => '0'); + bus_data_in(7 downto 0) <= M26C_CMD_START; + bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); + bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; + when x"061" => + bus_write_in <= '1'; + when x"062" => + when x"063" => + when x"064" => + bus_write_in <= '0'; + when x"065" => + +-- wait until jtag_tck_out = '1'; +-- wait until jtag_tck_out = '0'; +-- --jtag_tdo_in <= '1'; +-- wait until jtag_tck_out = '1'; +-- wait until jtag_tck_out = '0'; +-- --jtag_tdo_in <= '0'; + when x"066" => + if not (idle_out = '1') then + phase <= phase; -- wait + end if; + when x"067" => + trigger_jtag_write <= '1'; + when x"068" => + if not (idle_out = '0') then + phase <= phase; -- wait + end if; + when x"069" => + trigger_jtag_write <= '0'; + when x"06A" => + phase <= phase; -- end + when others => + phase <= x"000"; + end case; + if(RESET_IN = '1') then + broken <= '0'; + bus_addr_in(15 downto 0) <= x"0000"; + bus_data_in(31 downto 8) <= x"000000"; + bus_data_in(7 downto 0) <= M26C_CMD_NONE; + bus_write_in <= '0'; + bus_read_in <= '0'; + trigger_jtag_write <= '0'; + ramcounter <= (others => '0'); + statuscounter <= (others => '0'); + crc32_1_data_in <= x"00000000"; + crc32_1_clk_en <= '0'; + trstb <= '1'; + crc32_reset_in <= '1'; + phase <= x"000"; + chip <= (others => '0'); + regu <= (others => '0'); + wordu <= (others => '0'); + regpointer <= (others => '0'); + + end if; + end if; +end process; + +-- GET_STATUS: process +-- begin +-- wait for 500*8 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= M26C_CMD_COPY_TO_STATUS2; +-- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); +-- bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_write_in <= '1'; +-- wait for 30 ns; +-- bus_write_in <= '0'; +-- +-- wait for 500*8 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= (others => '0'); +-- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); +-- bus_addr_in(4 downto 0) <= ADDR_STATUS2_UPDATING; +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_write_in <= '1'; +-- wait for 30 ns; +-- bus_write_in <= '0'; +-- +-- wait for 500*8 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= (others => '0'); -- set baseaddr to 0 +-- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); +-- bus_addr_in(4 downto 0) <= ADDR_STATUS2_RAM3B_BASEADDR; +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_write_in <= '1'; +-- wait for 30 ns; +-- bus_write_in <= '0'; +-- +-- -- read status2 ram (error counters etc...) +-- STATUS2LOOP: for i in 0 to 15 loop +-- wait for 500*8 ns; +-- bus_data_in(31 downto 8) <= (others => '0'); +-- bus_data_in(7 downto 0) <= (others => '0'); +-- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); +-- bus_addr_in(4 downto 0) <= std_logic_vector(unsigned(ADDR_STATUS2_RAM3B_BEGIN) + to_unsigned(i,4)); +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_read_in <= '1'; +-- wait for 30 ns; +-- bus_read_in <= '0'; +-- end loop; +-- +-- wait for 500*8 ns; +-- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); +-- bus_addr_in(4 downto 0) <= statuscounter; +-- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_read_in <= '1'; +-- wait for 30 ns; +-- bus_read_in <= '0'; +-- wait for 500*8 ns; +-- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); +-- bus_addr_in(4 downto 0) <= statuscounter; +-- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_read_in <= '1'; +-- wait for 30 ns; +-- bus_read_in <= '0'; +-- wait for 500*8 ns; +-- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); +-- bus_addr_in(4 downto 0) <= statuscounter; +-- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_read_in <= '1'; +-- wait for 30 ns; +-- bus_read_in <= '0'; +-- wait for 500*8 ns; +-- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); +-- bus_addr_in(4 downto 0) <= statuscounter; +-- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); +-- wait for 20 ns; +-- wait until CLK_IN = '1'; +-- bus_read_in <= '1'; +-- wait for 30 ns; +-- bus_read_in <= '0'; +-- -- +-- -- wait for 500*8 ns; +-- -- bus_data_in(31 downto 0) <= x"80FFFF01"; +-- -- bus_addr_in(3 downto 0) <= ADDR_DATA; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- -- +-- -- wait for 500*8 ns; +-- -- bus_data_in(31 downto 0) <= x"00000020"; +-- -- bus_addr_in(3 downto 0) <= ADDR_LENGTH; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- -- +-- -- wait for 500*8 ns; +-- -- bus_data_in(3 downto 0) <= CMD_SHIFT_DR; +-- -- bus_addr_in(3 downto 0) <= ADDR_CMD; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- -- wait until jtag_tck_out = '1'; +-- -- wait until jtag_tck_out = '0'; +-- -- --jtag_tdo_in <= '1'; +-- -- wait until jtag_tck_out = '1'; +-- -- wait until jtag_tck_out = '0'; +-- -- --jtag_tdo_in <= '0'; +-- -- +-- -- wait for 60*8 us; +-- -- wait for 500*8 ns; +-- -- bus_data_in(3 downto 0) <= "0000"; +-- -- bus_addr_in(3 downto 0) <= ADDR_DATA; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- -- +-- -- wait for 500*8 ns; +-- -- bus_data_in(3 downto 0) <= CMD_UPDATE_DR; +-- -- bus_addr_in(3 downto 0) <= ADDR_CMD; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- -- +-- -- wait for 30*8 us; +-- -- bus_data_in(3 downto 0) <= "0000"; +-- -- bus_addr_in(3 downto 0) <= ADDR_DATA; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_read_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_read_in <= '0'; +-- -- +-- -- wait for 30*8 us; +-- -- jtag_tdo_in <= '1'; +-- -- bus_data_in(3 downto 0) <= CMD_RESET_JTAG; +-- -- bus_addr_in(3 downto 0) <= ADDR_CMD; +-- -- wait for 20 ns; +-- -- wait until CLK_IN = '1'; +-- -- bus_write_in <= '1'; +-- -- wait for 20 ns; +-- -- bus_write_in <= '0'; +-- +-- +-- -- cmd_in <= CMD_NONE; +-- -- wait until READY_FOR_CMD_OUT = '1'; +-- -- data_in <= '1'; +-- -- cmd_in <= CMD_SHIFT_DR; +-- -- wait for 30 ns; +-- -- cmd_in <= CMD_NONE; +-- -- wait until jtag_tck_out = '1'; +-- -- wait until jtag_tck_out = '0'; +-- -- jtag_tdo_in <= '1'; +-- -- wait until READY_FOR_CMD_OUT = '1'; +-- -- data_in <= '1'; +-- -- cmd_in <= CMD_SHIFT_DR; +-- -- wait for 30 ns; +-- -- cmd_in <= CMD_NONE; +-- -- wait until jtag_tck_out = '1'; +-- -- wait until jtag_tck_out = '0'; +-- -- jtag_tdo_in <= '0'; +-- -- wait until READY_FOR_CMD_OUT = '1'; +-- -- cmd_in <= CMD_UPDATE_DR; +-- -- wait for 30 ns; +-- -- cmd_in <= CMD_NONE; +-- -- wait until READY_FOR_CMD_OUT = '1'; +-- -- wait for 30 ns; +-- -- cmd_in <= CMD_NONE; +-- wait; +-- end process; +--testdriver_clk : process +--begin +-- clk_in <= '0'; +-- wait for 5 ns; +-- clk_in <= '1'; +-- wait for 5 ns; +--end process; + + +end architecture; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd new file mode 100644 index 0000000..9dc5396 --- /dev/null +++ b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd @@ -0,0 +1,77 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +--USE IEEE.std_logic_ARITH.ALL; +--USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.numeric_std.ALL; +library work; +use work.jtag_constants.all; +use work.jtag_simulation_constants.all; + +entity jtag_cmd_m26c_test_regvaluesfrominput2_test is +end entity; + +architecture arch_sim of jtag_cmd_m26c_test_regvaluesfrominput2_test is + +component jtag_cmd_m26c_test_regvaluesfrominput2 is +generic( + numregs : integer := 11; + maxreglen : integer := 1152; + -- instruction_codes : instrArray := (0 => "10000", 1 => "10001", 2 => "10010", others => (others => '1')); -- in the given order these are the instruction codes of the registers to be programmed by the JTAG-Chain-Controller + --drlen : drlenArray := (0 => 32, 1=> 8, 2=> 1024, others => 32); -- length of the registers (same order as instruction_codes) + instruction_codes : instrArray := (0 => "01111", --BIAS_GEN + 1 => "10000", --LINE0_PATTERN_REG + 2 => "10001", --DIS_DISCRI + 3 => "10010", --SEQ_PIX_REG + 4 => "10011", --CTRL_PIX_REG + 5 => "10100", --LINE1_PATTERN_REG + 6 => "10101", --SEQ_SUZE_REG + 7 => "10110", --HEADER_TRAILER_REG + 8 => "10111", --CTRL_SUZE_REG + 9 => "11101", --RO_MODE1 + 10 => "11110", --RO_MODE0 + others => (others => '1')); + drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, others => 0); + + numchips : integer := 3 +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + REGISTERS_IN : in std_logic_vector(numchips*numregs*maxreglen-1 downto 0); + TRIGGER_IN : in std_logic + ); +end component; + +signal regs : std_logic_vector(3*11*1152-1 downto 0); +signal clk_in, reset_in, trigger : std_logic; +begin + regs(3*11*1152-1 downto 1152*2)<= (others => '0'); + regs(2*1152-1 downto 1152+5) <= (others => '0'); + regs(1152+4 downto 1152) <= "11101"; + regs(1152-1 downto 5) <= (others => '0'); + regs(4 downto 0) <= "11110"; + + +the_jtag_cmd_m26c_test_regvaluesfrominput2 : jtag_cmd_m26c_test_regvaluesfrominput2 port map (CLK_IN => clk_in, RESET_IN => reset_in, REGISTERS_IN => regs, TRIGGER_IN => trigger); + +testdriver_clk : process +begin + clk_in <= '0'; + wait for 5 ns; + clk_in <= '1'; + wait for 5 ns; +end process; + + +stim1 : process +begin + reset_in <= '1'; + wait for 100 ns; + reset_in <= '0'; + wait for 20 ns; + trigger <= '1'; + wait for 20 ns; + trigger <= '0'; + wait; +end process; +end architecture; diff --git a/vhdl/code/tb/jtag_simulation_constants.vhd b/vhdl/code/tb/jtag_simulation_constants.vhd new file mode 100644 index 0000000..6a57651 --- /dev/null +++ b/vhdl/code/tb/jtag_simulation_constants.vhd @@ -0,0 +1,11 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; + +package jtag_simulation_constants is + +constant IRLEN : integer := 5; -- number of bits for JTAG instruction register +constant MAXNUMREGS : integer := 40; +type instrArray is array(MAXNUMREGS-1 downto 0) of std_logic_vector(IRLEN-1 downto 0); +type drlenArray is array(MAXNUMREGS-1 downto 0) of integer; +end package jtag_simulation_constants; diff --git a/vhdl/code/tb/jtag_tap_mi26_hard.vhd b/vhdl/code/tb/jtag_tap_mi26_hard.vhd new file mode 100644 index 0000000..fc514da --- /dev/null +++ b/vhdl/code/tb/jtag_tap_mi26_hard.vhd @@ -0,0 +1,492 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +--USE IEEE.std_logic_ARITH.ALL; +--USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.numeric_std.ALL; +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +-- use work.trb_net16_hub_func.all; +--use work.version.all; +use work.jtag_constants.all; + +use work.jtag_simulation_constants.all; + + +entity jtag_tap_mi26_hard is +generic( + default_ir : std_logic_vector(IRLEN-1 downto 0) := "01110"; + maxreglen : integer := 1152; + dev_id : std_logic_vector := x"4d323601" +); +port( + TCK_EMU: in std_logic; + TMS_EMU: in std_logic; + TDI_EMU: in std_logic; + TDO_EMU: out std_logic; + TRSTB_EMU: in std_logic; + + REGISTERS_OUT: out std_logic_vector(12*maxreglen-1 downto 0) + ); +end entity; + + +architecture jtag_tap_mi26_hard_arch of jtag_tap_mi26_hard is +type TAP_STATE_TYPE is (TS_TEST_LOGIC_RESET, TS_RUN_TEST, TS_SELECT_DR, TS_CAPTURE_DR, TS_SHIFT_DR, TS_EXIT1_DR, TS_PAUSE_DR, TS_EXIT2_DR, TS_UPDATE_DR, TS_SELECT_IR, TS_CAPTURE_IR, TS_SHIFT_IR, TS_EXIT1_IR, TS_PAUSE_IR, TS_EXIT2_IR, TS_UPDATE_IR); + +signal tap_state : TAP_STATE_TYPE; +constant instruction_codes : instrArray := (0 => "01111", --BIAS_GEN + 1 => "10000", --LINE0_PATTERN_REG + 2 => "10001", --DIS_DISCRI + 3 => "10010", --SEQ_PIX_REG + 4 => "10011", --CTRL_PIX_REG + 5 => "10100", --LINE1_PATTERN_REG + 6 => "10101", --SEQ_SUZE_REG + 7 => "10110", --HEADER_TRAILER_REG + 8 => "10111", --CTRL_SUZE_REG + 9 => "11101", --RO_MODE1 + 10 => "11110", --RO_MODE0 + 11 => "01110", --ID_CODE + others => (others => '1')); +-- drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, 11=>32, others => 0); + +signal register0 : std_logic_vector(152-1 downto 0); +signal register1 : std_logic_vector(1152-1 downto 0); +signal register2 : std_logic_vector(1152-1 downto 0); +signal register3 : std_logic_vector(128-1 downto 0); +signal register4 : std_logic_vector(40-1 downto 0); +signal register5 : std_logic_vector(1152-1 downto 0); +signal register6 : std_logic_vector(160-1 downto 0); +signal register7 : std_logic_vector(64-1 downto 0); +signal register8 : std_logic_vector(48-1 downto 0); +signal register9 : std_logic_vector(8-1 downto 0); +signal register10 : std_logic_vector(8-1 downto 0); +signal register11 : std_logic_vector(32-1 downto 0); +--signal register_id_code : std_logic_vector(32-1 downto 0); + +--type REG_ARRAY is array (numregs-1 downto 0) of std_logic_vector(maxreglen-1 downto 0); +--signal registers_shift : REG_ARRAY; +signal ir_shift : std_logic_vector(IRLEN-1 downto 0); + +-- -1 is the invalid selection, which means no register selected +-- signal selected_dr : integer range -1 to numregs-1; --replaced for ifv. helped?? +signal selected_dr : integer range 0 to 12-1; +signal bypassreg : std_logic; +--signal tdi_sampled : std_logic; -- value of TDI_EMU sampled at rising edge of TCK_EMU + +begin + +REGISTERS_OUT(maxreglen-1 downto register0'left+1) <= (others => '0'); +REGISTERS_OUT(register0'left downto 0) <= register0; +REGISTERS_OUT(1*maxreglen+maxreglen-1 downto 1*maxreglen+register1'left+1) <= (others => '0'); +REGISTERS_OUT(1*maxreglen+register1'left downto 1*maxreglen) <= register1; +REGISTERS_OUT(2*maxreglen+maxreglen-1 downto 2*maxreglen+register2'left+1) <= (others => '0'); +REGISTERS_OUT(2*maxreglen+register2'left downto 2*maxreglen) <= register2; +REGISTERS_OUT(3*maxreglen+maxreglen-1 downto 3*maxreglen+register3'left+1) <= (others => '0'); +REGISTERS_OUT(3*maxreglen+register3'left downto 3*maxreglen) <= register3; +REGISTERS_OUT(4*maxreglen+maxreglen-1 downto 4*maxreglen+register4'left+1) <= (others => '0'); +REGISTERS_OUT(4*maxreglen+register4'left downto 4*maxreglen) <= register4; +REGISTERS_OUT(5*maxreglen+maxreglen-1 downto 5*maxreglen+register5'left+1) <= (others => '0'); +REGISTERS_OUT(5*maxreglen+register5'left downto 5*maxreglen) <= register5; +REGISTERS_OUT(6*maxreglen+maxreglen-1 downto 6*maxreglen+register6'left+1) <= (others => '0'); +REGISTERS_OUT(6*maxreglen+register6'left downto 6*maxreglen) <= register6; +REGISTERS_OUT(7*maxreglen+maxreglen-1 downto 7*maxreglen+register7'left+1) <= (others => '0'); +REGISTERS_OUT(7*maxreglen+register7'left downto 7*maxreglen) <= register7; +REGISTERS_OUT(8*maxreglen+maxreglen-1 downto 8*maxreglen+register8'left+1) <= (others => '0'); +REGISTERS_OUT(8*maxreglen+register8'left downto 8*maxreglen) <= register8; +REGISTERS_OUT(9*maxreglen+maxreglen-1 downto 9*maxreglen+register9'left+1) <= (others => '0'); +REGISTERS_OUT(9*maxreglen+register9'left downto 9*maxreglen) <= register9; +REGISTERS_OUT(10*maxreglen+maxreglen-1 downto 10*maxreglen+register10'left+1) <= (others => '0'); +REGISTERS_OUT(10*maxreglen+register10'left downto 10*maxreglen) <= register10; +REGISTERS_OUT(12*maxreglen - 1 downto 11*maxreglen) <= (others => '0'); +tap_state_transition: process(TCK_EMU, TRSTB_EMU) +begin + if(rising_edge(TCK_EMU)) then + case tap_state is + when TS_TEST_LOGIC_RESET => + if(TMS_EMU = '0') then + tap_state <= TS_RUN_TEST; + end if; + + when TS_RUN_TEST => + if(TMS_EMU = '1') then + tap_state <= TS_SELECT_DR; + end if; + + when TS_SELECT_DR => + if(TMS_EMU = '1') then + tap_state <= TS_SELECT_IR; + else + tap_state <= TS_CAPTURE_DR; + end if; + + when TS_CAPTURE_DR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT1_DR; + else + tap_state <= TS_SHIFT_DR; + end if; + + when TS_SHIFT_DR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT1_DR; + end if; + + when TS_EXIT1_DR => + if(TMS_EMU = '1') then + tap_state <= TS_UPDATE_DR; + else + tap_state <= TS_PAUSE_DR; + end if; + + when TS_PAUSE_DR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT2_DR; + end if; + + when TS_EXIT2_DR => + if(TMS_EMU = '1') then + tap_state <= TS_UPDATE_DR; + else + tap_state <= TS_SHIFT_DR; + end if; + + when TS_UPDATE_DR => + if(TMS_EMU = '1') then + tap_state <= TS_SELECT_DR; + else + tap_state <= TS_RUN_TEST; + end if; + + -- equivalent states for IR + when TS_SELECT_IR => + if(TMS_EMU = '1') then + tap_state <= TS_TEST_LOGIC_RESET; + else + tap_state <= TS_CAPTURE_IR; + end if; + + when TS_CAPTURE_IR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT1_IR; + else + tap_state <= TS_SHIFT_IR; + end if; + + when TS_SHIFT_IR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT1_IR; + end if; + + when TS_EXIT1_IR => + if(TMS_EMU = '1') then + tap_state <= TS_UPDATE_IR; + else + tap_state <= TS_PAUSE_IR; + end if; + + when TS_PAUSE_IR => + if(TMS_EMU = '1') then + tap_state <= TS_EXIT2_IR; + end if; + + when TS_EXIT2_IR => + if(TMS_EMU = '1') then + tap_state <= TS_UPDATE_IR; + else + tap_state <= TS_SHIFT_IR; + end if; + + when TS_UPDATE_IR => + if(TMS_EMU = '1') then + tap_state <= TS_SELECT_DR; + else + tap_state <= TS_RUN_TEST; + end if; + + end case; + end if; + + if(TRSTB_EMU = '1') then + tap_state <= TS_TEST_LOGIC_RESET; + end if; + + +end process; + +tap_registers: process (TCK_EMU, TRSTB_EMU) +variable i: integer; +begin + -- update registers + if(rising_edge(TCK_EMU)) then + case tap_state is + when TS_TEST_LOGIC_RESET => + --selected_dr <= -1; --replaced for ifv. helped?? + selected_dr <= 0; + for i in 12-1 downto 0 loop + if instruction_codes(i) = default_ir then + selected_dr <= i; + end if; + end loop; + ir_shift <= default_ir; + + when TS_RUN_TEST => + + when TS_SELECT_DR => + if(selected_dr = 11) then --ID_CODE + register11(31 downto 0) <= dev_id; + end if; + when TS_CAPTURE_DR => + -- in first version: DONt copy register value to shift register +-- if(selected_dr>=0) then +-- registers_shift(selected_dr) <= registers((selected_dr+1)*maxreglen-1 downto selected_dr*maxreglen); +-- end if; + + + + when TS_SHIFT_DR => + case selected_dr is + when 0 => + register0(register0'left-1 downto 0) <= register0(register0'left downto 1); + register0(register0'left) <= TDI_EMU; + when 1 => + register1(register1'left-1 downto 0) <= register1(register1'left downto 1); + register1(register1'left) <= TDI_EMU; + when 2 => + register2(register2'left-1 downto 0) <= register2(register2'left downto 1); + register2(register2'left) <= TDI_EMU; + when 3 => + register3(register3'left-1 downto 0) <= register3(register3'left downto 1); + register3(register3'left) <= TDI_EMU; + when 4 => + register4(register4'left-1 downto 0) <= register4(register4'left downto 1); + register4(register4'left) <= TDI_EMU; + when 5 => + register5(register5'left-1 downto 0) <= register5(register5'left downto 1); + register5(register5'left) <= TDI_EMU; + when 6 => + register6(register6'left-1 downto 0) <= register6(register6'left downto 1); + register6(register6'left) <= TDI_EMU; + when 7 => + register7(register7'left-1 downto 0) <= register7(register7'left downto 1); + register7(register7'left) <= TDI_EMU; + when 8 => + register8(register8'left-1 downto 0) <= register8(register8'left downto 1); + register8(register8'left) <= TDI_EMU; + when 9 => + register9(register9'left-1 downto 0) <= register9(register9'left downto 1); + register9(register9'left) <= TDI_EMU; + when 10 => + register10(register10'left-1 downto 0) <= register10(register10'left downto 1); + register10(register10'left) <= TDI_EMU; + when 11 => -- ID_CODE + -- emulate shift register + register11(register11'left-1 downto 0) <= register11(register11'left downto 1); + register11(register11'left) <= TDI_EMU; + when others => + bypassreg <= TDI_EMU; + end case; + +-- 1 => "10000", --LINE0_PATTERN_REG +-- 2 => "10001", --DIS_DISCRI +-- 3 => "10010", --SEQ_PIX_REG +-- 4 => "10011", --CTRL_PIX_REG +-- 5 => "10100", --LINE1_PATTERN_REG +-- 6 => "10101", --SEQ_SUZE_REG +-- 7 => "10110", --HEADER_TRAILER_REG +-- 8 => "10111", --CTRL_SUZE_REG +-- 9 => "11101", --RO_MODE1 +-- 10 => "11110", --RO_MODE0 +-- others => (others => '1')); +-- +-- --registers_shift(selected_dr)(drlen(selected_dr)-2 downto 0) <= registers_shift(selected_dr)(drlen(selected_dr)-1 downto 1); -- shift register with size of DR, LSB first +-- --registers_shift(selected_dr)(maxreglen-2 downto 0) <= registers_shift(selected_dr)(maxreglen-1 downto 1); -- replaced by this const expr for ifv-- shift register with size of DR, LSB first +-- --registers_shift(selected_dr)(drlen(selected_dr)-1) <= TDI_EMU; -- use sampled TDI input, store in shift register +-- for i in 0 to maxreglen-2 loop +-- if(i + + when TS_PAUSE_DR => + + when TS_EXIT2_DR => + + when TS_UPDATE_DR => + -- for mi26 hard first implementation DONt do the following +-- if(selected_dr>=0) then +-- -- store shift register value to register number selected_dr +-- registers((selected_dr+1)*maxreglen-1 downto selected_dr*maxreglen) <= registers_shift(selected_dr); +-- end if; + + -- equivalent states for IR + when TS_SELECT_IR => + + when TS_CAPTURE_IR => + + + when TS_SHIFT_IR => + ir_shift(irlen-2 downto 0) <= ir_shift(irlen-1 downto 1); + --ir_shift(irlen-1) <= tdi_sampled; -- LSB first + ir_shift(irlen-1) <= TDI_EMU; -- LSB first + + + when TS_EXIT1_IR => + + when TS_PAUSE_IR => + + when TS_EXIT2_IR => + + when TS_UPDATE_IR => + for i in 12-1 downto 0 loop + if instruction_codes(i) = ir_shift then + selected_dr <= i; + end if; + end loop; + end case; + end if; + +end process; + +tap_output: process (TCK_EMU, TRSTB_EMU) +variable i: integer; +begin +-- output on falling edge + if(falling_edge(TCK_EMU)) then + case tap_state is + when TS_CAPTURE_DR => + -- copy register value to shift register + -- case selected_dr is +-- when 0 => +-- TDO_EMU <= register0(0); +-- when 1 => +-- TDO_EMU <= register1(0); +-- when 2 => +-- TDO_EMU <= register2(0); +-- when 3 => +-- TDO_EMU <= register3(0); +-- when 4 => +-- TDO_EMU <= register4(0); +-- when 5 => +-- TDO_EMU <= register5(0); +-- when 6 => +-- TDO_EMU <= register6(0); +-- when 7 => +-- TDO_EMU <= register7(0); +-- when 8 => +-- TDO_EMU <= register8(0); +-- when 9 => +-- TDO_EMU <= register9(0); +-- when 10 => +-- TDO_EMU <= register10(0); +-- when 11 => +-- TDO_EMU <= register11(0); +-- when others => +-- TDO_EMU <= bypassreg; +-- end case; + when TS_SHIFT_DR => + case selected_dr is + when 0 => + TDO_EMU <= register0(0); + when 1 => + TDO_EMU <= register1(0); + when 2 => + TDO_EMU <= register2(0); + when 3 => + TDO_EMU <= register3(0); + when 4 => + TDO_EMU <= register4(0); + when 5 => + TDO_EMU <= register5(0); + when 6 => + TDO_EMU <= register6(0); + when 7 => + TDO_EMU <= register7(0); + when 8 => + TDO_EMU <= register8(0); + when 9 => + TDO_EMU <= register9(0); + when 10 => + TDO_EMU <= register10(0); + when 11 => + TDO_EMU <= register11(0); + when others => + TDO_EMU <= bypassreg; + end case; + when TS_EXIT1_DR => + -- the same: update output because in last shift operation register has been shifted + case selected_dr is + when 0 => + TDO_EMU <= register0(0); + when 1 => + TDO_EMU <= register1(0); + when 2 => + TDO_EMU <= register2(0); + when 3 => + TDO_EMU <= register3(0); + when 4 => + TDO_EMU <= register4(0); + when 5 => + TDO_EMU <= register5(0); + when 6 => + TDO_EMU <= register6(0); + when 7 => + TDO_EMU <= register7(0); + when 8 => + TDO_EMU <= register8(0); + when 9 => + TDO_EMU <= register9(0); + when 10 => + TDO_EMU <= register10(0); + when 11 => + TDO_EMU <= register11(0); + when others => + TDO_EMU <= bypassreg; + end case; + when TS_UPDATE_DR => + -- added as test for errors + TDO_EMU <= '1'; + when TS_CAPTURE_IR => + TDO_EMU <= ir_shift(0); + when TS_SHIFT_IR => + TDO_EMU <= ir_shift(0); + when TS_EXIT1_IR => + -- the same: update output because in last shift operation register has been shifted + TDO_EMU <= ir_shift(0); + when others => + end case; + end if; + if(TRSTB_EMU = '1') then + TDO_EMU <= '0'; + end if; +end process; + +-- tap_sample_input: process (TCK_EMU, TRSTB_EMU) +-- +-- begin +-- if(rising_edge(TCK_EMU)) then +-- tdi_sampled <= TDI_EMU; +-- +-- end if; +-- if(TRSTB_EMU = '1') then +-- tdi_sampled <= '0'; +-- end if; +-- +-- end process; + + +end architecture; diff --git a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf b/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf index 7f5daec..a8477a2 100644 --- a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf +++ b/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf @@ -626,7 +626,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 10 ms +RunLength = 2 ms ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1644,65 +1644,73 @@ suppress = 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 29 -Project_File_0 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_dp.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 21 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_1 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_data_to_ram_m10.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356029 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_2 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_bypassreg_testchain_m10.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349358604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_3 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_delay_expected_values.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355704 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_4 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_write_m10.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_5 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux2to1_writeport.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 23 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_6 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_read_m26devid_m10.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355852 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_7 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355799 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_8 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux2to1_readport.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 22 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_9 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_update_error_counts_ram3a.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349358039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_10 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/blank_ram.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_11 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_cmd_m26c_test.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350916161 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_12 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net16_regio_bus_handler.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_13 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_cmd_m26c.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907441 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_14 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/ram_mux4to1_readport.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 24 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_15 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_misc.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907477 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_16 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/copy_ram.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net_components.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_18 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_check_crc_ram1a.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356551 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_19 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_init_ram1b.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349355717 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/crc_32.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_21 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_sample.vhd -Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_22 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/version.vhd -Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_23 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_compare_counttotal_noram_m10.vhd -Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350915625 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_24 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tdo_compare_count_m10.vhd -Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349356574 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_25 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/trb_net_std.vhd -Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_26 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_tck_out_component.vhd -Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_27 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_pulses.vhd -Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349351254 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_28 = /d/jspc29/bneumann/vhdl/jtag_proj/trb_jtag3_threecontrollers_vardelay012_generics/jtag_m26c/jtag_constants.vhd -Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350907278 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_Files_Count = 33 +Project_File_0 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/mathhelpers.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363372165 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_1 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_sample.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_2 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_components.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_3 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363802534 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_4 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363807206 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_5 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_count_m10.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_6 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tck_out_component.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_7 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_pulses.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_8 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_tap_mi26_hard.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363806490 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 31 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_9 = /local/bneumann/vhdl/jtag_proj/NEW/trb3/mvdjtag/version.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363372374 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_10 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_constants.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_11 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_dp.vhd +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_12 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_data_to_ram_m10.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_13 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_std.vhd +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_14 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_delay_expected_values.vhd +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_15 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_bypassreg_testchain_m10.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_16 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_write_m10.vhd +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363371102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801035 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_18 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_writeport.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_19 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_read_m26devid_m10.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_20 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363798313 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_21 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_readport.vhd +Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_22 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_update_error_counts_ram3a.vhd +Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_23 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/blank_ram.vhd +Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_24 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_cmd_m26c.vhd +Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363808130 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_25 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux4to1_readport.vhd +Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_26 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_misc.vhd +Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_27 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/copy_ram.vhd +Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_28 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_simulation_constants.vhd +Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801664 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_29 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_init_ram1b.vhd +Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_30 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_check_crc_ram1a.vhd +Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_31 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net16_regio_bus_handler.vhd +Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_32 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/crc_32.vhd +Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 -- 2.43.0