From f6ee2fa6f2ae5631827876a941a35b584056d9b1 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Wed, 4 Sep 2013 11:26:11 +0200 Subject: [PATCH] Contraints for MuPix Design --- base/trb3_periph_mupix.lpf | 238 +++++++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) create mode 100644 base/trb3_periph_mupix.lpf diff --git a/base/trb3_periph_mupix.lpf b/base/trb3_periph_mupix.lpf new file mode 100644 index 0000000..1053a3a --- /dev/null +++ b/base/trb3_periph_mupix.lpf @@ -0,0 +1,238 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + #SYSCONFIG MCCLK_FREQ = 2.5; + + #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; + + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; + + + + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +#IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +################################################################# +# Flash ROM and Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; + +################################################################# +#MuPix 4 +################################################################# +#SlowControl and Misc +LOCATE COMP "fpga_led_to_board_0" SITE "AB5"; +LOCATE COMP "fpga_led_to_board_1" SITE "AB6"; +LOCATE COMP "fpga_led_to_board_2" SITE "Y6"; +LOCATE COMP "fpga_led_to_board_3" SITE "Y7"; +DEFINE PORT GROUP "fpga_led_group" "fpga_led*"; +IOBUF GROUP "fpga_led_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "fpga_aux_to_board_0" SITE "T7"; +LOCATE COMP "fpga_aux_to_board_1" SITE "R6"; +LOCATE COMP "fpga_aux_to_board_2" SITE "K2"; +LOCATE COMP "fpga_aux_to_board_3" SITE "T8"; +LOCATE COMP "fpga_aux_to_board_4" SITE "K4"; +LOCATE COMP "fpga_aux_to_board_5" SITE "K1"; +LOCATE COMP "fpga_aux_to_board_6" SITE "E1"; +LOCATE COMP "fpga_aux_to_board_7" SITE "K5"; +LOCATE COMP "fpga_aux_to_board_8" SITE "B2"; +LOCATE COMP "fpga_aux_to_board_9" SITE "B3"; +DEFINE PORT GROUP "fpga_aux_group" "fpga_aux*"; +IOBUF GROUP "fpga_aux_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "testpulse2_to_board" SITE "AA4"; +LOCATE COMP "testpulse1_to_board" SITE "AA3"; +IOBUF PORT "testpulse2_to_board" IO_TYPE=LVCMOS25 ; +IOBUF PORT "testpulse1_to_board" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "spi_din_to_board" SITE "T3"; +LOCATE COMP "spi_ld_to_board" SITE "R5"; +LOCATE COMP "spi_clk_to_board" SITE "R4"; +DEFINE PORT GROUP "spi_group" "spi*"; +IOBUF GROUP "spigroup" IO_TYPE=LVCMOS25; + +LOCATE COMP "hbus_from_mupix" SITE "W8"; +IOBUF PORT "hbus_from_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_d_from_mupix" SITE "V1"; +IOBUF PORT "sout_d_from_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sout_c_from_mupix" SITE "U2"; +IOBUF PORT "sout_c_from_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "sin_to_mupix" SITE "T1"; +IOBUF PORT "sin_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_d_to_mupix" SITE "P4"; +IOBUF PORT "ck_d_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ld_c_to_mupix" SITE "U1"; +IOBUF PORT "ld_c_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ck_c_to_mupix" SITE "R3"; +IOBUF PORT "ck_c_to_mupix" IO_TYPE=LVCMOS25 ; + + +#MuPix Readout +LOCATE COMP "rowaddr_from_mupix_0" SITE "H2"; +LOCATE COMP "rowaddr_from_mupix_1" SITE "H1"; +LOCATE COMP "rowaddr_from_mupix_2" SITE "M5"; +LOCATE COMP "rowaddr_from_mupix_3" SITE "L2"; +LOCATE COMP "rowaddr_from_mupix_4" SITE "C2"; +LOCATE COMP "rowaddr_from_mupix_5" SITE "K3"; +DEFINE PORT GROUP "rowaddr_from_mupix_group" "rowaddr_from_mupix*"; +IOBUF GROUP "rowaddr_from_mupix_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "coladdr_from_mupix_0" SITE "W6"; +LOCATE COMP "coladdr_from_mupix_1" SITE "AA5"; +LOCATE COMP "coladdr_from_mupix_2" SITE "V7"; +LOCATE COMP "coladdr_from_mupix_3" SITE "G1"; +LOCATE COMP "coladdr_from_mupix_4" SITE "J1"; +LOCATE COMP "coladdr_from_mupix_5" SITE "L1"; +DEFINE PORT GROUP "coladdr_from_mupix_group" "coladdr_from_mupix*"; +IOBUF GROUP "coladdr_from_mupix_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_from_mupix_0" SITE "U3"; +LOCATE COMP "timestamp_from_mupix_1" SITE "R2"; +LOCATE COMP "timestamp_from_mupix_2" SITE "P3"; +LOCATE COMP "timestamp_from_mupix_3" SITE "P6"; +LOCATE COMP "timestamp_from_mupix_4" SITE "N6"; +LOCATE COMP "timestamp_from_mupix_5" SITE "AC3"; +LOCATE COMP "timestamp_from_mupix_6" SITE "AC1"; +LOCATE COMP "timestamp_from_mupix_7" SITE "AA2"; +DEFINE PORT GROUP "timestamp_from_mupix_group" "timestamp_from_mupix*"; +IOBUF GROUP "timestamp_from_mupix_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "timestamp_to_mupix_0" SITE "P5"; +LOCATE COMP "timestamp_to_mupix_1" SITE "N5"; +LOCATE COMP "timestamp_to_mupix_2" SITE "AC2"; +LOCATE COMP "timestamp_to_mupix_3" SITE "AB1"; +LOCATE COMP "timestamp_to_mupix_4" SITE "AA1"; +LOCATE COMP "timestamp_to_mupix_5" SITE "W7"; +LOCATE COMP "timestamp_to_mupix_6" SITE "Y5"; +LOCATE COMP "timestamp_to_mupix_7" SITE "V6"; +DEFINE PORT GROUP "timestamp_to_mupix_group" "timestamp_to_mupix*"; +IOBUF GROUP "timestamp_to_mupix_group" IO_TYPE=LVCMOS25; + + +LOCATE COMP "ldpix_to_mupix" SITE "T2"; +IOBUF PORT "ldpix_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "ldcol_to_mupix" SITE "N3"; +IOBUF PORT "ldcol_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "rdcol_to_mupix" SITE "J4"; +IOBUF PORT "rdcol_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "pulldown_to_mupix" SITE "L3"; +IOBUF PORT "pulldown_to_mupix" IO_TYPE=LVCMOS25 ; +LOCATE COMP "priout_from_mupix" SITE "J3"; +IOBUF PORT "priout_from_mupix" IO_TYPE=LVCMOS25 ; + + + + + + + + + + + -- 2.43.0