From f77800f1bb63661e52d2752f597539d1d89eb2cd Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 2 Dec 2010 14:41:42 +0000 Subject: [PATCH] *** empty log message *** --- lattice/scm/trb_net16_fifo_arch.vhd | 13 +++- media_interfaces/scm_sfp/serdes_gbe_0_200.txt | 12 +-- pinout/cts_fpga1.lpf | 76 +++++++++---------- 3 files changed, 53 insertions(+), 48 deletions(-) diff --git a/lattice/scm/trb_net16_fifo_arch.vhd b/lattice/scm/trb_net16_fifo_arch.vhd index b8aae5a..37b4332 100644 --- a/lattice/scm/trb_net16_fifo_arch.vhd +++ b/lattice/scm/trb_net16_fifo_arch.vhd @@ -29,13 +29,17 @@ architecture arch_trb_net16_fifo of trb_net16_fifo is component lattice_scm_fifo_18x1k is port ( Data: in std_logic_vector(17 downto 0); - Clock: in std_logic; + WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(17 downto 0); Empty: out std_logic; - Full: out std_logic); + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); end component; @@ -94,17 +98,18 @@ begin fifo:lattice_scm_fifo_18x1k port map ( Data => din, - Clock => CLK, + WrClock => CLK, + RdClock => CLK, WrEn => WRITE_ENABLE_IN, RdEn => READ_ENABLE_IN, Reset => RESET, + RPReset => RESET, Q => dout, Empty => EMPTY_OUT, Full => FULL_OUT ); -- end generate; - -- gen_FIFO1 : if DEPTH = 1 generate -- fifo:lattice_scm_fifo_18x16 -- port map ( diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_200.txt b/media_interfaces/scm_sfp/serdes_gbe_0_200.txt index 24756ba..1df7bc2 100755 --- a/media_interfaces/scm_sfp/serdes_gbe_0_200.txt +++ b/media_interfaces/scm_sfp/serdes_gbe_0_200.txt @@ -20,21 +20,21 @@ quad 04 00 # MCA enable 4 channels quad 18 10 # 8b10b Mode quad 14 FF # Word Alignment Mask [7:0] -quad 15 05 # +ve K [7:0] -> COMMA_A = 11_0000_0101 -quad 16 FA # -ve K [7:0] -> COMMA_B = 00_1111_1010 -quad 17 3C # upper bits of CA,CB,CM +quad 15 83 # +ve K [7:0] -> COMMA_A = 11_0000_0101 - its inverted (see register convention in datasheet)! +quad 16 7c # -ve K [7:0] -> COMMA_B = 00_1111_1010 - its inverted ! +quad 17 36 # upper bits of CA,CB,CM quad 0D 97 # Watermark level on CTC: 9 high, 7 low quad 0E 0B # insertion/deletion control of CTC: two char matching quad 11 BC # /I2/ pattern for CTC match (K28.5) -quad 12 50 # (D16.2) +quad 12 50 # (D16.2) quad 13 04 # (use comma) quad 19 0C # Disable word_align_en port, FPGA bus width is 16-bit/20-bit -ch0 14 90 # 16% pre-emphasis +ch0 14 90 # 16% pre-emphasis ch0 15 10 # +6dB equalization -# These lines must appear last in the autoconfig file. These lines apply the correct +# These lines must appear last in the autoconfig file. These lines apply the correct # reset sequence to the PCS block upon bitstream configuration quad 41 00 # de-assert serdes_rst quad 40 ff # assert datapath reset for all channels diff --git a/pinout/cts_fpga1.lpf b/pinout/cts_fpga1.lpf index 5109026..60782a6 100644 --- a/pinout/cts_fpga1.lpf +++ b/pinout/cts_fpga1.lpf @@ -77,7 +77,7 @@ LOCATE COMP "ADO_TTL_44" SITE "AM9"; LOCATE COMP "ADO_TTL_45" SITE "AM8"; LOCATE COMP "ADO_TTL_46" SITE "AF13"; DEFINE PORT GROUP "ADOTTL_group" "ADO_TTL*" ; -IOBUF GROUP "ADOTTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16; +IOBUF GROUP "ADOTTL_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16; #should be LVTTL33 LOCATE COMP "FS_PE_5" SITE "AE13"; LOCATE COMP "FS_PE_6" SITE "AL9"; @@ -87,45 +87,45 @@ LOCATE COMP "FS_PE_9" SITE "AK9"; LOCATE COMP "FS_PE_10" SITE "AJ9"; LOCATE COMP "FS_PE_11" SITE "AG10"; DEFINE PORT GROUP "FSPE_group" "FS_PE*" ; -IOBUF GROUP "FSPE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16; +IOBUF GROUP "FSPE_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16; #should be LVTTL33 ################################################################# # Debug ################################################################# -LOCATE COMP "TEST_LINE_0" SITE "AL6"; -LOCATE COMP "TEST_LINE_1" SITE "AL5"; -LOCATE COMP "TEST_LINE_2" SITE "AG7"; -LOCATE COMP "TEST_LINE_3" SITE "AG8"; -LOCATE COMP "TEST_LINE_4" SITE "AK6"; -LOCATE COMP "TEST_LINE_5" SITE "AJ6"; -LOCATE COMP "TEST_LINE_6" SITE "AF10"; -LOCATE COMP "TEST_LINE_7" SITE "AE11"; -LOCATE COMP "TEST_LINE_8" SITE "AM4"; -LOCATE COMP "TEST_LINE_9" SITE "AM3"; -LOCATE COMP "TEST_LINE_10" SITE "AH5"; -LOCATE COMP "TEST_LINE_11" SITE "AH4"; -LOCATE COMP "TEST_LINE_12" SITE "AK5"; -LOCATE COMP "TEST_LINE_13" SITE "AJ5"; -LOCATE COMP "TEST_LINE_14" SITE "AF8"; -LOCATE COMP "TEST_LINE_15" SITE "AF7"; -LOCATE COMP "TEST_LINE_16" SITE "AL4"; -LOCATE COMP "TEST_LINE_17" SITE "AL3"; -LOCATE COMP "TEST_LINE_18" SITE "AG5"; -LOCATE COMP "TEST_LINE_19" SITE "AF6"; -LOCATE COMP "TEST_LINE_20" SITE "AK3"; -LOCATE COMP "TEST_LINE_21" SITE "AJ3"; -LOCATE COMP "TEST_LINE_22" SITE "AE10"; -LOCATE COMP "TEST_LINE_23" SITE "AD10"; -LOCATE COMP "TEST_LINE_24" SITE "AL2"; -LOCATE COMP "TEST_LINE_25" SITE "AK2"; -LOCATE COMP "TEST_LINE_26" SITE "AE9"; -LOCATE COMP "TEST_LINE_27" SITE "AE8"; -LOCATE COMP "TEST_LINE_28" SITE "AJ1"; -LOCATE COMP "TEST_LINE_29" SITE "AK1"; -LOCATE COMP "TEST_LINE_30" SITE "AJ2"; -LOCATE COMP "TEST_LINE_31" SITE "AH3"; -DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=16; +# LOCATE COMP "TEST_LINE_0" SITE "AL6"; +# LOCATE COMP "TEST_LINE_1" SITE "AL5"; +# LOCATE COMP "TEST_LINE_2" SITE "AG7"; +# LOCATE COMP "TEST_LINE_3" SITE "AG8"; +# LOCATE COMP "TEST_LINE_4" SITE "AK6"; +# LOCATE COMP "TEST_LINE_5" SITE "AJ6"; +# LOCATE COMP "TEST_LINE_6" SITE "AF10"; +# LOCATE COMP "TEST_LINE_7" SITE "AE11"; +# LOCATE COMP "TEST_LINE_8" SITE "AM4"; +# LOCATE COMP "TEST_LINE_9" SITE "AM3"; +# LOCATE COMP "TEST_LINE_10" SITE "AH5"; +# LOCATE COMP "TEST_LINE_11" SITE "AH4"; +# LOCATE COMP "TEST_LINE_12" SITE "AK5"; +# LOCATE COMP "TEST_LINE_13" SITE "AJ5"; +# LOCATE COMP "TEST_LINE_14" SITE "AF8"; +# LOCATE COMP "TEST_LINE_15" SITE "AF7"; +# LOCATE COMP "TEST_LINE_16" SITE "AL4"; +# LOCATE COMP "TEST_LINE_17" SITE "AL3"; +# LOCATE COMP "TEST_LINE_18" SITE "AG5"; +# LOCATE COMP "TEST_LINE_19" SITE "AF6"; +# LOCATE COMP "TEST_LINE_20" SITE "AK3"; +# LOCATE COMP "TEST_LINE_21" SITE "AJ3"; +# LOCATE COMP "TEST_LINE_22" SITE "AE10"; +# LOCATE COMP "TEST_LINE_23" SITE "AD10"; +# LOCATE COMP "TEST_LINE_24" SITE "AL2"; +# LOCATE COMP "TEST_LINE_25" SITE "AK2"; +# LOCATE COMP "TEST_LINE_26" SITE "AE9"; +# LOCATE COMP "TEST_LINE_27" SITE "AE8"; +# LOCATE COMP "TEST_LINE_28" SITE "AJ1"; +# LOCATE COMP "TEST_LINE_29" SITE "AK1"; +# LOCATE COMP "TEST_LINE_30" SITE "AJ2"; +# LOCATE COMP "TEST_LINE_31" SITE "AH3"; +# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=16; ################################################################# # To second FPGA @@ -187,7 +187,7 @@ LOCATE COMP "SPI_CLK_OUT" SITE "A19"; LOCATE COMP "SPI_CS_OUT" SITE "A20"; LOCATE COMP "SPI_SI_OUT" SITE "H18"; LOCATE COMP "SPI_SO_IN" SITE "H17"; -LOCATE COMP "PROGRAMN_OUT" SITE "K12"; +LOCATE COMP "PROGRAMN_OUT" SITE "B17"; IOBUF PORT "SPI_CLK_OUT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; IOBUF PORT "SPI_CS_OUT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; IOBUF PORT "SPI_SI_OUT" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; @@ -243,7 +243,7 @@ LOCATE COMP "RS2_1" SITE "AF11"; LOCATE COMP "RS2_2" SITE "AD12"; LOCATE COMP "RS2_3" SITE "AE12"; DEFINE PORT GROUP "RS_group" "RS*" ; -IOBUF GROUP "RS_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +IOBUF GROUP "RS_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=16; #should be LVTTL33 ################################################################# # SFP -- 2.43.0