From f870590000bf077a9f455f404368915651cb9147 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 14 Jul 2009 12:52:04 +0000 Subject: [PATCH] bug fix . --- libtrbnet/trbnet.c | 389 +++++++++++++++++++++++---------------------- 1 file changed, 199 insertions(+), 190 deletions(-) diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 161c377..8247c3f 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -53,7 +53,7 @@ #define CHANNEL_N_SENDER_FIFO_STATUS 0x0104 #define CHANNEL_N_SENDER_STATUS 0x010f #define CHANNEL_N_RECEIVER_DATA 0x0203 -#define CHANNEL_N_RECEIVER_FIFO_STATUS 0x0204 +#define CHANNEL_N_RECEIVER_FIFO_STATUS 0x0204 #define CHANNEL_N_API_STATUS 0x0300 /* Registers inside Virtex FPGA -> TRBnet endpoint (channel 0) */ @@ -64,7 +64,7 @@ #define CHANNEL_0_SENDER_FIFO_STATUS 0x0114 #define CHANNEL_0_SENDER_STATUS 0x011f #define CHANNEL_0_RECEIVER_DATA 0x0213 -#define CHANNEL_0_RECEIVER_FIFO_STATUS 0x0214 +#define CHANNEL_0_RECEIVER_FIFO_STATUS 0x0214 #define CHANNEL_0_API_STATUS 0x0310 /* Registers inside Virtex FPGA -> TRBnet endpoint (channel 1) */ @@ -75,7 +75,7 @@ #define CHANNEL_1_SENDER_FIFO_STATUS 0x0134 #define CHANNEL_1_SENDER_STATUS 0x013f #define CHANNEL_1_RECEIVER_DATA 0x0233 -#define CHANNEL_1_RECEIVER_FIFO_STATUS 0x0234 +#define CHANNEL_1_RECEIVER_FIFO_STATUS 0x0234 #define CHANNEL_1_API_STATUS 0x0330 /* Registers inside Virtex FPGA -> TRBnet endpoint (channel 2) */ @@ -86,7 +86,7 @@ #define CHANNEL_2_SENDER_FIFO_STATUS 0x0154 #define CHANNEL_2_SENDER_STATUS 0x015f #define CHANNEL_2_RECEIVER_DATA 0x0253 -#define CHANNEL_2_RECEIVER_FIFO_STATUS 0x0254 +#define CHANNEL_2_RECEIVER_FIFO_STATUS 0x0254 #define CHANNEL_2_API_STATUS 0x0350 /* Registers inside Virtex FPGA -> TRBnet endpoint (channel 3) */ @@ -97,10 +97,10 @@ #define CHANNEL_3_SENDER_FIFO_STATUS 0x0174 #define CHANNEL_3_SENDER_STATUS 0x017f #define CHANNEL_3_RECEIVER_DATA 0x0273 -#define CHANNEL_3_RECEIVER_FIFO_STATUS 0x0274 +#define CHANNEL_3_RECEIVER_FIFO_STATUS 0x0274 #define CHANNEL_3_API_STATUS 0x0370 -/* SENDER_STATUS definitions */ +/* SENDER_STATUS definitions */ #define MASK_TX_RUNNING 0x00000001 /* Commands supported for packages */ @@ -140,7 +140,7 @@ typedef struct { /* Status-Bit definitions */ typedef enum { - Status_C_EndReached = 0, /* endpoint reached */ + Status_C_EndReached = 0, /* endpoint reached */ Status_C_Coll = 1, /* collision detected, */ Status_C_WordMiss = 2, /* word missing, */ Status_C_Checksum = 3, /* checksum error, */ @@ -149,13 +149,13 @@ typedef enum { } Status_Common; typedef enum { - Status_Ch0_TrigCtr = 0, /* trigger counter mismatch */ + Status_Ch0_TrigCtr = 0, /* trigger counter mismatch */ Status_Ch0_BufferHalfFull = 4, /* buffers half full */ Status_Ch0_BuffersFull = 5 /* buffers almost full */ } Status_CH0; typedef enum { - Status_Ch1_TrigNum = 0, /* trigger number mismatch */ + Status_Ch1_TrigNum = 0, /* trigger number mismatch */ Status_Ch1_TrigCode = 1, /* trigger code / random mismatch */ Status_Ch1_Length = 2, /* wrong length */ Status_Ch1_NoAnswer = 3, /* answer missing */ @@ -167,7 +167,7 @@ typedef enum { } Status_CH2; typedef enum { - Status_Ch3_Address = 0, /* unknown address */ + Status_Ch3_Address = 0, /* unknown address */ Status_Ch3_TimeOut = 4, /* timeout */ Status_Ch3_NoData = 5 /* nomoredata */ } Status_CH3; @@ -187,7 +187,7 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F2: 0x%04x --> data2\n", pkg->F2); fprintf(stderr, "F3: 0x%04x --> data3\n", pkg->F3); break; - + case HEADER_HDR: fprintf(stderr, "H0: 0x%04x --> HEADER channel: %01d reply: %01d\n", pkg->H0, @@ -196,12 +196,12 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F0: 0x%04x --> source address\n", pkg->F0); fprintf(stderr, "F1: 0x%04x --> target address\n", pkg->F1); fprintf(stderr, "F2: 0x%04x --> length\n", pkg->F2); - fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n", + fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n", pkg->F3, (pkg->F3 & MASK_SEQNR) >> SHIFT_SEQNR, (pkg->F3 & MASK_DATATYPE) >> SHIFT_DATATYPE); break; - + case HEADER_EOB: fprintf(stderr, "H0: 0x%04x --> EOB channel: %01d reply: %01d\n", pkg->H0, @@ -212,7 +212,7 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F2: 0x%04x --> data count\n", pkg->F2); fprintf(stderr, "F3: 0x%04x --> buffer number\n", pkg->F3); break; - + case HEADER_TRM: fprintf(stderr, "H0: 0x%04x --> TERM channel: %01d reply: %01d\n", pkg->H0, @@ -221,7 +221,7 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F0: 0x%04x --> checksum\n", pkg->F0); fprintf(stderr, "F1: 0x%04x --> statusbits channel\n", pkg->F1); fprintf(stderr, "F2: 0x%04x --> statusbits common\n", pkg->F2); - fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n", + fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n", pkg->F3, (pkg->F3 & MASK_SEQNR) >> SHIFT_SEQNR, (pkg->F3 & MASK_DATATYPE) >> SHIFT_DATATYPE); @@ -237,7 +237,7 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F2); fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F3); break; - + case HEADER_ACK: fprintf(stderr, "H0: 0x%04x --> ACK channel: %01d reply: %01d\n", pkg->H0, @@ -270,7 +270,7 @@ static void TRB_Package_dump(const TRB_Package* pkg) fprintf(stderr, "F2: 0x%04x --> ignore\n", pkg->F2); fprintf(stderr, "F2: 0x%04x --> ignore\n", pkg->F3); break; - + default: fprintf(stderr, "INVALID\n"); } @@ -280,12 +280,12 @@ static int trb_wait_tx_not_busy(uint8_t channel) { uint32_t tmp = 0; unsigned int timeout = 0; - + if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; return -1; } - + while (timeout < MAX_TIME_OUT) { read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); if ((tmp & MASK_TX_RUNNING) == 0) { @@ -293,7 +293,7 @@ static int trb_wait_tx_not_busy(uint8_t channel) } timeout++; } - + /* timeout occurred */ trb_errno = TRB_TX_BUSY; return -1; @@ -307,12 +307,12 @@ static int trb_init_transfer(uint8_t channel) trb_errno = TRB_INVALID_CHANNEL; return -1; } - + /* Check for TX not Busy, wait MAX_TIMEOUT */ if (trb_wait_tx_not_busy(3) == -1) { return -1; } - + /* Check receiver FIFO empty*/ read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), &tmp); @@ -321,7 +321,7 @@ static int trb_init_transfer(uint8_t channel) /* clear fifo ???*/ return -1; } - + /* No Errors */ return 0; } @@ -344,32 +344,32 @@ static int trb_fifo_read(uint8_t channel, static uint32_t dataBuffer[DATA_BUFFER_SIZE]; uint32_t *tmp = dataBuffer; int dma_size; - + TRB_Package package; int headerType = 0; uint32_t fifoBuffer = 0; unsigned int counter = 0; unsigned int dataCtr = 0; int packageCtr = -1; - unsigned int endPointCtr = 0; - - unsigned int timeout = 0; - + unsigned int endPointCtr = 0; + + unsigned int timeout = 0; + /* Determin FIFO-Address */ if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; return -1; } fifoBuffer = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4); - + /* Check for FIFO Ready */ timeout = 0; - + if (trb_dma == 1) { /* DMA-Readout */ do { - dma_size = - read32_from_FPGA_dma(fifoBuffer, tmp, DATA_BUFFER_SIZE); + dma_size = + read32_from_FPGA_dma(fifoBuffer, tmp, DATA_BUFFER_SIZE); } while ((dma_size == 0) && (++timeout < MAX_TIME_OUT)); } else { /* Standard */ @@ -377,12 +377,13 @@ static int trb_fifo_read(uint8_t channel, read32_from_FPGA(fifoBuffer, tmp); } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT)); } - - if (timeout >= MAX_TIME_OUT) { + + if (timeout >= MAX_TIME_OUT) { trb_errno = TRB_FIFO_TIMEOUT; + trb_fifo_flush(channel); return -1; } - + /* Read FIFO-Buffer, copy to User-Buffer */ while ((*tmp & MASK_FIFO_VALID) != 0) { if (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) @@ -403,16 +404,16 @@ static int trb_fifo_read(uint8_t channel, } } else { /* Data Word */ - if ((trb_lazy == 0) && + if ((trb_lazy == 0) && (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) != (counter - 1) % 2)) { /* Error: invalid sequence (not 0, 1, .), flush FIFO-BUFFER and exit */ trb_fifo_flush(channel); - trb_errno = TRB_FIFO_BROKEN_PACKAGE; + trb_errno = TRB_FIFO_BROKEN_PACKAGE; return -1; } } - + switch (counter) { case 0: package.H0 = *tmp; @@ -423,37 +424,37 @@ static int trb_fifo_read(uint8_t channel, case 2: package.F1 = *tmp; break; - case 3: + case 3: package.F2 = *tmp; break; - case 4: + case 4: package.F3 = *tmp; break; default: abort(); } - + /* DEBUG INFO */ if (trb_debug > 1) { fprintf(stderr, "FIFO_%03d: 0x%08x\n", packageCtr * 5 + counter, *tmp); } - + counter++; - + if (counter % 5 == 0) { /* End of Package, validate package and retrieve data */ - + /* Determine H0 HeaderType */ headerType = (package.H0 & MASK_HEADER_TYPE) >> SHIFT_HEADER_TYPE; - + /* DEBUG INFO */ if (trb_debug > 0) { TRB_Package_dump(&package); fprintf(stderr, "-------------------------------------------------\n"); } - - + + if (trb_lazy == 0) { /* First package: headerType must be HDR or TRM */ if (packageCtr == 0) { @@ -463,28 +464,28 @@ static int trb_fifo_read(uint8_t channel, return -1; } } - + /* Check Header H0 */ - if (((package.H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY + if (((package.H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY != 0x01) || - ((package.H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL + ((package.H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL != channel)) { - + /* Error Package inconsistencies, flush FIFO-BUFFER and exit */ trb_fifo_flush(channel); trb_errno = TRB_FIFO_HEADERS; return -1; } } - + /* Get Data F0 - F3 and store it in User-Data-Buffer if requested */ switch (mode) { - + case FIFO_MODE_NONE: break; - + case FIFO_MODE_REG_READ: - + switch (headerType) { case HEADER_HDR: if ((packageCtr - endPointCtr * 2) != 0) { @@ -497,10 +498,10 @@ static int trb_fifo_read(uint8_t channel, } else { trb_fifo_flush(channel); trb_errno = TRB_USER_BUFFER_OVF; - return -1; + return -1; } break; - + case HEADER_DAT: if ((packageCtr - endPointCtr * 2) != 1) { trb_fifo_flush(channel); @@ -508,7 +509,7 @@ static int trb_fifo_read(uint8_t channel, return -1; } if (dataCtr < dsize) { - data[dataCtr++] = (((uint32_t)package.F1 << 16) | + data[dataCtr++] = (((uint32_t)package.F1 << 16) | ((uint32_t)package.F2)); endPointCtr++; } else { @@ -517,23 +518,23 @@ static int trb_fifo_read(uint8_t channel, return -1; } break; - + case HEADER_TRM: break; - + default: trb_fifo_flush(channel); trb_errno = TRB_FIFO_INVALID_CONTENT; return -1; } - + break; - + case FIFO_MODE_REG_READ_MEM: { static uint32_t* lastHeader = NULL; static uint32_t memLen = 0; - + switch (headerType) { case HEADER_HDR: if (dataCtr < dsize) { @@ -547,28 +548,28 @@ static int trb_fifo_read(uint8_t channel, trb_fifo_flush(channel); trb_errno = TRB_USER_BUFFER_OVF; fprintf(stderr, "HEADER\n"); - return -1; + return -1; } break; - + case HEADER_DAT: if (dataCtr < dsize) { - data[dataCtr++] = (((uint32_t)package.F1 << 16) | + data[dataCtr++] = (((uint32_t)package.F1 << 16) | ((uint32_t)package.F2)); memLen++; } else { trb_fifo_flush(channel); trb_errno = TRB_USER_BUFFER_OVF; - return -1; + return -1; } break; - + case HEADER_TRM: if (lastHeader != NULL) { *lastHeader |= (memLen << 16); } break; - + default: trb_fifo_flush(channel); trb_errno = TRB_FIFO_INVALID_CONTENT; @@ -576,22 +577,22 @@ static int trb_fifo_read(uint8_t channel, } } break; - + case FIFO_MODE_REG_WRITE: if (headerType == HEADER_TRM) break; - + if (packageCtr > 1) { trb_fifo_flush(channel); trb_errno = TRB_INVALID_PKG_NUMBER; return -1; } break; - + case FIFO_MODE_IPU_DATA: { static unsigned int len = 0; unsigned int i; - + switch (headerType) { case HEADER_TRM: @@ -610,14 +611,14 @@ static int trb_fifo_read(uint8_t channel, } len = (unsigned int)package.F2; break; - + case HEADER_DAT: for (i = 0; (i < 2) && (dataCtr < len); i++) { if (dataCtr < dsize) { - data[dataCtr++] = i == 0 - ? (((uint32_t)package.F0 << 16) | + data[dataCtr++] = i == 0 + ? (((uint32_t)package.F0 << 16) | ((uint32_t)package.F1)) - : (((uint32_t)package.F2 << 16) | + : (((uint32_t)package.F2 << 16) | ((uint32_t)package.F3)); } else { trb_fifo_flush(channel); @@ -626,7 +627,7 @@ static int trb_fifo_read(uint8_t channel, } } break; - + default: trb_fifo_flush(channel); trb_errno = TRB_FIFO_INVALID_CONTENT; @@ -634,13 +635,13 @@ static int trb_fifo_read(uint8_t channel, } } break; - + case FIFO_MODE_UID: { static uint32_t uidLow; static uint32_t uidHigh; static uint32_t sourceAddress; - + switch (headerType) { case HEADER_HDR: if ((packageCtr - endPointCtr * 3) != 0) { @@ -650,16 +651,16 @@ static int trb_fifo_read(uint8_t channel, } sourceAddress = (uint32_t)package.F0; break; - + case HEADER_DAT: if ((packageCtr - endPointCtr * 3) == 1) { - uidHigh = (((uint32_t)package.F0 << 0) | + uidHigh = (((uint32_t)package.F0 << 0) | ((uint32_t)package.F1 << 16)); - uidLow = (((uint32_t)package.F2 << 0) | + uidLow = (((uint32_t)package.F2 << 0) | ((uint32_t)package.F3 << 16)); break; } - + if ((packageCtr - endPointCtr * 3) == 2) { if ((dataCtr + 3) < dsize) { /* store uid, endPoint and sourceAddress in userDataBuffer */ @@ -677,7 +678,7 @@ static int trb_fifo_read(uint8_t channel, } case HEADER_TRM: break; - + default: trb_fifo_flush(channel); trb_errno = TRB_FIFO_INVALID_CONTENT; @@ -685,78 +686,86 @@ static int trb_fifo_read(uint8_t channel, } } break; - + case FIFO_MODE_SET_ADDRESS: if (headerType == HEADER_TRM) break; - + if ((packageCtr == 1) && (headerType == HEADER_DAT)) { if (package.F0 != NET_ACKADDRESS) { trb_fifo_flush(channel); return -1; } } - + if (packageCtr > 1) { trb_fifo_flush(channel); trb_errno = TRB_INVALID_PKG_NUMBER; return -1; } - + dataCtr++; break; - + default: trb_fifo_flush(channel); trb_errno = TRB_FIFO_INVALID_MODE; return -1; } } - + /* Read Next Word */ if (trb_dma == 1) { tmp++; } else { + timeout = 0; + do { read32_from_FPGA(fifoBuffer, tmp); + } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT)); + if (timeout >= MAX_TIME_OUT) { + trb_errno = TRB_FIFO_TIMEOUT; + trb_fifo_flush(channel); + return -1; + } } } - - + + /* Copy StatusBits and Sequenze of TerminationPackage */ trb_term.status_common = package.F2; trb_term.status_channel = package.F1; trb_term.sequence = package.F3; trb_term.channel = channel; - + if (trb_lazy == 0) { /* Check whether last package is complete */ if ((packageCtr >= 0) && (counter != 5)) { trb_errno = TRB_FIFO_BROKEN_PACKAGE; return -1; } - + /* Check whether last package is a TERMINATION Package */ if (headerType != HEADER_TRM) { trb_errno = TRB_FIFO_INVALID_CONTENT; return -1; } - + /* Check StatusBits of TerminationPackage */ if ((trb_term.status_common == 0) && (trb_term.status_channel == 0)) { trb_errno = TRB_ENDPOINT_NOT_REACHED; return -1; } - + if ((trb_term.status_common & 0x0036) != 0) { trb_errno = TRB_STATUS_ERROR; return -1; } if ((channel == 3) && ((trb_term.status_channel & 0x0003) != 0)) { - trb_errno = TRB_STATUS_ERROR; + trb_errno = TRB_STATUS_ERROR; return -1; } } - + return dataCtr; } @@ -774,12 +783,12 @@ int trb_fifo_flush(uint8_t channel) trb_errno = TRB_INVALID_CHANNEL; return -1; } - + /* DEBUG INFO */ if (trb_debug > 1) { fprintf(stderr, "Flushing FIFO of channel# %d\n", channel); } - + fifoAddress = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4); do { read32_from_FPGA(fifoAddress, &tmp); @@ -799,19 +808,19 @@ int trb_register_read(uint16_t trb_address, unsigned int dsize) { int status = 0; - + trb_errno = TRB_NONE; /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -820,24 +829,24 @@ int trb_register_read(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_REGISTER_READ started.\n"); } - + status = trb_fifo_read(3, FIFO_MODE_REG_READ, data, dsize); - + if ((status > 0) && (status % 2 != 0)) { trb_errno = TRB_INVALID_PKG_NUMBER; - return -1; + return -1; } return status; } -int trb_register_read_mem(uint16_t trb_address, - uint16_t reg_address, +int trb_register_read_mem(uint16_t trb_address, + uint16_t reg_address, uint8_t option, uint16_t size, uint32_t *data, @@ -848,8 +857,8 @@ int trb_register_read_mem(uint16_t trb_address, const uint32_t *p = NULL; const uint32_t *end = NULL; - trb_errno = TRB_NONE; - + trb_errno = TRB_NONE; + /* check size and set reading-mode */ length = size & 0x7fff; if ((size == 0) || (size != length)) { @@ -857,17 +866,17 @@ int trb_register_read_mem(uint16_t trb_address, return -1; } length = length | (option == 0 ? 0x8000 : 0x0000); - + /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Tranfer done.\n"); } - + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -876,16 +885,16 @@ int trb_register_read_mem(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_READ_MEM); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_REGISTER_READ_MEM started.\n"); } - + status = trb_fifo_read(3, FIFO_MODE_REG_READ_MEM, data, dsize); - + if (status == -1) return status; - + /* Check size */ p = data; end = p + status; @@ -896,14 +905,14 @@ int trb_register_read_mem(uint16_t trb_address, trb_errno = TRB_READMEM_INVALID_SIZE; return -1; } - p += len + 1; + p += len + 1; } - - return status; + + return status; } int trb_register_write(uint16_t trb_address, - uint16_t reg_address, + uint16_t reg_address, uint32_t value) { trb_errno = TRB_NONE; @@ -911,8 +920,8 @@ int trb_register_write(uint16_t trb_address, /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); @@ -926,17 +935,17 @@ int trb_register_write(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, value & 0xffff); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_REGISTER_WRITE started.\n"); } - + return trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); } -int trb_register_write_mem(uint16_t trb_address, - uint16_t reg_address, +int trb_register_write_mem(uint16_t trb_address, + uint16_t reg_address, uint8_t option, const uint32_t *data, uint16_t dsize) @@ -945,7 +954,7 @@ int trb_register_write_mem(uint16_t trb_address, uint16_t i; trb_errno = TRB_NONE; - + /* check size and set write-mode */ config = dsize & 0x7fff; if ((dsize == 0) || (dsize != config)) { @@ -953,12 +962,12 @@ int trb_register_write_mem(uint16_t trb_address, return -1; } config = config | (option == 0 ? 0x8000 : 0x0000); - + /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); @@ -972,18 +981,18 @@ int trb_register_write_mem(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); for (i = 0; i < dsize; i++) { - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, (data[i] >> 16) & 0xffff); write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[i] & 0xffff); - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); } write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_REGISTER_WRITE_MEM started.\n"); } - + return trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0); } @@ -994,17 +1003,17 @@ int trb_read_uid(uint16_t trb_address, int status; trb_errno = TRB_NONE; - + /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1013,19 +1022,19 @@ int trb_read_uid(uint16_t trb_address, write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_READ_UNIQUE_ID started.\n"); } - + status = trb_fifo_read(3, FIFO_MODE_UID, (uint32_t*)uidBuffer, dsize); - + if ((status > 0) && (status % 4 != 0)) { trb_errno = TRB_INVALID_PKG_NUMBER; - return -1; + return -1; } - + return status; } @@ -1037,23 +1046,23 @@ int trb_set_address(uint64_t uid, int status; trb_errno = TRB_NONE; - + /* check for valid TRBnet address to be assigned */ if (trb_address >= 0xff00 ) { trb_errno = TRB_INVALID_ADDRESS; return -1; } - + /* Init transfer */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Build up package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1066,21 +1075,21 @@ int trb_set_address(uint64_t uid, write32_to_FPGA(CHANNEL_3_SENDER_DATA, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_NETADMINISTRATION); - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "CMD_SETADDRESS started.\n"); } - - status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0); + + status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0); if (status == -1) return -1; - + if (status != 2) { trb_errno = TRB_ENDPOINT_NOT_REACHED; return -1; } - - + + return 0; } @@ -1094,22 +1103,22 @@ int trb_ipu_data_read(uint8_t type, int status; trb_errno = TRB_NONE; - + if (data == NULL) return -1; - + /* Init transfer IPU Channel */ if (trb_init_transfer(1) == -1) { return -1; } - + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Prepare IPU channel */ - write32_to_FPGA(CHANNEL_1_SENDER_ERROR, (((uint32_t)trg_info << 24) | - ((uint32_t)trg_random << 16) | + write32_to_FPGA(CHANNEL_1_SENDER_ERROR, (((uint32_t)trg_info << 24) | + ((uint32_t)trg_random << 16) | ((uint32_t)trg_number) )); write32_to_FPGA(CHANNEL_1_SENDER_CONTROL, @@ -1119,9 +1128,9 @@ int trb_ipu_data_read(uint8_t type, if (trb_debug > 0) { fprintf(stderr, "CMD_IPU_DATA_READ started.\n"); } - + status = trb_fifo_read(1, FIFO_MODE_IPU_DATA, data, dsize); - + return status; } @@ -1134,35 +1143,35 @@ int trb_send_trigger(uint8_t type, int status; trb_errno = TRB_NONE; - + /* Init transfer trigger */ if (trb_init_transfer(0) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Prepare trigger channel */ - write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | - ((uint32_t)trg_random << 16) | + write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | + ((uint32_t)trg_random << 16) | ((uint32_t)trg_number) )); /* Send trigger */ write32_to_FPGA(CHANNEL_0_SENDER_CONTROL, SHORT_TRANSFER | (uint32_t)(type & 0x0f)); - + if (trb_debug > 0) { fprintf(stderr, "trigger started.\n"); } - + /* Check for replay packets (trigger) */ status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0); if (status == -1) return -1; - + return 0; } @@ -1175,25 +1184,25 @@ int trb_send_trigger_rich(uint8_t trg_input, int status; trb_errno = TRB_NONE; - + /* Init transfer slowcontrol */ if (trb_init_transfer(3) == -1) { return -1; - } - + } + /* Init transfer trigger */ if (trb_init_transfer(0) == -1) { return -1; - } - + } + /* DEBUG INFO */ if (trb_debug > 0) { fprintf(stderr, "Init_Transfer done.\n"); } - + /* Prepare trigger channel */ - write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | - ((uint32_t)trg_random << 16) | + write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) | + ((uint32_t)trg_random << 16) | ((uint32_t)trg_number) )); @@ -1202,29 +1211,29 @@ int trb_send_trigger_rich(uint8_t trg_input, write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); write32_to_FPGA(CHANNEL_3_SENDER_DATA, (0x8080 | (uint32_t)trg_input)); write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000dead); /*fake data is */ - write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000beef); /* discarded at ADCM */ + write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x0000beef); /* discarded at ADCM */ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000); - + /* Send both fake trigger and LVL1 information */ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE); write32_to_FPGA(CHANNEL_0_SENDER_CONTROL, SHORT_TRANSFER | (uint32_t)(type & 0x0f)); - + if (trb_debug > 0) { fprintf(stderr, "trigger started.\n"); } - + /* Check for replay packets (slowcontrol) */ status = trb_fifo_read(3, FIFO_MODE_NONE, NULL, 0); if (status == -1) { trb_fifo_flush(0); return -1; } - + /* Check for replay packets (trigger) */ status = trb_fifo_read(0, FIFO_MODE_NONE, NULL, 0); if (status == -1) return -1; - + return 0; } -- 2.43.0