From f879b12759806aabfe96bb77dd3e7f5972755d2b Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 3 Apr 2008 16:57:47 +0000
Subject: [PATCH] *** empty log message ***

---
 trb_net_std.vhd | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/trb_net_std.vhd b/trb_net_std.vhd
index ead1e06..618178c 100644
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@ -1,7 +1,7 @@
 -- std package
 library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
 USE IEEE.std_logic_UNSIGNED.ALL;
 
 package trb_net_std is
@@ -104,6 +104,9 @@ package trb_net_std is
   
   function get_bit_position  (arg : std_logic_vector)
     return integer;
+
+  function is_time_reached  (timer : integer; time : integer; period : integer)
+    return std_logic;
   
 end package trb_net_std;
 
@@ -167,7 +170,25 @@ package body trb_net_std is
       return 0;
   end get_bit_position;
 
-
+  function is_time_reached  (timer : integer; time : integer; period : integer)
+    return std_logic is
+    variable i : integer range 0 to 1 := 0;
+    variable t : std_logic_vector(16 downto 0) := conv_std_logic_vector(timer,17);
+    begin
+      i := 0;
+      if period = 10 then
+        case time is
+          when 640000 => if t(16) = '1' then i := 1; end if;
+          when 80000  => if t(13) = '1' then i := 1; end if;
+          when 10000  => if t(10) = '1' then i := 1; end if;
+          when 1200   => if t(7)  = '1' then i := 1; end if;
+          when others => if timer = time/period then i := 1; end if;
+        end case;
+      else
+        if timer = time/period then i := 1; end if;
+      end if;
+      if i = 1 then  return '1'; else return '0'; end if;
+    end is_time_reached;
   
 end package body trb_net_std;
 
-- 
2.43.0