From f87ccc2df79b8ea2c69691a290a7b03f79547bd8 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sat, 14 May 2022 08:11:08 +0200 Subject: [PATCH] small fixes --- media_interfaces/sync/tx_control_RS.vhd | 2 +- special/clockbox.vhd | 27 ++++----- special/phaserbox.vhd | 66 +++++++++++++++------ special/trb_net_i2cwire.vhd | 78 ++++++++++++------------- 4 files changed, 101 insertions(+), 72 deletions(-) diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index ef561ce..0aac139 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -225,7 +225,7 @@ begin --RAM empty ram_empty <= '1' when ((last_ram_write_addr = ram_read_addr) or (CLEAR = '1')) else '0'; - ram_afull <= '1' when (ram_fill_level >= 4) else '0'; + ram_afull <= '1' when (ram_fill_level >= 4) else '0'; -- INCREASE TO CHECK FOR trbflash BUG last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TXI); diff --git a/special/clockbox.vhd b/special/clockbox.vhd index 326c630..155a336 100644 --- a/special/clockbox.vhd +++ b/special/clockbox.vhd @@ -19,25 +19,26 @@ end entity clockbox; architecture clockbox_arch of clockbox is -- Components - component clockpoint is - port( - SAMPLE_CLK : in std_logic; - DATA_IN : in std_logic; - CLK_DATA : in std_logic; - DATA_OUT : out std_logic - ); + component clockpoint is + port( + SAMPLE_CLK : in std_logic; + DATA_IN : in std_logic; + CLK_DATA : in std_logic; + DATA_OUT : out std_logic + ); end component clockpoint; -- state machine signals -- Signals - attribute HGROUP : string; - attribute BBOX : string; - attribute HGROUP of clockbox_arch : architecture is "clockbox_group"; - attribute BBOX of clockbox_arch : architecture is "1,2"; - attribute syn_sharing : string; - attribute syn_sharing of clockbox_arch : architecture is "off"; +-- attribute HGROUP : string; +-- attribute BBOX : string; +-- attribute HGROUP of clockbox_arch : architecture is "clockbox_group"; +-- attribute BBOX of clockbox_arch : architecture is "1,2"; +-- attribute BBOX of clockbox_arch : architecture is "2,1"; +-- attribute syn_sharing : string; +-- attribute syn_sharing of clockbox_arch : architecture is "off"; attribute syn_hier : string; attribute syn_hier of clockbox_arch : architecture is "hard"; diff --git a/special/phaserbox.vhd b/special/phaserbox.vhd index 80a4a76..f2afec1 100644 --- a/special/phaserbox.vhd +++ b/special/phaserbox.vhd @@ -6,25 +6,30 @@ library work; entity phaserbox is port( - SAMPLE_CLK : in std_logic; -- auxiliary clock for sampling - RESET : in std_logic; + SAMPLE_CLK : in std_logic; -- auxiliary clock for sampling + RESET : in std_logic; -- input signals - TX_SYNC_IN : in std_logic; -- outgoing sync signal - TX_CLK_IN : in std_logic; -- TX clock - RX_SYNC_IN : in std_logic; -- incoming sync signal - RX_CLK_IN : in std_logic; -- RX clock - START_DELAY_IN : in std_logic; -- outgoing DLM komma - STOP_DELAY_IN : in std_logic; -- incoming DLM komma + TX_SYNC_IN : in std_logic; -- outgoing sync signal + TX_CLK_IN : in std_logic; -- TX clock + RX_SYNC_IN : in std_logic; -- incoming sync signal + RX_CLK_IN : in std_logic; -- RX clock + START_DELAY_IN : in std_logic; -- outgoing DLM komma + STOP_DELAY_IN : in std_logic; -- incoming DLM komma -- histogram - HISTO_CLK : in std_logic; - HISTO_START_IN : in std_logic; - HISTO_DONE_OUT : out std_logic; - HISTO_ADDR_IN : in std_logic_vector(9 downto 0); - HISTO_DATA_OUT : out std_logic_vector(17 downto 0); + HISTO_CLK : in std_logic; + HISTO_START_IN : in std_logic; + HISTO_DONE_OUT : out std_logic; + HISTO_ADDR_IN : in std_logic_vector(9 downto 0); + HISTO_DATA_OUT : out std_logic_vector(31 downto 0); + HISTO_READ_IN : in std_logic; + HISTO_WRITE_IN : in std_logic; + HISTO_ACK_OUT : out std_logic; + HISTO_NACK_OUT : out std_logic; + HISTO_UNKNOWN_OUT : out std_logic; -- - COARSE_DELAY_OUT : out std_logic_vector(31 downto 0); + COARSE_DELAY_OUT : out std_logic_vector(31 downto 0); -- - DEBUG_OUT : out std_logic_vector(15 downto 0) + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity phaserbox; @@ -105,8 +110,13 @@ architecture phaserbox_arch of phaserbox is signal cal_phase_q : std_logic; -- OBSELETE signal toggle_q : std_logic; -- OBSELETE signal coarse_delay_i : std_logic_vector(31 downto 0); + signal ack_delay : std_logic_vector(2 downto 0); + signal ack_delay_x : std_logic; signal debug : std_logic_vector(15 downto 0); + signal histo_data_i : std_logic_vector(31 downto 0); + signal histo_done_i : std_logic; + attribute HGROUP : string; -- attribute BBOX : string; attribute HGROUP of phaserbox_arch : architecture is "phaserbox_group"; @@ -173,12 +183,25 @@ begin FSM_ACTIVE_OUT => fsm_active_i, FSM_CE_OUT => fsm_ce_i, FSM_RST_OUT => fsm_rst_i, - FSM_DONE_OUT => HISTO_DONE_OUT, + FSM_DONE_OUT => histo_done_i, RD_CLK => HISTO_CLK, RD_ADDRESS_IN => HISTO_ADDR_IN, - RD_DATA_OUT => HISTO_DATA_OUT + RD_DATA_OUT => histo_data_i(17 downto 0) ); + histo_data_i(31) <= histo_done_i; + histo_data_i(30 downto 18) <= (others => '0'); + + -- simple readout + ack_delay_x <= HISTO_READ_IN or HISTO_WRITE_IN; + + THE_ACK_DELAY_PROC: process( HISTO_CLK ) + begin + if( rising_edge(HISTO_CLK) ) then + ack_delay <= ack_delay(1 downto 0) & ack_delay_x; + end if; + end process THE_ACK_DELAY_PROC; + -- DEBUG debug(15 downto 6) <= (others => '0'); debug(5) <= start_rx_sync_i; @@ -189,7 +212,12 @@ begin debug(0) <= stretched_tx_sync_i; -- Outputs - COARSE_DELAY_OUT <= cal_phase_q & coarse_delay_i(30 downto 0); - DEBUG_OUT <= debug; + COARSE_DELAY_OUT <= cal_phase_q & coarse_delay_i(30 downto 0); -- workaround + HISTO_DONE_OUT <= histo_done_i; + HISTO_DATA_OUT <= histo_data_i; + HISTO_ACK_OUT <= ack_delay(2); + HISTO_NACK_OUT <= '0'; + HISTO_UNKNOWN_OUT <= '0'; + DEBUG_OUT <= debug; end architecture; diff --git a/special/trb_net_i2cwire.vhd b/special/trb_net_i2cwire.vhd index 7bf8da6..264de3f 100644 --- a/special/trb_net_i2cwire.vhd +++ b/special/trb_net_i2cwire.vhd @@ -16,15 +16,15 @@ entity trb_net_i2cwire is RESET : in std_logic; READOUT_ENABLE_IN : in std_logic := '1'; --connection to I2C interface - SCL_INOUT : inout std_logic; - SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + SDA_INOUT : inout std_logic; --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT : out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT : out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) ); end trb_net_i2cwire; @@ -36,18 +36,18 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is signal CURRENT_STATE, NEXT_STATE: FSM_STATES; -- Signals - constant MAX_COUNTER : integer := 2**28-1; - signal timecounter : integer range 0 to MAX_COUNTER; + constant MAX_COUNTER : integer := 2**28-1; + signal timecounter : integer range 0 to MAX_COUNTER; signal rst_tc_x : std_logic; - constant IDLE_PERIOD : integer := 1000; -- unit [ns] + constant IDLE_PERIOD : integer := 1000; -- unit [ns] constant READOUT_PERIOD : integer := 1000000000; -- unit [ns] - constant I2C_CYCLE : integer := 5000; -- unit [ns] + constant I2C_CYCLE : integer := 5000; -- unit [ns] constant I2C_PERIOD : integer := (((I2C_CYCLE / CLK_PERIOD) - 2)/8); signal ram_we_x : std_logic; signal ram_we : std_logic; - signal temp_we_x : std_logic; - signal temp_we : std_logic; + signal temp_we_x : std_logic; + signal temp_we : std_logic; signal i2c_go_x : std_logic; signal i2c_go : std_logic; @@ -55,48 +55,48 @@ architecture trb_net_i2cwire_arch of trb_net_i2cwire is signal i2c_action_int : std_logic; signal i2c_word_int : std_logic; signal i2c_addr_int : std_logic_vector(7 downto 0); - signal i2c_cmd_int : std_logic_vector(7 downto 0); + signal i2c_cmd_int : std_logic_vector(7 downto 0); signal i2c_dw_int : std_logic_vector(15 downto 0); signal i2c_dr_int : std_logic_vector(15 downto 0); signal i2c_status_int : std_logic_vector(7 downto 0); signal i2c_busy_int : std_logic; signal i2c_done_int : std_logic; - signal i2c_bsm_int : std_logic_vector(4 downto 0); - signal valid_int : std_logic; + signal i2c_bsm_int : std_logic_vector(4 downto 0); + signal valid_int : std_logic; signal addr_int : std_logic_vector(2 downto 0); signal id_int : std_logic_vector(63 downto 0); signal temp_int : std_logic_vector(11 downto 0); - signal sda_drv : std_logic; - signal scl_drv : std_logic; + signal sda_drv : std_logic; + signal scl_drv : std_logic; -- Components component i2c_slim is port( - CLOCK : in std_logic; - RESET : in std_logic; + CLOCK : in std_logic; + RESET : in std_logic; -- I2C command / setup - I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions - ACTION_IN : in std_logic; -- '0' -> write, '1' -> read - WORD_IN : in std_logic; -- '0' -> byte, '1' -> word - I2C_SPEED_IN : in std_logic_vector(5 downto 0); -- speed adjustment (to be defined) - I2C_ADDR_IN : in std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN : in std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte) - I2C_DW_IN : in std_logic_vector(15 downto 0); -- data word for write command - I2C_DR_OUT : out std_logic_vector(15 downto 0); -- data word from read command - STATUS_OUT : out std_logic_vector(7 downto 0); -- status and error bits - VALID_OUT : out std_logic; - I2C_BUSY_OUT : out std_logic; - I2C_DONE_OUT : out std_logic; + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + WORD_IN : in std_logic; -- '0' -> byte, '1' -> word + I2C_SPEED_IN : in std_logic_vector(5 downto 0); -- speed adjustment (to be defined) + I2C_ADDR_IN : in std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector(15 downto 0); -- data word for write command + I2C_DR_OUT : out std_logic_vector(15 downto 0); -- data word from read command + STATUS_OUT : out std_logic_vector(7 downto 0); -- status and error bits + VALID_OUT : out std_logic; + I2C_BUSY_OUT : out std_logic; + I2C_DONE_OUT : out std_logic; -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; -- Debug - BSM_OUT : out std_logic_vector(4 downto 0) + BSM_OUT : out std_logic_vector(4 downto 0) ); end component i2c_slim; @@ -117,7 +117,7 @@ begin else CURRENT_STATE <= NEXT_STATE; ram_we <= ram_we_x; - temp_we <= temp_we_x; + temp_we <= temp_we_x; i2c_go <= i2c_go_x; end if; end if; -- 2.43.0