From f96c9767a0e366e2541daba304866c1646f91c89 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 1 Apr 2010 16:02:45 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/fifo/fifo_var_oreg.vhd | 1 - lattice/ecp2m/lattice_ecp2m_fifo.vhd | 78 +++++++++++++++++ special/handler_data.vhd | 100 ++++++++++++++++++---- special/handler_trigger_and_data.vhd | 24 ++++-- trb_net16_endpoint_hades_full_handler.vhd | 83 +++++++++++++++--- trb_net_components.vhd | 39 +++++---- 6 files changed, 273 insertions(+), 52 deletions(-) diff --git a/lattice/ecp2m/fifo/fifo_var_oreg.vhd b/lattice/ecp2m/fifo/fifo_var_oreg.vhd index 5cd3cd0..0aaebcc 100644 --- a/lattice/ecp2m/fifo/fifo_var_oreg.vhd +++ b/lattice/ecp2m/fifo/fifo_var_oreg.vhd @@ -31,7 +31,6 @@ architecture fifo_var_oreg_arch of fifo_var_oreg is begin - assert FIFO_WIDTH=36 report "Selected data buffer size not implemented" severity error; assert (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 15 and FIFO_WIDTH = 36) or (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 11 and FIFO_WIDTH = 18) report "Selected data buffer size not implemented" severity error; diff --git a/lattice/ecp2m/lattice_ecp2m_fifo.vhd b/lattice/ecp2m/lattice_ecp2m_fifo.vhd index 2061203..0d2a715 100644 --- a/lattice/ecp2m/lattice_ecp2m_fifo.vhd +++ b/lattice/ecp2m/lattice_ecp2m_fifo.vhd @@ -169,4 +169,82 @@ package lattice_ecp2m_fifo is end component; + component fifo_18x256_oreg + port ( + Data : in std_logic_vector(17 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_18x512_oreg + port ( + Data : in std_logic_vector(17 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(8 downto 0); + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_18x1k_oreg + port ( + Data : in std_logic_vector(17 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(9 downto 0); + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(10 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + component fifo_18x2k_oreg + port ( + Data : in std_logic_vector(17 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(10 downto 0); + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(11 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); + end component; + + + + + + + + + end package; \ No newline at end of file diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 0d1e4e2..140686b 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -7,6 +7,8 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.lattice_ecp2m_fifo.all; + + entity handler_data is generic( DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; @@ -81,6 +83,11 @@ end entity; -- 20 : buffer idle -- 21 : buffer busy -- 22 : buffer waiting +-- 23 : +-- 24 : length fifo empty +-- 25 : length fifo almost full +-- 26 : length fifo full +-- 27 : length fifo write --------------------------------------------------------------------------- @@ -103,7 +110,7 @@ architecture handler_data_arch of handler_data is signal header_buffer_data_in : std_logic_vector(36-1 downto 0); signal header_buffer_data_out : std_logic_vector(36-1 downto 0); - signal header_buffer_filllevel : std_logic_vector(DATA_BUFFER_DEPTH downto 0); + signal header_buffer_filllevel : std_logic_vector(HEADER_BUFFER_DEPTH downto 0); signal header_buffer_full : std_logic; signal header_buffer_empty : std_logic; signal header_buffer_almost_full : std_logic; @@ -112,6 +119,7 @@ architecture handler_data_arch of handler_data is signal lvl1_busy_release_i : std_logic; signal lvl1_statusbits_i : std_logic_vector(31 downto 0); + signal got_busy_release : std_logic_vector(DATA_INTERFACE_NUMBER downto 0); signal data_counter : cnt16_DAT_t; signal buffer_state_bits : bits3_t; signal lvl1_state_bits : std_logic_vector(2 downto 0); @@ -119,7 +127,13 @@ architecture handler_data_arch of handler_data is signal current_buffer_state : buffer_state_arr_t; signal current_lvl1_state : lvl1_state_t; + signal length_buffer_data_in : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0); + signal length_buffer_data_out : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0); signal length_buffer_write : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal length_buffer_empty : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal length_buffer_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal length_buffer_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + begin @@ -127,16 +141,12 @@ begin assert HEADER_BUFFER_FULL_THRESH < 2**HEADER_BUFFER_DEPTH-2 report "Header buffer threshold too high" severity error; --------------------------------------------------------------------------- --- FEE I/O +-- FEE & IPU I/O --------------------------------------------------------------------------- FEE_DATA_ALMOST_FULL_OUT <= data_buffer_almost_full; ---------------------------------------------------------------------------- --- IPU I/O ---------------------------------------------------------------------------- IPU_HDR_DATA_EMPTY_OUT <= header_buffer_empty; - IPU_HDR_DATA_OUT <= header_buffer_data_out; - + IPU_HDR_DATA_OUT <= header_buffer_data_out(31 downto 0); IPU_DATA_EMPTY_OUT <= data_buffer_empty; @@ -148,7 +158,7 @@ begin data_buffer_data_in((i+1)*data_width-1 downto i*data_width) <= LVL1_TRG_NUMBER_IN(3 downto 0) & FEE_DATA_IN((i+1)*DATA_BUFFER_WIDTH-1 downto i*DATA_BUFFER_WIDTH); - IPU_DATA_OUT(i*data_width+DATA_BUFFER_WIDTH-1 downto i*data_width) + IPU_DATA_OUT((i+1)*DATA_BUFFER_WIDTH-1 downto i*DATA_BUFFER_WIDTH) <= data_buffer_data_out(i*data_width+DATA_BUFFER_WIDTH-1 downto i*data_width); IPU_DATA_FLAGS_OUT(i*4+3 downto i*4) @@ -174,7 +184,7 @@ begin WrEn => FEE_DATA_WRITE_IN(i), RdEn => IPU_DATA_READ_IN(i), Reset => RESET, - AmFullThresh => DATA_BUFFER_FULL_THRESH, + AmFullThresh => std_logic_vector(to_unsigned(DATA_BUFFER_FULL_THRESH, DATA_BUFFER_DEPTH)), Q => data_buffer_data_out(i*36+35 downto i*36), WCNT => data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)), Empty => data_buffer_empty(i), @@ -198,7 +208,7 @@ begin WrEn => header_buffer_write, RdEn => IPU_HDR_DATA_READ_IN, Reset => RESET, - AmFullThresh => HEADER_BUFFER_FULL_THRESH, + AmFullThresh => std_logic_vector(to_unsigned(HEADER_BUFFER_FULL_THRESH, HEADER_BUFFER_DEPTH)), Q => header_buffer_data_out, WCNT => header_buffer_filllevel, Empty => header_buffer_empty, @@ -210,7 +220,26 @@ begin --------------------------------------------------------------------------- -- Length FIFO --------------------------------------------------------------------------- --- THE_LENGTH_FIFO : + gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + THE_LENGTH_FIFO : fifo_var_oreg + generic map( + FIFO_WIDTH => 18, + FIFO_DEPTH => HEADER_BUFFER_DEPTH + ) + port map( + Data => length_buffer_data_in(i*18+17 downto i*18), + Clock => CLOCK, + WrEn => length_buffer_write(i), + RdEn => IPU_HDR_DATA_READ_IN, + Reset => RESET, + AmFullThresh => std_logic_vector(to_unsigned(HEADER_BUFFER_FULL_THRESH, HEADER_BUFFER_DEPTH)), + Q => length_buffer_data_out(i*18+17 downto i*18), + WCNT => open, + Empty => length_buffer_empty(i), + Full => length_buffer_full(i), + AlmostFull => length_buffer_almost_full(i) + ); + end generate; --------------------------------------------------------------------------- @@ -228,13 +257,13 @@ begin case current_buffer_state(i) is when IDLE => buffer_state_bits(i) <= "001"; - data_counter(i) <= 0; + data_counter(i) <= to_unsigned(0,16); if LVL1_VALID_TRIGGER_IN = '1' then current_buffer_state(i) <= BUSY; end if; when BUSY => - buffer_state_bits(i) <= "100"; + buffer_state_bits(i) <= "010"; if FEE_DATA_WRITE_IN(i) = '1' then data_counter(i) <= data_counter(i) + to_unsigned(1,1); elsif FEE_DATA_FINISHED_IN(i) = '1' then @@ -243,7 +272,7 @@ begin end if; when WAITING => - buffer_state_bits(i) <= "010"; + buffer_state_bits(i) <= "100"; if lvl1_busy_release_i = '1' then current_buffer_state(i) <= IDLE; end if; @@ -263,6 +292,7 @@ begin if RESET = '1' then current_lvl1_state <= IDLE; else + LVL1_TRG_RELEASE_OUT <= '0'; case current_lvl1_state is when IDLE => lvl1_state_bits <= "001"; @@ -272,6 +302,10 @@ begin when BUSY_RELEASE => lvl1_state_bits <= "100"; + if or_all(got_busy_release) = '1' then + LVL1_TRG_RELEASE_OUT <= '1'; + current_lvl1_state <= IDLE; + end if; end case; end if; @@ -279,6 +313,34 @@ begin end process; + proc_data_handler_busy : process(CLOCK) + begin + if rising_edge(CLOCK) then + if RESET = '1' or current_lvl1_state = IDLE then + got_busy_release <= (others => '0'); + else + got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0) + <= got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0) or FEE_DATA_FINISHED_IN; + if TRG_RELEASE_AFTER_DATA = c_NO then + got_busy_release(DATA_INTERFACE_NUMBER) <= '1'; + elsif or_all(got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)) = '1' and + (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' then + got_busy_release(DATA_INTERFACE_NUMBER) <= '1'; + end if; + end if; + end if; + end process; + + + +--------------------------------------------------------------------------- +-- Generate Statusbits +--------------------------------------------------------------------------- + LVL1_STATUSBITS_OUT <= (others => '0'); + + + + --------------------------------------------------------------------------- -- Make Status Registers --------------------------------------------------------------------------- @@ -300,6 +362,14 @@ begin STAT_DATA_BUFFER_LEVEL(i*32+22 downto i*32+20) <= buffer_state_bits(i); + + STAT_DATA_BUFFER_LEVEL(i*32+26 downto i*32+24) + <= length_buffer_full(i) & length_buffer_almost_full(i) & length_buffer_empty(i); + + STAT_DATA_BUFFER_LEVEL(i*32+27) + <= length_buffer_write(i); + + end if; end process; end generate; @@ -320,7 +390,7 @@ begin <= header_buffer_write; STAT_HEADER_BUFFER_LEVEL(22 downto 20) - <= lvl1_state_bits(i); + <= lvl1_state_bits; end if; end process; diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index f755a97..177a0b7 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -57,6 +57,8 @@ entity handler_trigger_and_data is FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); --Status Registers + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); STATUS_OUT : out std_logic_vector(127 downto 0); --Debug @@ -82,7 +84,6 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is signal fee_trg_info : std_logic_vector(23 downto 0); signal fee_trg_code : std_logic_vector(7 downto 0); signal fee_trg_number : std_logic_vector(15 downto 0); - signal fee_trg_release : std_logic; signal fee_trg_statusbits : std_logic_vector(31 downto 0); signal dat_lvl1_release : std_logic; @@ -97,6 +98,8 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is signal ipu_header_empty : std_logic; signal ipu_header_read : std_logic; + signal fee_trg_release : std_logic_vector(DATA_INTERFACE_NUMBER downto 0); + begin @@ -105,21 +108,24 @@ begin ----------------------------------------------------------------------- proc_trg_release : process(CLOCK) - variable tmp_release : std_logic; variable tmp_statusbits : std_logic_vector(31 downto 0); begin if rising_edge(CLOCK) then if RESET = '1' or LVL1_VALID_TRIGGER_IN = '0' then fee_trg_statusbits <= (others => '0'); - fee_trg_release <= '0'; + fee_trg_release <= (others => '0'); else - tmp_release := fee_trg_release or dat_lvl1_release; - tmp_statusbits := fee_trg_statusbits or dat_lvl1_statusbits; + fee_trg_release <= fee_trg_release or (dat_lvl1_release & FEE_TRG_RELEASE_IN); + + tmp_statusbits := fee_trg_statusbits; for i in 0 to DATA_INTERFACE_NUMBER-1 loop - tmp_release := tmp_release or FEE_TRG_RELEASE_IN(i); - tmp_statusbits := tmp_statusbits or FEE_TRG_STATUSBITS_IN(32*i+31 downto 32*i); + if FEE_TRG_RELEASE_IN(i) = '1' then + tmp_statusbits := tmp_statusbits or FEE_TRG_STATUSBITS_IN(32*i+31 downto 32*i); + end if; end loop; - fee_trg_release <= tmp_release; + if dat_lvl1_release = '1' then + tmp_statusbits := tmp_statusbits or dat_lvl1_statusbits; + end if; fee_trg_statusbits <= tmp_statusbits; end if; end if; @@ -211,7 +217,7 @@ begin ----------------------------------------------------------------------- -- Connect Outputs ----------------------------------------------------------------------- - LVL1_TRG_RELEASE_OUT <= fee_trg_release; + LVL1_TRG_RELEASE_OUT <= and_all(fee_trg_release); LVL1_ERROR_PATTERN_OUT <= fee_trg_statusbits; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 2f5c4cf..c465a27 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -183,7 +183,17 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal time_ticks_i : std_logic_vector ( 1 downto 0); signal stat_handler_i : std_logic_vector (127 downto 0); + signal stat_data_buffer_level : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0); + signal stat_header_buffer_level: std_logic_vector (31 downto 0); + signal dbuf_read_enable : std_logic; + signal dbuf_addr : std_logic_vector (3 downto 0); + signal dbuf_data_in : std_logic_vector (31 downto 0); + signal dbuf_dataready : std_logic; + signal dbuf_unknown_addr : std_logic; + + signal tbuf_dataready : std_logic; + signal tbuf_read_enable : std_logic; begin --------------------------------------------------------------------------- @@ -300,9 +310,9 @@ begin THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 1, - PORT_ADDRESSES => (0 => x"8000", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, others => 0) + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, others => 0) ) port map( CLK => CLK, @@ -328,7 +338,30 @@ begin BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, - BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN + BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN, + + BUS_READ_ENABLE_OUT(1) => dbuf_read_enable, + BUS_WRITE_ENABLE_OUT(1) => open, + BUS_DATA_OUT(63 downto 32) => open, + BUS_ADDR_OUT(19 downto 16) => dbuf_addr, + BUS_ADDR_OUT(31 downto 20) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(63 downto 32) => dbuf_data_in, + BUS_DATAREADY_IN(1) => dbuf_dataready, + BUS_WRITE_ACK_IN(1) => '0', + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, + + BUS_READ_ENABLE_OUT(2) => tbuf_read_enable, + BUS_WRITE_ENABLE_OUT(2) => open, + BUS_DATA_OUT(95 downto 64) => open, + BUS_ADDR_OUT(47 downto 32) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, + BUS_DATAREADY_IN(2) => tbuf_dataready, + BUS_WRITE_ACK_IN(2) => '0', + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0' ); --------------------------------------------------------------------------- @@ -337,13 +370,13 @@ begin THE_HANDLER_TRIGGER_DATA : handler_trigger_and_data generic map( - DATA_INTERFACE_NUMBER => DATA_INTERFACE_NUMBER, - DATA_BUFFER_DEPTH => DATA_BUFFER_DEPTH, - DATA_BUFFER_WIDTH => DATA_BUFFER_WIDTH, - DATA_BUFFER_FULL_THRESH => DATA_BUFFER_FULL_THRESH, - TRG_RELEASE_AFTER_DATA => TRG_RELEASE_AFTER_DATA, - HEADER_BUFFER_DEPTH => HEADER_BUFFER_DEPTH, - HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH + DATA_INTERFACE_NUMBER => DATA_INTERFACE_NUMBER, + DATA_BUFFER_DEPTH => DATA_BUFFER_DEPTH, + DATA_BUFFER_WIDTH => DATA_BUFFER_WIDTH, + DATA_BUFFER_FULL_THRESH => DATA_BUFFER_FULL_THRESH, + TRG_RELEASE_AFTER_DATA => TRG_RELEASE_AFTER_DATA, + HEADER_BUFFER_DEPTH => HEADER_BUFFER_DEPTH, + HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH ) port map( CLOCK => CLK, @@ -381,6 +414,8 @@ begin FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT, --Status Registers + STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level, + STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, STATUS_OUT => stat_handler_i, --Debug @@ -391,6 +426,32 @@ begin lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i; + +--------------------------------------------------------------------------- +-- Connect Status Registers +--------------------------------------------------------------------------- + proc_buf_status : process(CLK) + variable tmp : integer range 0 to DATA_INTERFACE_NUMBER-1; + begin + if rising_edge(CLK) then + dbuf_unknown_addr <= '0'; + dbuf_dataready <= '0'; + tbuf_dataready <= tbuf_read_enable; + if dbuf_read_enable = '1' then + tmp := to_integer(unsigned(dbuf_addr)); + if tmp < DATA_INTERFACE_NUMBER then + dbuf_data_in <= stat_data_buffer_level(tmp*32+31 downto tmp*32); + dbuf_dataready <= '1'; + else + dbuf_data_in <= (others => '0'); + dbuf_unknown_addr <= '1'; + end if; + end if; + end if; + end process; + + + --------------------------------------------------------------------------- -- Connect I/O Ports --------------------------------------------------------------------------- diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 723a53b..6f41457 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -447,15 +447,11 @@ package trb_net_components is --Configure data handler DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8; - --RegIO Bus Handler - PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 1; - PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); - PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8 ); port( @@ -510,16 +506,16 @@ package trb_net_components is REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); --internal data port - BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); - BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); - BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_DATA_IN : in std_logic_vector(PORT_NUMBER*32-1 downto 0) := (others => '0'); - BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); - BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0) := (others => '0'); + BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic; + BUS_WRITE_ENABLE_OUT : out std_logic; + BUS_TIMEOUT_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + BUS_DATAREADY_IN : in std_logic := '0'; + BUS_WRITE_ACK_IN : in std_logic := '0'; + BUS_NO_MORE_DATA_IN : in std_logic := '0'; + BUS_UNKNOWN_ADDR_IN : in std_logic := '0'; --Onewire ONEWIRE_INOUT : inout std_logic; --temperature sensor ONEWIRE_MONITOR_IN : in std_logic := '0'; @@ -795,6 +791,10 @@ package trb_net_components is IPU_HDR_DATA_READ_IN : in std_logic; IPU_HDR_DATA_EMPTY_OUT : out std_logic; + --Status + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + --Debug DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -896,6 +896,8 @@ package trb_net_components is --Status Registers STATUS_OUT : out std_logic_vector(127 downto 0); + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); --Debug DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); @@ -905,6 +907,11 @@ package trb_net_components is end component; + + + + + component trb_net16_ibuf is generic ( DEPTH : integer range 0 to 7 := c_FIFO_BRAM; -- 2.43.0