From fa45d6634fafcedddb4d0c245badbe4551c3ab0e Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 18 Jan 2011 09:47:47 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/dll_in100_out25.lpc | 39 + lattice/ecp2m/dll_in100_out25.vhd | 133 + lattice/scm/fifo_72x512.ipx | 9 + lattice/scm/fifo_72x512.lpc | 48 + lattice/scm/fifo_72x512.vhd | 226 + .../scm/lattice_scm_fifo_16bit_dualport.ipx | 9 + .../scm/lattice_scm_fifo_16bit_dualport.lpc | 22 +- .../scm/lattice_scm_fifo_16bit_dualport.srp | 10 +- .../scm/lattice_scm_fifo_16bit_dualport.sym | Bin 546 -> 546 bytes .../scm/lattice_scm_fifo_16bit_dualport.vhd | 51 +- .../lattice_scm_fifo_16bit_dualport_tmpl.vhd | 6 +- lattice/scm/lattice_scm_fifo_18x1k.ipx | 9 + lattice/scm/pll_in100_out150.ipx | 8 + lattice/scm/pll_in100_out150.lpc | 58 + lattice/scm/pll_in100_out150.vhd | 167 + lattice/scm/pll_in100_out50_250.ipx | 8 + lattice/scm/pll_in100_out50_250.lpc | 58 + lattice/scm/pll_in100_out50_250.vhd | 167 + .../scm/trb_net_fifo_16bit_bram_dualport.vhd | 37 +- .../scm_sfp/serdes_gbe_0_100_ext.ipx | 11 + .../scm_sfp/serdes_gbe_0_100_ext.lpc | 61 + .../scm_sfp/serdes_gbe_0_100_ext.txt | 70 + .../scm_sfp/serdes_gbe_0_100_ext.vhd | 2392 +++++++ .../trb_net16_med_scm_sfp_gbe.vhd | 112 +- special/trb_net_bridge_pcie_apl.vhd | 399 ++ special/trb_net_bridge_pcie_endpoint.vhd | 541 ++ trb_net16_regIO.vhd | 9 - trb_net_components.vhd | 6005 +++++++++-------- trb_net_onewire.vhd | 1 - 29 files changed, 7605 insertions(+), 3061 deletions(-) create mode 100644 lattice/ecp2m/dll_in100_out25.lpc create mode 100644 lattice/ecp2m/dll_in100_out25.vhd create mode 100644 lattice/scm/fifo_72x512.ipx create mode 100644 lattice/scm/fifo_72x512.lpc create mode 100644 lattice/scm/fifo_72x512.vhd create mode 100644 lattice/scm/lattice_scm_fifo_16bit_dualport.ipx create mode 100644 lattice/scm/lattice_scm_fifo_18x1k.ipx create mode 100644 lattice/scm/pll_in100_out150.ipx create mode 100644 lattice/scm/pll_in100_out150.lpc create mode 100644 lattice/scm/pll_in100_out150.vhd create mode 100644 lattice/scm/pll_in100_out50_250.ipx create mode 100644 lattice/scm/pll_in100_out50_250.lpc create mode 100644 lattice/scm/pll_in100_out50_250.vhd create mode 100644 media_interfaces/scm_sfp/serdes_gbe_0_100_ext.ipx create mode 100644 media_interfaces/scm_sfp/serdes_gbe_0_100_ext.lpc create mode 100644 media_interfaces/scm_sfp/serdes_gbe_0_100_ext.txt create mode 100644 media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd create mode 100644 special/trb_net_bridge_pcie_apl.vhd create mode 100644 special/trb_net_bridge_pcie_endpoint.vhd diff --git a/lattice/ecp2m/dll_in100_out25.lpc b/lattice/ecp2m/dll_in100_out25.lpc new file mode 100644 index 0000000..165fcec --- /dev/null +++ b/lattice/ecp2m/dll_in100_out25.lpc @@ -0,0 +1,39 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F900I +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=IND +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DLL +CoreRevision=3.5 +ModuleName=dll_in100_out25 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=08/19/2010 +Time=13:33:44 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +dlltype=Clock Injection Delay Removal +fin=100 +clkos_div=4 +clkos_ph=0 +Mode=CLKOP +Freq=CLKI +Smiports=0 +RSTNport=0 +reset_en=0 +DCNTL=0 diff --git a/lattice/ecp2m/dll_in100_out25.vhd b/lattice/ecp2m/dll_in100_out25.vhd new file mode 100644 index 0000000..73f39ca --- /dev/null +++ b/lattice/ecp2m/dll_in100_out25.vhd @@ -0,0 +1,133 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) +-- Module Version: 3.5 +--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n dll_in100_out25 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dll -dll_type cid -fin 100 -clkos_div 4 -fb_mode 0 -e + +-- Thu Aug 19 13:33:44 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity dll_in100_out25 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of dll_in100_out25 : entity is true; +end dll_in100_out25; + +architecture Structure of dll_in100_out25 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal clkos_t: std_logic; + signal scuba_vhi: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + -- local component declarations + component CIDDLLA + -- synopsys translate_off + generic (ALU_INIT_CNTVAL : in Integer; + ALU_UNLOCK_CNT : in Integer; ALU_LOCK_CNT : in Integer; + GSR : in String; CLKOS_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FPHASE : in Integer; + CLKOS_PHASE : in Integer; CLKOP_PHASE : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; + RSTN: in std_logic; ALUHOLD: in std_logic; + SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; LOCK: out std_logic; + SMIRDATA: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute GSR : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute ALU_INIT_CNTVAL : string; + attribute ALU_UNLOCK_CNT : string; + attribute ALU_LOCK_CNT : string; + attribute CLKI_DIV : string; + attribute CLKOS_DIV : string; + attribute CLKOS_FPHASE : string; + attribute CLKOS_PHASE : string; + attribute CLKOP_PHASE : string; + attribute FREQUENCY_PIN_CLKOS of dll_in100_out25_0_0 : label is "25.000000"; + attribute FREQUENCY_PIN_CLKOP of dll_in100_out25_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKI of dll_in100_out25_0_0 : label is "100.000000"; + attribute GSR of dll_in100_out25_0_0 : label is "DISABLED"; + attribute CLKFB_PDEL of dll_in100_out25_0_0 : label is "DEL0"; + attribute CLKI_PDEL of dll_in100_out25_0_0 : label is "DEL0"; + attribute ALU_INIT_CNTVAL of dll_in100_out25_0_0 : label is "0"; + attribute ALU_UNLOCK_CNT of dll_in100_out25_0_0 : label is "3"; + attribute ALU_LOCK_CNT of dll_in100_out25_0_0 : label is "3"; + attribute CLKI_DIV of dll_in100_out25_0_0 : label is "1"; + attribute CLKOS_DIV of dll_in100_out25_0_0 : label is "4"; + attribute CLKOS_FPHASE of dll_in100_out25_0_0 : label is "0"; + attribute CLKOS_PHASE of dll_in100_out25_0_0 : label is "270"; + attribute CLKOP_PHASE of dll_in100_out25_0_0 : label is "270"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + dll_in100_out25_0_0: CIDDLLA + -- synopsys translate_off + generic map (GSR=> "DISABLED", ALU_INIT_CNTVAL=> 0, + ALU_UNLOCK_CNT=> 3, ALU_LOCK_CNT=> 3, CLKI_DIV=> 1, CLKOS_DIV=> 4, + CLKOS_FPHASE=> 0, CLKOS_PHASE=> 270, CLKOP_PHASE=> 270) + -- synopsys translate_on + port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi, + ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t, + LOCK=>lock, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of dll_in100_out25 is + for Structure + for all:CIDDLLA use entity ecp2m.CIDDLLA(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/scm/fifo_72x512.ipx b/lattice/scm/fifo_72x512.ipx new file mode 100644 index 0000000..3a78e88 --- /dev/null +++ b/lattice/scm/fifo_72x512.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/scm/fifo_72x512.lpc b/lattice/scm/fifo_72x512.lpc new file mode 100644 index 0000000..4259088 --- /dev/null +++ b/lattice/scm/fifo_72x512.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FFA1020C +SpeedGrade=7 +Package=FFABGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_72x512 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/17/2011 +Time=18:00:14 + +[Parameters] +Verilog=1 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=512 +RWidth=72 +WDepth=512 +WWidth=72 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=1 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=500 +PfDeassert=506 +Reset=Async +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/lattice/scm/fifo_72x512.vhd b/lattice/scm/fifo_72x512.vhd new file mode 100644 index 0000000..43c3166 --- /dev/null +++ b/lattice/scm/fifo_72x512.vhd @@ -0,0 +1,226 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_72x512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 72 -rwidth 72 -no_enable -pe 1 -pf 500 -e + +-- Mon Jan 17 18:00:14 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity fifo_72x512 is + port ( + Data: in std_logic_vector(71 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(71 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_72x512; + +architecture Structure of fifo_72x512 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal Empty_int: std_logic; + signal Full_int: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO16KA + -- synopsys translate_off + generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); + FULLPOINTER : in std_logic_vector(14 downto 0); + AFPOINTER1 : in std_logic_vector(14 downto 0); + AEPOINTER1 : in std_logic_vector(14 downto 0); + AFPOINTER : in std_logic_vector(14 downto 0); + AEPOINTER : in std_logic_vector(14 downto 0); + CSDECODE_R : in std_logic_vector(1 downto 0); + CSDECODE_W : in std_logic_vector(1 downto 0); + RESETMODE : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + FULLI: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; EMPTYI: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; + RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; + RST: in std_logic; RPRST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic; + EF: out std_logic; AEF: out std_logic; AFF: out std_logic; + FF: out std_logic); + end component; + attribute FULLPOINTER1 : string; + attribute FULLPOINTER : string; + attribute AFPOINTER1 : string; + attribute AFPOINTER : string; + attribute AEPOINTER1 : string; + attribute AEPOINTER : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute FULLPOINTER1 of fifo_72x512_0_1 : label is "0b011111111000001"; + attribute FULLPOINTER of fifo_72x512_0_1 : label is "0b011111111100001"; + attribute AFPOINTER1 of fifo_72x512_0_1 : label is "0b011111001000001"; + attribute AFPOINTER of fifo_72x512_0_1 : label is "0b011111001100001"; + attribute AEPOINTER1 of fifo_72x512_0_1 : label is "0b000000001011111"; + attribute AEPOINTER of fifo_72x512_0_1 : label is "0b000000000111111"; + attribute RESETMODE of fifo_72x512_0_1 : label is "ASYNC"; + attribute REGMODE of fifo_72x512_0_1 : label is "NOREG"; + attribute CSDECODE_R of fifo_72x512_0_1 : label is "0b11"; + attribute CSDECODE_W of fifo_72x512_0_1 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_72x512_0_1 : label is "36"; + attribute DATA_WIDTH_W of fifo_72x512_0_1 : label is "36"; + attribute FULLPOINTER1 of fifo_72x512_1_0 : label is "0b000000000000000"; + attribute FULLPOINTER of fifo_72x512_1_0 : label is "0b111111111111111"; + attribute AFPOINTER1 of fifo_72x512_1_0 : label is "0b000000000000000"; + attribute AFPOINTER of fifo_72x512_1_0 : label is "0b111111111111111"; + attribute AEPOINTER1 of fifo_72x512_1_0 : label is "0b000000000000000"; + attribute AEPOINTER of fifo_72x512_1_0 : label is "0b111111111111111"; + attribute RESETMODE of fifo_72x512_1_0 : label is "ASYNC"; + attribute REGMODE of fifo_72x512_1_0 : label is "NOREG"; + attribute CSDECODE_R of fifo_72x512_1_0 : label is "0b11"; + attribute CSDECODE_W of fifo_72x512_1_0 : label is "0b11"; + attribute DATA_WIDTH_R of fifo_72x512_1_0 : label is "36"; + attribute DATA_WIDTH_W of fifo_72x512_1_0 : label is "36"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_72x512_0_1: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", + AFPOINTER1=> "011111001000001", AFPOINTER=> "011111001100001", + AEPOINTER1=> "000000001011111", AEPOINTER=> "000000000111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, + WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), + DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), + DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty, + AFF=>AlmostFull, FF=>Full_int); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + fifo_72x512_1_0: FIFO16KA + -- synopsys translate_off + generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", + AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", + AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), + DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), + DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), + DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), + DI35=>Data(71), FULLI=>Full_int, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, + CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, + CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(54), + DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), + DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), + DO11=>Q(65), DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), + DO15=>Q(69), DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), + DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), + DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), + DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), + DO31=>Q(49), DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), + DO35=>Q(53), EF=>open, AEF=>open, AFF=>open, FF=>open); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of fifo_72x512 is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.ipx b/lattice/scm/lattice_scm_fifo_16bit_dualport.ipx new file mode 100644 index 0000000..9620b1f --- /dev/null +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc b/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc index d63038e..3521624 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc @@ -1,9 +1,9 @@ [Device] Family=latticescm -PartType=LFSCM3GA25EP1 -PartName=LFSCM3GA25EP1-6FF1020C -SpeedGrade=-6 -Package=FFBGA1020 +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FFA1020C +SpeedGrade=7 +Package=FFABGA1020 OperatingCondition=COM Status=P @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC -CoreRevision=4.4 +CoreRevision=5.4 ModuleName=lattice_scm_fifo_16bit_dualport -SourceFormat=Schematic/VHDL +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=07/30/2008 -Time=18:54:57 +Date=12/23/2010 +Time=11:49:43 [Parameters] Verilog=0 @@ -28,9 +28,9 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Only -RDepth=1024 +RDepth=64 RWidth=18 -WDepth=1024 +WDepth=64 WWidth=18 regout=0 CtrlByRdEn=0 @@ -40,7 +40,7 @@ PeAssert=10 PeDeassert=12 FullFlg=1 PfMode=Static - Single Threshold -PfAssert=508 +PfAssert=32 PfDeassert=506 Reset=Sync RDataCount=0 diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.srp b/lattice/scm/lattice_scm_fifo_16bit_dualport.srp index 54ab978..18ab6fd 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.srp +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.srp @@ -1,16 +1,16 @@ -SCUBA, Version ispLever_v71_PROD_Build (58) -Wed Jul 30 18:54:57 2008 +SCUBA, Version Diamond_1.1_Production (517) +Thu Dec 23 11:49:43 2010 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e + Issued command : /d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 64 -width 18 -rwidth 18 -no_enable -pe 10 -pf 32 -sync_reset -e Circuit name : lattice_scm_fifo_16bit_dualport Module type : ebfifo - Module Version : 4.4 + Module Version : 5.4 Ports : Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset Outputs : Q[17:0], Empty, Full, AlmostEmpty, AlmostFull diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.sym b/lattice/scm/lattice_scm_fifo_16bit_dualport.sym index d029f6b663d26ac3976f60f3dd78f0f94d88e708..23b3cbf4bd6d770ed49eb1c9f2256af471d094ba 100644 GIT binary patch delta 15 VcmZ3)vWSIkO*jJ(Y-E#R0stRK11kUk delta 15 WcmZ3)vWSIkP58sMocxV!GE4w2tp#lW diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd b/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd index ab276da..32843d7 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) --- Module Version: 4.4 ---/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 64 -width 18 -rwidth 18 -no_enable -pe 10 -pf 32 -sync_reset -e --- Wed Jul 30 18:54:57 2008 +-- Thu Dec 23 11:49:43 2010 library IEEE; use IEEE.std_logic_1164.all; @@ -109,18 +109,18 @@ architecture Structure of lattice_scm_fifo_16bit_dualport is attribute CSDECODE_W : string; attribute DATA_WIDTH_R : string; attribute DATA_WIDTH_W : string; - attribute FULLPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111100001"; - attribute FULLPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111110001"; - attribute AFPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b001111110100001"; - attribute AFPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b001111110110001"; - attribute AEPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010111111"; - attribute AEPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010101111"; + attribute FULLPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000011111000001"; + attribute FULLPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000011111100001"; + attribute AFPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000001111000001"; + attribute AFPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000001111100001"; + attribute AEPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000101111111"; + attribute AEPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000101011111"; attribute RESETMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "SYNC"; attribute REGMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "NOREG"; attribute CSDECODE_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11"; attribute CSDECODE_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11"; - attribute DATA_WIDTH_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "18"; - attribute DATA_WIDTH_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "18"; + attribute DATA_WIDTH_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "36"; + attribute DATA_WIDTH_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "36"; attribute syn_keep : boolean; begin @@ -133,11 +133,11 @@ begin lattice_scm_fifo_16bit_dualport_0_0: FIFO16KA -- synopsys translate_off - generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001", - AFPOINTER1=> "001111110100001", AFPOINTER=> "001111110110001", - AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111", + generic map (FULLPOINTER1=> "000011111000001", FULLPOINTER=> "000011111100001", + AFPOINTER1=> "000001111000001", AFPOINTER=> "000001111100001", + AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", RESETMODE=> "SYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", - CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18) + CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) -- synopsys translate_on port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), @@ -153,16 +153,15 @@ begin FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, - RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), - DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), - DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), - DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), - DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open, - DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open, - DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, - DO32=>open, DO33=>open, DO34=>open, DO35=>open, - EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull, - FF=>Full_int); + RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, + DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, + DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, + DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, + AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); Empty <= Empty_int; Full <= Full_int; diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport_tmpl.vhd b/lattice/scm/lattice_scm_fifo_16bit_dualport_tmpl.vhd index a4677a2..da7c75d 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport_tmpl.vhd +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58) --- Module Version: 4.4 --- Wed Jul 30 18:54:57 2008 +-- VHDL module instantiation generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.4 +-- Thu Dec 23 11:49:43 2010 -- parameterized module component declaration component lattice_scm_fifo_16bit_dualport diff --git a/lattice/scm/lattice_scm_fifo_18x1k.ipx b/lattice/scm/lattice_scm_fifo_18x1k.ipx new file mode 100644 index 0000000..1d67b17 --- /dev/null +++ b/lattice/scm/lattice_scm_fifo_18x1k.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/scm/pll_in100_out150.ipx b/lattice/scm/pll_in100_out150.ipx new file mode 100644 index 0000000..3dbe34d --- /dev/null +++ b/lattice/scm/pll_in100_out150.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lattice/scm/pll_in100_out150.lpc b/lattice/scm/pll_in100_out150.lpc new file mode 100644 index 0000000..5b077d5 --- /dev/null +++ b/lattice/scm/pll_in100_out150.lpc @@ -0,0 +1,58 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FFA1020C +SpeedGrade=7 +Package=FFABGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.2 +ModuleName=pll_in100_out150 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/07/2011 +Time=18:19:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Clki_freq=100 +U_OFrq=150 +OP_Tol=0.0 +ClkOP_Freq= 150.000000 +U_SFrq=100 +OS_Tol=0.0 +ClkOS_Freq= 100.000000 +Phase=180 +FineDelay=0 +FeedbackClk=CLKOP +Frequency= 150.000000 +enSpectrum=0 +smiport=0 +enRSTN=0 +Clki_boosting=DEL0 +Clkfb_boosting=DEL0 +Clki_fine=0 +Clkfb_fine=0 +enSpread=0 +modulation=1 +Desired=30 +Actual=30 +lock=Frequency +enGSR=0 +VcoRate= 450.000000 +Bandwidth= 4.074303 +enHighBand=0 +enBypassP=0 +enBypassS=1 diff --git a/lattice/scm/pll_in100_out150.vhd b/lattice/scm/pll_in100_out150.vhd new file mode 100644 index 0000000..432ea51 --- /dev/null +++ b/lattice/scm/pll_in100_out150.vhd @@ -0,0 +1,167 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.2 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n pll_in100_out150 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 150 -nfreq 100 -bypasss -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e + +-- Fri Jan 7 18:19:56 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity pll_in100_out150 is + generic ( + SMI_OFFSET : in String := "0x410" + ); + port ( + clk: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in100_out150 : entity is true; +end pll_in100_out150; + +architecture Structure of pll_in100_out150 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal clkos_t: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + attribute module_type : string; + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EHXPLLA + generic (SMI_OFFSET : in String + -- synopsys translate_off + ; GSR : in String; CLKOS_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; + CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; + CLKOS_MODE : in String; CLKOP_MODE : in String; + PHASEADJ : in Integer; CLKOS_VCODEL : in Integer + -- synopsys translate_on + ); + port (SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKI: in std_logic; + CLKFB: in std_logic; RSTN: in std_logic; + CLKOS: out std_logic; CLKOP: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic; + SMIRDATA: out std_logic); + end component; + attribute module_type of EHXPLLA : component is "EHXPLLA"; + attribute ip_type : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute VCO_LOWERFREQ : string; + attribute GMCFREQSEL : string; + attribute GSR : string; + attribute SPREAD_DIV2 : string; + attribute SPREAD_DIV1 : string; + attribute SPREAD_DRIFT : string; + attribute SPREAD : string; + attribute CLKFB_FDEL : string; + attribute CLKI_FDEL : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute LF_RESISTOR : string; + attribute LF_IX5UA : string; + attribute CLKOS_FDEL : string; + attribute CLKOS_VCODEL : string; + attribute PHASEADJ : string; + attribute CLKOS_MODE : string; + attribute CLKOP_MODE : string; + attribute CLKOS_DIV : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute ip_type of pll_in100_out150_0_0 : label is "EHXPLLA"; + attribute FREQUENCY_PIN_CLKOS of pll_in100_out150_0_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of pll_in100_out150_0_0 : label is "150.000000"; + attribute FREQUENCY_PIN_CLKI of pll_in100_out150_0_0 : label is "100.000000"; + attribute VCO_LOWERFREQ of pll_in100_out150_0_0 : label is "DISABLED"; + attribute GMCFREQSEL of pll_in100_out150_0_0 : label is "HIGH"; + attribute GSR of pll_in100_out150_0_0 : label is "ENABLED"; + attribute SPREAD_DIV2 of pll_in100_out150_0_0 : label is "2"; + attribute SPREAD_DIV1 of pll_in100_out150_0_0 : label is "2"; + attribute SPREAD_DRIFT of pll_in100_out150_0_0 : label is "1"; + attribute SPREAD of pll_in100_out150_0_0 : label is "DISABLED"; + attribute CLKFB_FDEL of pll_in100_out150_0_0 : label is "0"; + attribute CLKI_FDEL of pll_in100_out150_0_0 : label is "0"; + attribute CLKFB_PDEL of pll_in100_out150_0_0 : label is "DEL0"; + attribute CLKI_PDEL of pll_in100_out150_0_0 : label is "DEL0"; + attribute LF_RESISTOR of pll_in100_out150_0_0 : label is "0b111001"; + attribute LF_IX5UA of pll_in100_out150_0_0 : label is "31"; + attribute CLKOS_FDEL of pll_in100_out150_0_0 : label is "0"; + attribute CLKOS_VCODEL of pll_in100_out150_0_0 : label is "0"; + attribute PHASEADJ of pll_in100_out150_0_0 : label is "0"; + attribute CLKOS_MODE of pll_in100_out150_0_0 : label is "BYPASS"; + attribute CLKOP_MODE of pll_in100_out150_0_0 : label is "DIV"; + attribute CLKOS_DIV of pll_in100_out150_0_0 : label is "3"; + attribute CLKOP_DIV of pll_in100_out150_0_0 : label is "3"; + attribute CLKFB_DIV of pll_in100_out150_0_0 : label is "3"; + attribute CLKI_DIV of pll_in100_out150_0_0 : label is "2"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + pll_in100_out150_0_0: EHXPLLA + generic map (SMI_OFFSET=> SMI_OFFSET + -- synopsys translate_off + , GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0, + CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "BYPASS", + CLKOP_MODE=> "DIV", CLKOS_DIV=> 3, CLKOP_DIV=> 3, CLKFB_DIV=> 3, + CLKI_DIV=> 2 + -- synopsys translate_on + ) + port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, + RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, + CLKINTFB=>open, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of pll_in100_out150 is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:EHXPLLA use entity SCM.EHXPLLA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/scm/pll_in100_out50_250.ipx b/lattice/scm/pll_in100_out50_250.ipx new file mode 100644 index 0000000..b67218d --- /dev/null +++ b/lattice/scm/pll_in100_out50_250.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lattice/scm/pll_in100_out50_250.lpc b/lattice/scm/pll_in100_out50_250.lpc new file mode 100644 index 0000000..80c3453 --- /dev/null +++ b/lattice/scm/pll_in100_out50_250.lpc @@ -0,0 +1,58 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FF1020C +SpeedGrade=7 +Package=FFBGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.2 +ModuleName=pll_in100_out50_250 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/05/2011 +Time=14:30:43 + +[Parameters] +Verilog=1 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Clki_freq=100 +U_OFrq=250 +OP_Tol=0.0 +ClkOP_Freq= 250.000000 +U_SFrq=50 +OS_Tol=0.0 +ClkOS_Freq= 50.000000 +Phase=0 +FineDelay=0 +FeedbackClk=CLKOP +Frequency= 250.000000 +enSpectrum=0 +smiport=0 +enRSTN=0 +Clki_boosting=DEL0 +Clkfb_boosting=DEL0 +Clki_fine=0 +Clkfb_fine=0 +enSpread=0 +modulation=1 +Desired=30 +Actual=30 +lock=Frequency +enGSR=0 +VcoRate= 500.000000 +Bandwidth= 4.176226 +enHighBand=0 +enBypassP=0 +enBypassS=0 diff --git a/lattice/scm/pll_in100_out50_250.vhd b/lattice/scm/pll_in100_out50_250.vhd new file mode 100644 index 0000000..d6591dd --- /dev/null +++ b/lattice/scm/pll_in100_out50_250.vhd @@ -0,0 +1,167 @@ +-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) +-- Module Version: 5.2 +--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n pll_in100_out50_250 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 250 -nfreq 50 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e + +-- Wed Jan 5 14:30:43 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity pll_in100_out50_250 is + generic ( + SMI_OFFSET : in String := "0x410" + ); + port ( + clk: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in100_out50_250 : entity is true; +end pll_in100_out50_250; + +architecture Structure of pll_in100_out50_250 is + + -- internal signal declarations + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal clkos_t: std_logic; + signal clkop_t: std_logic; + signal clk_t: std_logic; + + attribute module_type : string; + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EHXPLLA + generic (SMI_OFFSET : in String + -- synopsys translate_off + ; GSR : in String; CLKOS_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; + CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; + CLKOS_MODE : in String; CLKOP_MODE : in String; + PHASEADJ : in Integer; CLKOS_VCODEL : in Integer + -- synopsys translate_on + ); + port (SMIADDR9: in std_logic; SMIADDR8: in std_logic; + SMIADDR7: in std_logic; SMIADDR6: in std_logic; + SMIADDR5: in std_logic; SMIADDR4: in std_logic; + SMIADDR3: in std_logic; SMIADDR2: in std_logic; + SMIADDR1: in std_logic; SMIADDR0: in std_logic; + SMIRD: in std_logic; SMIWR: in std_logic; + SMICLK: in std_logic; SMIWDATA: in std_logic; + SMIRSTN: in std_logic; CLKI: in std_logic; + CLKFB: in std_logic; RSTN: in std_logic; + CLKOS: out std_logic; CLKOP: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic; + SMIRDATA: out std_logic); + end component; + attribute module_type of EHXPLLA : component is "EHXPLLA"; + attribute ip_type : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute VCO_LOWERFREQ : string; + attribute GMCFREQSEL : string; + attribute GSR : string; + attribute SPREAD_DIV2 : string; + attribute SPREAD_DIV1 : string; + attribute SPREAD_DRIFT : string; + attribute SPREAD : string; + attribute CLKFB_FDEL : string; + attribute CLKI_FDEL : string; + attribute CLKFB_PDEL : string; + attribute CLKI_PDEL : string; + attribute LF_RESISTOR : string; + attribute LF_IX5UA : string; + attribute CLKOS_FDEL : string; + attribute CLKOS_VCODEL : string; + attribute PHASEADJ : string; + attribute CLKOS_MODE : string; + attribute CLKOP_MODE : string; + attribute CLKOS_DIV : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute ip_type of pll_in100_out50_250_0_0 : label is "EHXPLLA"; + attribute FREQUENCY_PIN_CLKOS of pll_in100_out50_250_0_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOP of pll_in100_out50_250_0_0 : label is "250.000000"; + attribute FREQUENCY_PIN_CLKI of pll_in100_out50_250_0_0 : label is "100.000000"; + attribute VCO_LOWERFREQ of pll_in100_out50_250_0_0 : label is "DISABLED"; + attribute GMCFREQSEL of pll_in100_out50_250_0_0 : label is "HIGH"; + attribute GSR of pll_in100_out50_250_0_0 : label is "ENABLED"; + attribute SPREAD_DIV2 of pll_in100_out50_250_0_0 : label is "2"; + attribute SPREAD_DIV1 of pll_in100_out50_250_0_0 : label is "2"; + attribute SPREAD_DRIFT of pll_in100_out50_250_0_0 : label is "1"; + attribute SPREAD of pll_in100_out50_250_0_0 : label is "DISABLED"; + attribute CLKFB_FDEL of pll_in100_out50_250_0_0 : label is "0"; + attribute CLKI_FDEL of pll_in100_out50_250_0_0 : label is "0"; + attribute CLKFB_PDEL of pll_in100_out50_250_0_0 : label is "DEL0"; + attribute CLKI_PDEL of pll_in100_out50_250_0_0 : label is "DEL0"; + attribute LF_RESISTOR of pll_in100_out50_250_0_0 : label is "0b110111"; + attribute LF_IX5UA of pll_in100_out50_250_0_0 : label is "31"; + attribute CLKOS_FDEL of pll_in100_out50_250_0_0 : label is "0"; + attribute CLKOS_VCODEL of pll_in100_out50_250_0_0 : label is "0"; + attribute PHASEADJ of pll_in100_out50_250_0_0 : label is "0"; + attribute CLKOS_MODE of pll_in100_out50_250_0_0 : label is "DIV"; + attribute CLKOP_MODE of pll_in100_out50_250_0_0 : label is "DIV"; + attribute CLKOS_DIV of pll_in100_out50_250_0_0 : label is "10"; + attribute CLKOP_DIV of pll_in100_out50_250_0_0 : label is "2"; + attribute CLKFB_DIV of pll_in100_out50_250_0_0 : label is "5"; + attribute CLKI_DIV of pll_in100_out50_250_0_0 : label is "2"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + pll_in100_out50_250_0_0: EHXPLLA + generic map (SMI_OFFSET=> SMI_OFFSET + -- synopsys translate_off + , GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0, + CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV", + CLKOP_MODE=> "DIV", CLKOS_DIV=> 10, CLKOP_DIV=> 2, CLKFB_DIV=> 5, + CLKI_DIV=> 2 + -- synopsys translate_on + ) + port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, + SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, + SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, + SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, + SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, + SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, + SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, + RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, + CLKINTFB=>open, SMIRDATA=>open); + + clkos <= clkos_t; + clkop <= clkop_t; + clk_t <= clk; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of pll_in100_out50_250 is + for Structure + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:EHXPLLA use entity SCM.EHXPLLA(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd b/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd index a11f313..4a5d6f5 100644 --- a/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd +++ b/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd @@ -28,15 +28,22 @@ end entity trb_net_fifo_16bit_bram_dualport; architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is - component lattice_scm_fifo_16bit_dualport - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; Full: out std_logic); - end component; +component lattice_scm_fifo_16bit_dualport is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end component; - signal buf_empty_out, buf_full_out : std_logic; BEGIN FIFO_DP_BRAM : lattice_scm_fifo_16bit_dualport @@ -47,16 +54,16 @@ BEGIN WrEn => write_enable_in, RdEn => read_enable_in, Reset => fifo_gsr_in, - RPReset => '0', + RPReset => fifo_gsr_in, Q => read_data_out, - Empty => buf_empty_out, - Full => buf_full_out + Empty => empty_out, + Full => full_out, + AlmostEmpty => almost_empty_out, + AlmostFull => almost_full_out ); -empty_out <= buf_empty_out; -full_out <= buf_full_out; -almost_empty_out <= buf_empty_out; -almost_full_out <= buf_full_out; + fifostatus_out <= (others => '0'); valid_read_out <= '0'; + end architecture trb_net_fifo_16bit_bram_dualport_arch; diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.ipx b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.ipx new file mode 100644 index 0000000..0a47643 --- /dev/null +++ b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.ipx @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.lpc b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.lpc new file mode 100644 index 0000000..2c9b081 --- /dev/null +++ b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.lpc @@ -0,0 +1,61 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-7FFA1020C +SpeedGrade=7 +Package=FFABGA1020 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.1 +ModuleName=serdes_gbe_0_100_ext +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/10/2011 +Time=10:09:47 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +QuadMode=Generic 8b10b +enChannel0=1 +enChannel1=0 +enChannel2=0 +enChannel3=0 +enAlign0=0 +enAlign1=0 +enAlign2=0 +enControlPorts=1 +enSystemBus=0 +en10gLsm=0 +ClkSelect=Dedicated CML Transmit/Receive Reference Clock +BitClkRate=2 +RefClkMult=20X +RefClkRate=100 +BusWidth=16 +IntClkRate=100 +AmpBoost=Disabled +Bit1=0 +Word1=FF +Bit2=0 +Word2=7C +Bit3=0 +Word3=7C +enQuad=0 +QuadGroup=Group 0 + +[FilesGenerated] +serdes_gbe_0_100_ext.pp=pp +serdes_gbe_0_100_ext.tft=tft +serdes_gbe_0_100_ext.txt=pcs_module +serdes_gbe_0_100_ext.sym=sym diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.txt b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.txt new file mode 100644 index 0000000..0da4e1a --- /dev/null +++ b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.txt @@ -0,0 +1,70 @@ + +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCS quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCS quad to the final design requirements. +# channel_0 is in "8b10b" mode +# channel_1 is in "Disabled" mode +# channel_2 is in "Disabled" mode +# channel_3 is in "Disabled" mode + +ch0 13 03 # Powerup Channel +ch0 00 01 +quad 00 00 +quad 01 E4 +quad 28 40 # Reference clock multiplier +quad 29 01 # default +quad 02 00 # ref_pclk source is ch0 +quad 04 00 # MCA enable 4 channels + +quad 18 10 # 8b10b Mode +# quad 14 7F # Word Alignment Mask +# quad 15 03 # +ve K +# quad 16 7C # -ve K +quad 19 0C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit +ch0 14 90 # 16% pre-emphasis +ch0 15 18 # +6dB equalization + +# These lines must appear last in the autoconfig file. These lines apply the correct +# reset sequence to the PCS block upon bitstream configuration +quad 41 00 # de-assert serdes_rst +quad 40 ff # assert datapath reset for all channels +quad 40 00 # de-assert datapath reset for all channels + + + +#Copied from internal 100 MHz: +# ch0 13 03 # Powerup Channel 0 TX/RX +# ch0 00 01 # link state machine enabled +# quad 00 00 # some standard settings? +# quad 01 E4 # RX clock select +# quad 28 40 # Reference clock multiplier +# quad 29 11 # JM101203 core clock as reference # set to 01 +# quad 30 04 # JM101203 TX sync enable #sync TX clock from all channels +# quad 02 00 # ref_pclk source is ch0, rxa_pclk is ch0, rxb_pclk is ch0 +# quad 04 00 # MCA enable 4 channels +# +# quad 18 10 # 8b10b Mode +# +# #Here default values are used by SM +# # quad 14 FF # Word Alignment Mask [7:0] +# # quad 15 83 # +ve K [7:0] -> COMMA_A = 11_0000_0101 - its inverted (see register convention in datasheet)! +# # quad 16 7c # -ve K [7:0] -> COMMA_B = 00_1111_1010 - its inverted ! +# # quad 17 36 # upper bits of CA,CB,CM +# +# +# # quad 0D 97 # Watermark level on CTC: 9 high, 7 low +# # quad 0E 08 # JM101203 was 0B # insertion/deletion control of CTC: two char matching +# # quad 11 BC # /I2/ pattern for CTC match (K28.5) +# # quad 12 50 # (D16.2) +# # quad 13 04 # (use comma) +# +# quad 19 0C # Disable word_align_en port, FPGA bus width is 16-bit/20-bit +# ch0 14 90 # 16% pre-emphasis +# ch0 15 18 # JM101203 was 10 # +6dB equalization +# +# # These lines must appear last in the autoconfig file. These lines apply the correct +# # reset sequence to the PCS block upon bitstream configuration +# quad 41 00 # de-assert serdes_rst +# quad 40 ff # assert datapath reset for all channels +# quad 40 00 # de-assert datapath reset for all channels \ No newline at end of file diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd new file mode 100644 index 0000000..61c6005 --- /dev/null +++ b/media_interfaces/scm_sfp/serdes_gbe_0_100_ext.vhd @@ -0,0 +1,2392 @@ + + +-- channel_0 is in "8b10b" mode +-- channel_1 is in "Disabled" mode +-- channel_2 is in "Disabled" mode +-- channel_3 is in "Disabled" mode + +--synopsys translate_off + +library pcsa_work; +use pcsa_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSA is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt" + ); +port ( + HDINP0 : in std_logic; + HDINN0 : in std_logic; + HDINP1 : in std_logic; + HDINN1 : in std_logic; + HDINP2 : in std_logic; + HDINN2 : in std_logic; + HDINP3 : in std_logic; + HDINN3 : in std_logic; + HDOUTP0 : out std_logic; + HDOUTN0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTP3 : out std_logic; + HDOUTN3 : out std_logic; + REFCLKP : in std_logic; + REFCLKN : in std_logic; + RXREFCLKP : in std_logic; + RXREFCLKN : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_MACRO_RST : in std_logic; + + FFC_LANE_TX_RST0 : in std_logic; + FFC_LANE_TX_RST1 : in std_logic; + FFC_LANE_TX_RST2 : in std_logic; + FFC_LANE_TX_RST3 : in std_logic; + + FFC_LANE_RX_RST0 : in std_logic; + FFC_LANE_RX_RST1 : in std_logic; + FFC_LANE_RX_RST2 : in std_logic; + FFC_LANE_RX_RST3 : in std_logic; + + FFC_PCIE_EI_EN_0 : in std_logic; + FFC_PCIE_EI_EN_1 : in std_logic; + FFC_PCIE_EI_EN_2 : in std_logic; + FFC_PCIE_EI_EN_3 : in std_logic; + + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + + FFC_PCIE_TX_0 : in std_logic; + FFC_PCIE_TX_1 : in std_logic; + FFC_PCIE_TX_2 : in std_logic; + FFC_PCIE_TX_3 : in std_logic; + + FFC_PCIE_RX_0 : in std_logic; + FFC_PCIE_RX_1 : in std_logic; + FFC_PCIE_RX_2 : in std_logic; + FFC_PCIE_RX_3 : in std_logic; + + FFC_SD_0 : in std_logic; + FFC_SD_1 : in std_logic; + FFC_SD_2 : in std_logic; + FFC_SD_3 : in std_logic; + + FFC_EN_CGA_0 : in std_logic; + FFC_EN_CGA_1 : in std_logic; + FFC_EN_CGA_2 : in std_logic; + FFC_EN_CGA_3 : in std_logic; + + FFC_ALIGN_EN_0 : in std_logic; + FFC_ALIGN_EN_1 : in std_logic; + FFC_ALIGN_EN_2 : in std_logic; + FFC_ALIGN_EN_3 : in std_logic; + + FFC_AB_RESET : in std_logic; + FFC_CD_RESET : in std_logic; + + FFS_LS_STATUS_0 : out std_logic; + FFS_LS_STATUS_1 : out std_logic; + FFS_LS_STATUS_2 : out std_logic; + FFS_LS_STATUS_3 : out std_logic; + + FFS_AB_STATUS : out std_logic; + FFS_CD_STATUS : out std_logic; + + FFS_AB_ALIGNED : out std_logic; + FFS_CD_ALIGNED : out std_logic; + + FFS_RLOS_LO0 : out std_logic; + FFS_RLOS_LO1 : out std_logic; + FFS_RLOS_LO2 : out std_logic; + FFS_RLOS_LO3 : out std_logic; + + FFS_AB_FAILED : out std_logic; + FFS_CD_FAILED : out std_logic; + + FFC_FB_LB_0 : in std_logic; + FFC_FB_LB_1 : in std_logic; + FFC_FB_LB_2 : in std_logic; + FFC_FB_LB_3 : in std_logic; + + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + + FFS_CC_ORUN_0 : out std_logic; + FFS_CC_ORUN_1 : out std_logic; + FFS_CC_ORUN_2 : out std_logic; + FFS_CC_ORUN_3 : out std_logic; + + FFS_CC_URUN_0 : out std_logic; + FFS_CC_URUN_1 : out std_logic; + FFS_CC_URUN_2 : out std_logic; + FFS_CC_URUN_3 : out std_logic; + + FFC_CK_CORE_TX : in std_logic; + FFC_CK_CORE_RX : in std_logic; + RDATAO_7 : out std_logic; + RDATAO_6 : out std_logic; + RDATAO_5 : out std_logic; + RDATAO_4 : out std_logic; + RDATAO_3 : out std_logic; + RDATAO_2 : out std_logic; + RDATAO_1 : out std_logic; + RDATAO_0 : out std_logic; + INTO : out std_logic; + + ADDRI_7 : in std_logic; + ADDRI_6 : in std_logic; + ADDRI_5 : in std_logic; + ADDRI_4 : in std_logic; + ADDRI_3 : in std_logic; + ADDRI_2 : in std_logic; + ADDRI_1 : in std_logic; + ADDRI_0 : in std_logic; + WDATAI_7 : in std_logic; + WDATAI_6 : in std_logic; + WDATAI_5 : in std_logic; + WDATAI_4 : in std_logic; + WDATAI_3 : in std_logic; + WDATAI_2 : in std_logic; + WDATAI_1 : in std_logic; + WDATAI_0 : in std_logic; + RDI : in std_logic; + WSTBI : in std_logic; + + CS_CHIF_0 : in std_logic; + CS_CHIF_1 : in std_logic; + CS_CHIF_2 : in std_logic; + CS_CHIF_3 : in std_logic; + CS_QIF : in std_logic; + + QUAD_ID_1 : in std_logic; + QUAD_ID_0 : in std_logic; + + FF_SYSCLK_P1 : out std_logic; + + FF_SYSCLK0 : out std_logic; + FF_SYSCLK1 : out std_logic; + FF_SYSCLK2 : out std_logic; + FF_SYSCLK3 : out std_logic; + + FF_RXCLK_P1 : out std_logic; + FF_RXCLK_P2 : out std_logic; + + FF_RXCLK0 : out std_logic; + FF_RXCLK1 : out std_logic; + FF_RXCLK2 : out std_logic; + FF_RXCLK3 : out std_logic; + + QUAD_CLK : out std_logic; + + GRP_CLK_P1_3 : in std_logic; + GRP_CLK_P1_2 : in std_logic; + GRP_CLK_P1_1 : in std_logic; + GRP_CLK_P1_0 : in std_logic; + + GRP_CLK_P2_3 : in std_logic; + GRP_CLK_P2_2 : in std_logic; + GRP_CLK_P2_1 : in std_logic; + GRP_CLK_P2_0 : in std_logic; + + GRP_START_3 : in std_logic; + GRP_START_2 : in std_logic; + GRP_START_1 : in std_logic; + GRP_START_0 : in std_logic; + + GRP_DONE_3 : in std_logic; + GRP_DONE_2 : in std_logic; + GRP_DONE_1 : in std_logic; + GRP_DONE_0 : in std_logic; + + GRP_DESKEW_ERROR_3 : in std_logic; + GRP_DESKEW_ERROR_2 : in std_logic; + GRP_DESKEW_ERROR_1 : in std_logic; + GRP_DESKEW_ERROR_0 : in std_logic; + + IQA_START_LS : out std_logic; + IQA_DONE_LS : out std_logic; + IQA_AND_FP1_LS : out std_logic; + IQA_AND_FP0_LS : out std_logic; + IQA_OR_FP1_LS : out std_logic; + IQA_OR_FP0_LS : out std_logic; + IQA_RST_N : out std_logic; + + FF_TCLK0 : in std_logic; + FF_TCLK1 : in std_logic; + FF_TCLK2 : in std_logic; + FF_TCLK3 : in std_logic; + + FF_RCLK0 : in std_logic; + FF_RCLK1 : in std_logic; + FF_RCLK2 : in std_logic; + FF_RCLK3 : in std_logic; + TCK_FMACP : in std_logic; + + FF_TXD_0_23 : in std_logic; + FF_TXD_0_22 : in std_logic; + FF_TXD_0_21 : in std_logic; + FF_TXD_0_20 : in std_logic; + FF_TXD_0_19 : in std_logic; + FF_TXD_0_18 : in std_logic; + FF_TXD_0_17 : in std_logic; + FF_TXD_0_16 : in std_logic; + FF_TXD_0_15 : in std_logic; + FF_TXD_0_14 : in std_logic; + FF_TXD_0_13 : in std_logic; + FF_TXD_0_12 : in std_logic; + FF_TXD_0_11 : in std_logic; + FF_TXD_0_10 : in std_logic; + FF_TXD_0_9 : in std_logic; + FF_TXD_0_8 : in std_logic; + FF_TXD_0_7 : in std_logic; + FF_TXD_0_6 : in std_logic; + FF_TXD_0_5 : in std_logic; + FF_TXD_0_4 : in std_logic; + FF_TXD_0_3 : in std_logic; + FF_TXD_0_2 : in std_logic; + FF_TXD_0_1 : in std_logic; + FF_TXD_0_0 : in std_logic; + FB_RXD_0_23 : out std_logic; + FB_RXD_0_22 : out std_logic; + FB_RXD_0_21 : out std_logic; + FB_RXD_0_20 : out std_logic; + FB_RXD_0_19 : out std_logic; + FB_RXD_0_18 : out std_logic; + FB_RXD_0_17 : out std_logic; + FB_RXD_0_16 : out std_logic; + FB_RXD_0_15 : out std_logic; + FB_RXD_0_14 : out std_logic; + FB_RXD_0_13 : out std_logic; + FB_RXD_0_12 : out std_logic; + FB_RXD_0_11 : out std_logic; + FB_RXD_0_10 : out std_logic; + FB_RXD_0_9 : out std_logic; + FB_RXD_0_8 : out std_logic; + FB_RXD_0_7 : out std_logic; + FB_RXD_0_6 : out std_logic; + FB_RXD_0_5 : out std_logic; + FB_RXD_0_4 : out std_logic; + FB_RXD_0_3 : out std_logic; + FB_RXD_0_2 : out std_logic; + FB_RXD_0_1 : out std_logic; + FB_RXD_0_0 : out std_logic; + FF_TXD_1_23 : in std_logic; + FF_TXD_1_22 : in std_logic; + FF_TXD_1_21 : in std_logic; + FF_TXD_1_20 : in std_logic; + FF_TXD_1_19 : in std_logic; + FF_TXD_1_18 : in std_logic; + FF_TXD_1_17 : in std_logic; + FF_TXD_1_16 : in std_logic; + FF_TXD_1_15 : in std_logic; + FF_TXD_1_14 : in std_logic; + FF_TXD_1_13 : in std_logic; + FF_TXD_1_12 : in std_logic; + FF_TXD_1_11 : in std_logic; + FF_TXD_1_10 : in std_logic; + FF_TXD_1_9 : in std_logic; + FF_TXD_1_8 : in std_logic; + FF_TXD_1_7 : in std_logic; + FF_TXD_1_6 : in std_logic; + FF_TXD_1_5 : in std_logic; + FF_TXD_1_4 : in std_logic; + FF_TXD_1_3 : in std_logic; + FF_TXD_1_2 : in std_logic; + FF_TXD_1_1 : in std_logic; + FF_TXD_1_0 : in std_logic; + FB_RXD_1_23 : out std_logic; + FB_RXD_1_22 : out std_logic; + FB_RXD_1_21 : out std_logic; + FB_RXD_1_20 : out std_logic; + FB_RXD_1_19 : out std_logic; + FB_RXD_1_18 : out std_logic; + FB_RXD_1_17 : out std_logic; + FB_RXD_1_16 : out std_logic; + FB_RXD_1_15 : out std_logic; + FB_RXD_1_14 : out std_logic; + FB_RXD_1_13 : out std_logic; + FB_RXD_1_12 : out std_logic; + FB_RXD_1_11 : out std_logic; + FB_RXD_1_10 : out std_logic; + FB_RXD_1_9 : out std_logic; + FB_RXD_1_8 : out std_logic; + FB_RXD_1_7 : out std_logic; + FB_RXD_1_6 : out std_logic; + FB_RXD_1_5 : out std_logic; + FB_RXD_1_4 : out std_logic; + FB_RXD_1_3 : out std_logic; + FB_RXD_1_2 : out std_logic; + FB_RXD_1_1 : out std_logic; + FB_RXD_1_0 : out std_logic; + FF_TXD_2_23 : in std_logic; + FF_TXD_2_22 : in std_logic; + FF_TXD_2_21 : in std_logic; + FF_TXD_2_20 : in std_logic; + FF_TXD_2_19 : in std_logic; + FF_TXD_2_18 : in std_logic; + FF_TXD_2_17 : in std_logic; + FF_TXD_2_16 : in std_logic; + FF_TXD_2_15 : in std_logic; + FF_TXD_2_14 : in std_logic; + FF_TXD_2_13 : in std_logic; + FF_TXD_2_12 : in std_logic; + FF_TXD_2_11 : in std_logic; + FF_TXD_2_10 : in std_logic; + FF_TXD_2_9 : in std_logic; + FF_TXD_2_8 : in std_logic; + FF_TXD_2_7 : in std_logic; + FF_TXD_2_6 : in std_logic; + FF_TXD_2_5 : in std_logic; + FF_TXD_2_4 : in std_logic; + FF_TXD_2_3 : in std_logic; + FF_TXD_2_2 : in std_logic; + FF_TXD_2_1 : in std_logic; + FF_TXD_2_0 : in std_logic; + FB_RXD_2_23 : out std_logic; + FB_RXD_2_22 : out std_logic; + FB_RXD_2_21 : out std_logic; + FB_RXD_2_20 : out std_logic; + FB_RXD_2_19 : out std_logic; + FB_RXD_2_18 : out std_logic; + FB_RXD_2_17 : out std_logic; + FB_RXD_2_16 : out std_logic; + FB_RXD_2_15 : out std_logic; + FB_RXD_2_14 : out std_logic; + FB_RXD_2_13 : out std_logic; + FB_RXD_2_12 : out std_logic; + FB_RXD_2_11 : out std_logic; + FB_RXD_2_10 : out std_logic; + FB_RXD_2_9 : out std_logic; + FB_RXD_2_8 : out std_logic; + FB_RXD_2_7 : out std_logic; + FB_RXD_2_6 : out std_logic; + FB_RXD_2_5 : out std_logic; + FB_RXD_2_4 : out std_logic; + FB_RXD_2_3 : out std_logic; + FB_RXD_2_2 : out std_logic; + FB_RXD_2_1 : out std_logic; + FB_RXD_2_0 : out std_logic; + FF_TXD_3_23 : in std_logic; + FF_TXD_3_22 : in std_logic; + FF_TXD_3_21 : in std_logic; + FF_TXD_3_20 : in std_logic; + FF_TXD_3_19 : in std_logic; + FF_TXD_3_18 : in std_logic; + FF_TXD_3_17 : in std_logic; + FF_TXD_3_16 : in std_logic; + FF_TXD_3_15 : in std_logic; + FF_TXD_3_14 : in std_logic; + FF_TXD_3_13 : in std_logic; + FF_TXD_3_12 : in std_logic; + FF_TXD_3_11 : in std_logic; + FF_TXD_3_10 : in std_logic; + FF_TXD_3_9 : in std_logic; + FF_TXD_3_8 : in std_logic; + FF_TXD_3_7 : in std_logic; + FF_TXD_3_6 : in std_logic; + FF_TXD_3_5 : in std_logic; + FF_TXD_3_4 : in std_logic; + FF_TXD_3_3 : in std_logic; + FF_TXD_3_2 : in std_logic; + FF_TXD_3_1 : in std_logic; + FF_TXD_3_0 : in std_logic; + FB_RXD_3_23 : out std_logic; + FB_RXD_3_22 : out std_logic; + FB_RXD_3_21 : out std_logic; + FB_RXD_3_20 : out std_logic; + FB_RXD_3_19 : out std_logic; + FB_RXD_3_18 : out std_logic; + FB_RXD_3_17 : out std_logic; + FB_RXD_3_16 : out std_logic; + FB_RXD_3_15 : out std_logic; + FB_RXD_3_14 : out std_logic; + FB_RXD_3_13 : out std_logic; + FB_RXD_3_12 : out std_logic; + FB_RXD_3_11 : out std_logic; + FB_RXD_3_10 : out std_logic; + FB_RXD_3_9 : out std_logic; + FB_RXD_3_8 : out std_logic; + FB_RXD_3_7 : out std_logic; + FB_RXD_3_6 : out std_logic; + FB_RXD_3_5 : out std_logic; + FB_RXD_3_4 : out std_logic; + FB_RXD_3_3 : out std_logic; + FB_RXD_3_2 : out std_logic; + FB_RXD_3_1 : out std_logic; + FB_RXD_3_0 : out std_logic; + TCK_FMAC : out std_logic; + BS4PAD_0 : out std_logic; + BS4PAD_1 : out std_logic; + BS4PAD_2 : out std_logic; + BS4PAD_3 : out std_logic; + COUT_21 : out std_logic; + COUT_20 : out std_logic; + COUT_19 : out std_logic; + COUT_18 : out std_logic; + COUT_17 : out std_logic; + COUT_16 : out std_logic; + COUT_15 : out std_logic; + COUT_14 : out std_logic; + COUT_13 : out std_logic; + COUT_12 : out std_logic; + COUT_11 : out std_logic; + COUT_10 : out std_logic; + COUT_9 : out std_logic; + COUT_8 : out std_logic; + COUT_7 : out std_logic; + COUT_6 : out std_logic; + COUT_5 : out std_logic; + COUT_4 : out std_logic; + COUT_3 : out std_logic; + COUT_2 : out std_logic; + COUT_1 : out std_logic; + COUT_0 : out std_logic; + CIN_12 : in std_logic; + CIN_11 : in std_logic; + CIN_10 : in std_logic; + CIN_9 : in std_logic; + CIN_8 : in std_logic; + CIN_7 : in std_logic; + CIN_6 : in std_logic; + CIN_5 : in std_logic; + CIN_4 : in std_logic; + CIN_3 : in std_logic; + CIN_2 : in std_logic; + CIN_1 : in std_logic; + CIN_0 : in std_logic; + TESTCLK_MACO : in std_logic +); + +end PCSA; + +architecture PCSA_arch of PCSA is + +component PCSA_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINP0 : in std_logic; + HDINN0 : in std_logic; + HDINP1 : in std_logic; + HDINN1 : in std_logic; + HDINP2 : in std_logic; + HDINN2 : in std_logic; + HDINP3 : in std_logic; + HDINN3 : in std_logic; + HDOUTP0 : out std_logic; + HDOUTN0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTP3 : out std_logic; + HDOUTN3 : out std_logic; + REFCLKP : in std_logic; + REFCLKN : in std_logic; + RXREFCLKP : in std_logic; + RXREFCLKN : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_MACRO_RST : in std_logic; + + FFC_LANE_TX_RST0 : in std_logic; + FFC_LANE_TX_RST1 : in std_logic; + FFC_LANE_TX_RST2 : in std_logic; + FFC_LANE_TX_RST3 : in std_logic; + + FFC_LANE_RX_RST0 : in std_logic; + FFC_LANE_RX_RST1 : in std_logic; + FFC_LANE_RX_RST2 : in std_logic; + FFC_LANE_RX_RST3 : in std_logic; + + FFC_PCIE_EI_EN_0 : in std_logic; + FFC_PCIE_EI_EN_1 : in std_logic; + FFC_PCIE_EI_EN_2 : in std_logic; + FFC_PCIE_EI_EN_3 : in std_logic; + + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + + FFC_PCIE_TX_0 : in std_logic; + FFC_PCIE_TX_1 : in std_logic; + FFC_PCIE_TX_2 : in std_logic; + FFC_PCIE_TX_3 : in std_logic; + + FFC_PCIE_RX_0 : in std_logic; + FFC_PCIE_RX_1 : in std_logic; + FFC_PCIE_RX_2 : in std_logic; + FFC_PCIE_RX_3 : in std_logic; + + FFC_SD_0 : in std_logic; + FFC_SD_1 : in std_logic; + FFC_SD_2 : in std_logic; + FFC_SD_3 : in std_logic; + + FFC_EN_CGA_0 : in std_logic; + FFC_EN_CGA_1 : in std_logic; + FFC_EN_CGA_2 : in std_logic; + FFC_EN_CGA_3 : in std_logic; + + FFC_ALIGN_EN_0 : in std_logic; + FFC_ALIGN_EN_1 : in std_logic; + FFC_ALIGN_EN_2 : in std_logic; + FFC_ALIGN_EN_3 : in std_logic; + + FFC_AB_RESET : in std_logic; + FFC_CD_RESET : in std_logic; + + FFS_LS_STATUS_0 : out std_logic; + FFS_LS_STATUS_1 : out std_logic; + FFS_LS_STATUS_2 : out std_logic; + FFS_LS_STATUS_3 : out std_logic; + + FFS_AB_STATUS : out std_logic; + FFS_CD_STATUS : out std_logic; + + FFS_AB_ALIGNED : out std_logic; + FFS_CD_ALIGNED : out std_logic; + + FFS_AB_FAILED : out std_logic; + FFS_CD_FAILED : out std_logic; + + FFS_RLOS_LO0 : out std_logic; + FFS_RLOS_LO1 : out std_logic; + FFS_RLOS_LO2 : out std_logic; + FFS_RLOS_LO3 : out std_logic; + + FFC_FB_LB_0 : in std_logic; + FFC_FB_LB_1 : in std_logic; + FFC_FB_LB_2 : in std_logic; + FFC_FB_LB_3 : in std_logic; + + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + + FFS_CC_ORUN_0 : out std_logic; + FFS_CC_ORUN_1 : out std_logic; + FFS_CC_ORUN_2 : out std_logic; + FFS_CC_ORUN_3 : out std_logic; + + FFS_CC_URUN_0 : out std_logic; + FFS_CC_URUN_1 : out std_logic; + FFS_CC_URUN_2 : out std_logic; + FFS_CC_URUN_3 : out std_logic; + + FFC_CK_CORE_TX : in std_logic; + FFC_CK_CORE_RX : in std_logic; + RDATAO_7 : out std_logic; + RDATAO_6 : out std_logic; + RDATAO_5 : out std_logic; + RDATAO_4 : out std_logic; + RDATAO_3 : out std_logic; + RDATAO_2 : out std_logic; + RDATAO_1 : out std_logic; + RDATAO_0 : out std_logic; + INTO : out std_logic; + + ADDRI_7 : in std_logic; + ADDRI_6 : in std_logic; + ADDRI_5 : in std_logic; + ADDRI_4 : in std_logic; + ADDRI_3 : in std_logic; + ADDRI_2 : in std_logic; + ADDRI_1 : in std_logic; + ADDRI_0 : in std_logic; + WDATAI_7 : in std_logic; + WDATAI_6 : in std_logic; + WDATAI_5 : in std_logic; + WDATAI_4 : in std_logic; + WDATAI_3 : in std_logic; + WDATAI_2 : in std_logic; + WDATAI_1 : in std_logic; + WDATAI_0 : in std_logic; + RDI : in std_logic; + WSTBI : in std_logic; + + CS_CHIF_0 : in std_logic; + CS_CHIF_1 : in std_logic; + CS_CHIF_2 : in std_logic; + CS_CHIF_3 : in std_logic; + CS_QIF : in std_logic; + + QUAD_ID_1 : in std_logic; + QUAD_ID_0 : in std_logic; + + FF_SYSCLK_P1 : out std_logic; + + FF_SYSCLK0 : out std_logic; + FF_SYSCLK1 : out std_logic; + FF_SYSCLK2 : out std_logic; + FF_SYSCLK3 : out std_logic; + + FF_RXCLK_P1 : out std_logic; + FF_RXCLK_P2 : out std_logic; + + FF_RXCLK0 : out std_logic; + FF_RXCLK1 : out std_logic; + FF_RXCLK2 : out std_logic; + FF_RXCLK3 : out std_logic; + + QUAD_CLK : out std_logic; + + GRP_CLK_P1_3 : in std_logic; + GRP_CLK_P1_2 : in std_logic; + GRP_CLK_P1_1 : in std_logic; + GRP_CLK_P1_0 : in std_logic; + + GRP_CLK_P2_3 : in std_logic; + GRP_CLK_P2_2 : in std_logic; + GRP_CLK_P2_1 : in std_logic; + GRP_CLK_P2_0 : in std_logic; + + GRP_START_3 : in std_logic; + GRP_START_2 : in std_logic; + GRP_START_1 : in std_logic; + GRP_START_0 : in std_logic; + + GRP_DONE_3 : in std_logic; + GRP_DONE_2 : in std_logic; + GRP_DONE_1 : in std_logic; + GRP_DONE_0 : in std_logic; + + GRP_DESKEW_ERROR_3 : in std_logic; + GRP_DESKEW_ERROR_2 : in std_logic; + GRP_DESKEW_ERROR_1 : in std_logic; + GRP_DESKEW_ERROR_0 : in std_logic; + + IQA_START_LS : out std_logic; + IQA_DONE_LS : out std_logic; + IQA_AND_FP1_LS : out std_logic; + IQA_AND_FP0_LS : out std_logic; + IQA_OR_FP1_LS : out std_logic; + IQA_OR_FP0_LS : out std_logic; + IQA_RST_N : out std_logic; + + FF_TCLK0 : in std_logic; + FF_TCLK1 : in std_logic; + FF_TCLK2 : in std_logic; + FF_TCLK3 : in std_logic; + + FF_RCLK0 : in std_logic; + FF_RCLK1 : in std_logic; + FF_RCLK2 : in std_logic; + FF_RCLK3 : in std_logic; + TCK_FMACP : in std_logic; + + FF_TXD_0_23 : in std_logic; + FF_TXD_0_22 : in std_logic; + FF_TXD_0_21 : in std_logic; + FF_TXD_0_20 : in std_logic; + FF_TXD_0_19 : in std_logic; + FF_TXD_0_18 : in std_logic; + FF_TXD_0_17 : in std_logic; + FF_TXD_0_16 : in std_logic; + FF_TXD_0_15 : in std_logic; + FF_TXD_0_14 : in std_logic; + FF_TXD_0_13 : in std_logic; + FF_TXD_0_12 : in std_logic; + FF_TXD_0_11 : in std_logic; + FF_TXD_0_10 : in std_logic; + FF_TXD_0_9 : in std_logic; + FF_TXD_0_8 : in std_logic; + FF_TXD_0_7 : in std_logic; + FF_TXD_0_6 : in std_logic; + FF_TXD_0_5 : in std_logic; + FF_TXD_0_4 : in std_logic; + FF_TXD_0_3 : in std_logic; + FF_TXD_0_2 : in std_logic; + FF_TXD_0_1 : in std_logic; + FF_TXD_0_0 : in std_logic; + FB_RXD_0_23 : out std_logic; + FB_RXD_0_22 : out std_logic; + FB_RXD_0_21 : out std_logic; + FB_RXD_0_20 : out std_logic; + FB_RXD_0_19 : out std_logic; + FB_RXD_0_18 : out std_logic; + FB_RXD_0_17 : out std_logic; + FB_RXD_0_16 : out std_logic; + FB_RXD_0_15 : out std_logic; + FB_RXD_0_14 : out std_logic; + FB_RXD_0_13 : out std_logic; + FB_RXD_0_12 : out std_logic; + FB_RXD_0_11 : out std_logic; + FB_RXD_0_10 : out std_logic; + FB_RXD_0_9 : out std_logic; + FB_RXD_0_8 : out std_logic; + FB_RXD_0_7 : out std_logic; + FB_RXD_0_6 : out std_logic; + FB_RXD_0_5 : out std_logic; + FB_RXD_0_4 : out std_logic; + FB_RXD_0_3 : out std_logic; + FB_RXD_0_2 : out std_logic; + FB_RXD_0_1 : out std_logic; + FB_RXD_0_0 : out std_logic; + FF_TXD_1_23 : in std_logic; + FF_TXD_1_22 : in std_logic; + FF_TXD_1_21 : in std_logic; + FF_TXD_1_20 : in std_logic; + FF_TXD_1_19 : in std_logic; + FF_TXD_1_18 : in std_logic; + FF_TXD_1_17 : in std_logic; + FF_TXD_1_16 : in std_logic; + FF_TXD_1_15 : in std_logic; + FF_TXD_1_14 : in std_logic; + FF_TXD_1_13 : in std_logic; + FF_TXD_1_12 : in std_logic; + FF_TXD_1_11 : in std_logic; + FF_TXD_1_10 : in std_logic; + FF_TXD_1_9 : in std_logic; + FF_TXD_1_8 : in std_logic; + FF_TXD_1_7 : in std_logic; + FF_TXD_1_6 : in std_logic; + FF_TXD_1_5 : in std_logic; + FF_TXD_1_4 : in std_logic; + FF_TXD_1_3 : in std_logic; + FF_TXD_1_2 : in std_logic; + FF_TXD_1_1 : in std_logic; + FF_TXD_1_0 : in std_logic; + FB_RXD_1_23 : out std_logic; + FB_RXD_1_22 : out std_logic; + FB_RXD_1_21 : out std_logic; + FB_RXD_1_20 : out std_logic; + FB_RXD_1_19 : out std_logic; + FB_RXD_1_18 : out std_logic; + FB_RXD_1_17 : out std_logic; + FB_RXD_1_16 : out std_logic; + FB_RXD_1_15 : out std_logic; + FB_RXD_1_14 : out std_logic; + FB_RXD_1_13 : out std_logic; + FB_RXD_1_12 : out std_logic; + FB_RXD_1_11 : out std_logic; + FB_RXD_1_10 : out std_logic; + FB_RXD_1_9 : out std_logic; + FB_RXD_1_8 : out std_logic; + FB_RXD_1_7 : out std_logic; + FB_RXD_1_6 : out std_logic; + FB_RXD_1_5 : out std_logic; + FB_RXD_1_4 : out std_logic; + FB_RXD_1_3 : out std_logic; + FB_RXD_1_2 : out std_logic; + FB_RXD_1_1 : out std_logic; + FB_RXD_1_0 : out std_logic; + FF_TXD_2_23 : in std_logic; + FF_TXD_2_22 : in std_logic; + FF_TXD_2_21 : in std_logic; + FF_TXD_2_20 : in std_logic; + FF_TXD_2_19 : in std_logic; + FF_TXD_2_18 : in std_logic; + FF_TXD_2_17 : in std_logic; + FF_TXD_2_16 : in std_logic; + FF_TXD_2_15 : in std_logic; + FF_TXD_2_14 : in std_logic; + FF_TXD_2_13 : in std_logic; + FF_TXD_2_12 : in std_logic; + FF_TXD_2_11 : in std_logic; + FF_TXD_2_10 : in std_logic; + FF_TXD_2_9 : in std_logic; + FF_TXD_2_8 : in std_logic; + FF_TXD_2_7 : in std_logic; + FF_TXD_2_6 : in std_logic; + FF_TXD_2_5 : in std_logic; + FF_TXD_2_4 : in std_logic; + FF_TXD_2_3 : in std_logic; + FF_TXD_2_2 : in std_logic; + FF_TXD_2_1 : in std_logic; + FF_TXD_2_0 : in std_logic; + FB_RXD_2_23 : out std_logic; + FB_RXD_2_22 : out std_logic; + FB_RXD_2_21 : out std_logic; + FB_RXD_2_20 : out std_logic; + FB_RXD_2_19 : out std_logic; + FB_RXD_2_18 : out std_logic; + FB_RXD_2_17 : out std_logic; + FB_RXD_2_16 : out std_logic; + FB_RXD_2_15 : out std_logic; + FB_RXD_2_14 : out std_logic; + FB_RXD_2_13 : out std_logic; + FB_RXD_2_12 : out std_logic; + FB_RXD_2_11 : out std_logic; + FB_RXD_2_10 : out std_logic; + FB_RXD_2_9 : out std_logic; + FB_RXD_2_8 : out std_logic; + FB_RXD_2_7 : out std_logic; + FB_RXD_2_6 : out std_logic; + FB_RXD_2_5 : out std_logic; + FB_RXD_2_4 : out std_logic; + FB_RXD_2_3 : out std_logic; + FB_RXD_2_2 : out std_logic; + FB_RXD_2_1 : out std_logic; + FB_RXD_2_0 : out std_logic; + FF_TXD_3_23 : in std_logic; + FF_TXD_3_22 : in std_logic; + FF_TXD_3_21 : in std_logic; + FF_TXD_3_20 : in std_logic; + FF_TXD_3_19 : in std_logic; + FF_TXD_3_18 : in std_logic; + FF_TXD_3_17 : in std_logic; + FF_TXD_3_16 : in std_logic; + FF_TXD_3_15 : in std_logic; + FF_TXD_3_14 : in std_logic; + FF_TXD_3_13 : in std_logic; + FF_TXD_3_12 : in std_logic; + FF_TXD_3_11 : in std_logic; + FF_TXD_3_10 : in std_logic; + FF_TXD_3_9 : in std_logic; + FF_TXD_3_8 : in std_logic; + FF_TXD_3_7 : in std_logic; + FF_TXD_3_6 : in std_logic; + FF_TXD_3_5 : in std_logic; + FF_TXD_3_4 : in std_logic; + FF_TXD_3_3 : in std_logic; + FF_TXD_3_2 : in std_logic; + FF_TXD_3_1 : in std_logic; + FF_TXD_3_0 : in std_logic; + FB_RXD_3_23 : out std_logic; + FB_RXD_3_22 : out std_logic; + FB_RXD_3_21 : out std_logic; + FB_RXD_3_20 : out std_logic; + FB_RXD_3_19 : out std_logic; + FB_RXD_3_18 : out std_logic; + FB_RXD_3_17 : out std_logic; + FB_RXD_3_16 : out std_logic; + FB_RXD_3_15 : out std_logic; + FB_RXD_3_14 : out std_logic; + FB_RXD_3_13 : out std_logic; + FB_RXD_3_12 : out std_logic; + FB_RXD_3_11 : out std_logic; + FB_RXD_3_10 : out std_logic; + FB_RXD_3_9 : out std_logic; + FB_RXD_3_8 : out std_logic; + FB_RXD_3_7 : out std_logic; + FB_RXD_3_6 : out std_logic; + FB_RXD_3_5 : out std_logic; + FB_RXD_3_4 : out std_logic; + FB_RXD_3_3 : out std_logic; + FB_RXD_3_2 : out std_logic; + FB_RXD_3_1 : out std_logic; + FB_RXD_3_0 : out std_logic; + TCK_FMAC : out std_logic; + BS4PAD_0 : out std_logic; + BS4PAD_1 : out std_logic; + BS4PAD_2 : out std_logic; + BS4PAD_3 : out std_logic; + COUT_21 : out std_logic; + COUT_20 : out std_logic; + COUT_19 : out std_logic; + COUT_18 : out std_logic; + COUT_17 : out std_logic; + COUT_16 : out std_logic; + COUT_15 : out std_logic; + COUT_14 : out std_logic; + COUT_13 : out std_logic; + COUT_12 : out std_logic; + COUT_11 : out std_logic; + COUT_10 : out std_logic; + COUT_9 : out std_logic; + COUT_8 : out std_logic; + COUT_7 : out std_logic; + COUT_6 : out std_logic; + COUT_5 : out std_logic; + COUT_4 : out std_logic; + COUT_3 : out std_logic; + COUT_2 : out std_logic; + COUT_1 : out std_logic; + COUT_0 : out std_logic; + CIN_12 : in std_logic; + CIN_11 : in std_logic; + CIN_10 : in std_logic; + CIN_9 : in std_logic; + CIN_8 : in std_logic; + CIN_7 : in std_logic; + CIN_6 : in std_logic; + CIN_5 : in std_logic; + CIN_4 : in std_logic; + CIN_3 : in std_logic; + CIN_2 : in std_logic; + CIN_1 : in std_logic; + CIN_0 : in std_logic; + TESTCLK_MACO : in std_logic +); +end component; + +begin + +PCSA_sim_inst : PCSA_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINP0 => HDINP0, + HDINN0 => HDINN0, + HDINP1 => HDINP1, + HDINN1 => HDINN1, + HDINP2 => HDINP2, + HDINN2 => HDINN2, + HDINP3 => HDINP3, + HDINN3 => HDINN3, + HDOUTP0 => HDOUTP0, + HDOUTN0 => HDOUTN0, + HDOUTP1 => HDOUTP1, + HDOUTN1 => HDOUTN1, + HDOUTP2 => HDOUTP2, + HDOUTN2 => HDOUTN2, + HDOUTP3 => HDOUTP3, + HDOUTN3 => HDOUTN3, + REFCLKP => REFCLKP, + REFCLKN => REFCLKN, + RXREFCLKP => RXREFCLKP, + RXREFCLKN => RXREFCLKN, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0, + FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1, + FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2, + FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3, + FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0, + FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1, + FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2, + FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3, + FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0, + FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1, + FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2, + FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFC_PCIE_TX_0 => FFC_PCIE_TX_0, + FFC_PCIE_TX_1 => FFC_PCIE_TX_1, + FFC_PCIE_TX_2 => FFC_PCIE_TX_2, + FFC_PCIE_TX_3 => FFC_PCIE_TX_3, + FFC_PCIE_RX_0 => FFC_PCIE_RX_0, + FFC_PCIE_RX_1 => FFC_PCIE_RX_1, + FFC_PCIE_RX_2 => FFC_PCIE_RX_2, + FFC_PCIE_RX_3 => FFC_PCIE_RX_3, + FFC_SD_0 => FFC_SD_0, + FFC_SD_1 => FFC_SD_1, + FFC_SD_2 => FFC_SD_2, + FFC_SD_3 => FFC_SD_3, + FFC_EN_CGA_0 => FFC_EN_CGA_0, + FFC_EN_CGA_1 => FFC_EN_CGA_1, + FFC_EN_CGA_2 => FFC_EN_CGA_2, + FFC_EN_CGA_3 => FFC_EN_CGA_3, + FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0, + FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1, + FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2, + FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3, + FFC_AB_RESET => FFC_AB_RESET, + FFC_CD_RESET => FFC_CD_RESET, + FFS_LS_STATUS_0 => FFS_LS_STATUS_0, + FFS_LS_STATUS_1 => FFS_LS_STATUS_1, + FFS_LS_STATUS_2 => FFS_LS_STATUS_2, + FFS_LS_STATUS_3 => FFS_LS_STATUS_3, + FFS_AB_STATUS => FFS_AB_STATUS, + FFS_CD_STATUS => FFS_CD_STATUS, + FFS_AB_ALIGNED => FFS_AB_ALIGNED, + FFS_CD_ALIGNED => FFS_CD_ALIGNED, + FFS_AB_FAILED => FFS_AB_FAILED, + FFS_CD_FAILED => FFS_CD_FAILED, + FFS_RLOS_LO0 => FFS_RLOS_LO0, + FFS_RLOS_LO1 => FFS_RLOS_LO1, + FFS_RLOS_LO2 => FFS_RLOS_LO2, + FFS_RLOS_LO3 => FFS_RLOS_LO3, + FFC_FB_LB_0 => FFC_FB_LB_0, + FFC_FB_LB_1 => FFC_FB_LB_1, + FFC_FB_LB_2 => FFC_FB_LB_2, + FFC_FB_LB_3 => FFC_FB_LB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFS_CC_ORUN_0 => FFS_CC_ORUN_0, + FFS_CC_ORUN_1 => FFS_CC_ORUN_1, + FFS_CC_ORUN_2 => FFS_CC_ORUN_2, + FFS_CC_ORUN_3 => FFS_CC_ORUN_3, + FFS_CC_URUN_0 => FFS_CC_URUN_0, + FFS_CC_URUN_1 => FFS_CC_URUN_1, + FFS_CC_URUN_2 => FFS_CC_URUN_2, + FFS_CC_URUN_3 => FFS_CC_URUN_3, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + BS4PAD_0 => BS4PAD_0, + BS4PAD_1 => BS4PAD_1, + BS4PAD_2 => BS4PAD_2, + BS4PAD_3 => BS4PAD_3, + RDATAO_7 => RDATAO_7, + RDATAO_6 => RDATAO_6, + RDATAO_5 => RDATAO_5, + RDATAO_4 => RDATAO_4, + RDATAO_3 => RDATAO_3, + RDATAO_2 => RDATAO_2, + RDATAO_1 => RDATAO_1, + RDATAO_0 => RDATAO_0, + INTO => INTO, + ADDRI_7 => ADDRI_7, + ADDRI_6 => ADDRI_6, + ADDRI_5 => ADDRI_5, + ADDRI_4 => ADDRI_4, + ADDRI_3 => ADDRI_3, + ADDRI_2 => ADDRI_2, + ADDRI_1 => ADDRI_1, + ADDRI_0 => ADDRI_0, + WDATAI_7 => WDATAI_7, + WDATAI_6 => WDATAI_6, + WDATAI_5 => WDATAI_5, + WDATAI_4 => WDATAI_4, + WDATAI_3 => WDATAI_3, + WDATAI_2 => WDATAI_2, + WDATAI_1 => WDATAI_1, + WDATAI_0 => WDATAI_0, + RDI => RDI, + WSTBI => WSTBI, + CS_CHIF_0 => CS_CHIF_0, + CS_CHIF_1 => CS_CHIF_1, + CS_CHIF_2 => CS_CHIF_2, + CS_CHIF_3 => CS_CHIF_3, + CS_QIF => CS_QIF, + QUAD_ID_1 => QUAD_ID_1, + QUAD_ID_0 => QUAD_ID_0, + FF_SYSCLK_P1 => FF_SYSCLK_P1, + FF_SYSCLK0 => FF_SYSCLK0, + FF_SYSCLK1 => FF_SYSCLK1, + FF_SYSCLK2 => FF_SYSCLK2, + FF_SYSCLK3 => FF_SYSCLK3, + FF_RXCLK_P1 => FF_RXCLK_P1, + FF_RXCLK_P2 => FF_RXCLK_P2, + FF_RXCLK0 => FF_RXCLK0, + FF_RXCLK1 => FF_RXCLK1, + FF_RXCLK2 => FF_RXCLK2, + FF_RXCLK3 => FF_RXCLK3, + QUAD_CLK => QUAD_CLK, + GRP_CLK_P1_3 => GRP_CLK_P1_3, + GRP_CLK_P1_2 => GRP_CLK_P1_2, + GRP_CLK_P1_1 => GRP_CLK_P1_1, + GRP_CLK_P1_0 => GRP_CLK_P1_0, + GRP_CLK_P2_3 => GRP_CLK_P2_3, + GRP_CLK_P2_2 => GRP_CLK_P2_2, + GRP_CLK_P2_1 => GRP_CLK_P2_1, + GRP_CLK_P2_0 => GRP_CLK_P2_0, + GRP_START_3 => GRP_START_3, + GRP_START_2 => GRP_START_2, + GRP_START_1 => GRP_START_1, + GRP_START_0 => GRP_START_0, + GRP_DONE_3 => GRP_DONE_3, + GRP_DONE_2 => GRP_DONE_2, + GRP_DONE_1 => GRP_DONE_1, + GRP_DONE_0 => GRP_DONE_0, + GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3, + GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2, + GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1, + GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0, + IQA_START_LS => IQA_START_LS, + IQA_DONE_LS => IQA_DONE_LS, + IQA_AND_FP1_LS => IQA_AND_FP1_LS, + IQA_AND_FP0_LS => IQA_AND_FP0_LS, + IQA_OR_FP1_LS => IQA_OR_FP1_LS, + IQA_OR_FP0_LS => IQA_OR_FP0_LS, + IQA_RST_N => IQA_RST_N, + FF_TCLK0 => FF_TCLK0, + FF_TCLK1 => FF_TCLK1, + FF_TCLK2 => FF_TCLK2, + FF_TCLK3 => FF_TCLK3, + FF_RCLK0 => FF_RCLK0, + FF_RCLK1 => FF_RCLK1, + FF_RCLK2 => FF_RCLK2, + FF_RCLK3 => FF_RCLK3, + TCK_FMACP => TCK_FMACP, + FF_TXD_0_23 => FF_TXD_0_23, + FF_TXD_0_22 => FF_TXD_0_22, + FF_TXD_0_21 => FF_TXD_0_21, + FF_TXD_0_20 => FF_TXD_0_20, + FF_TXD_0_19 => FF_TXD_0_19, + FF_TXD_0_18 => FF_TXD_0_18, + FF_TXD_0_17 => FF_TXD_0_17, + FF_TXD_0_16 => FF_TXD_0_16, + FF_TXD_0_15 => FF_TXD_0_15, + FF_TXD_0_14 => FF_TXD_0_14, + FF_TXD_0_13 => FF_TXD_0_13, + FF_TXD_0_12 => FF_TXD_0_12, + FF_TXD_0_11 => FF_TXD_0_11, + FF_TXD_0_10 => FF_TXD_0_10, + FF_TXD_0_9 => FF_TXD_0_9, + FF_TXD_0_8 => FF_TXD_0_8, + FF_TXD_0_7 => FF_TXD_0_7, + FF_TXD_0_6 => FF_TXD_0_6, + FF_TXD_0_5 => FF_TXD_0_5, + FF_TXD_0_4 => FF_TXD_0_4, + FF_TXD_0_3 => FF_TXD_0_3, + FF_TXD_0_2 => FF_TXD_0_2, + FF_TXD_0_1 => FF_TXD_0_1, + FF_TXD_0_0 => FF_TXD_0_0, + FB_RXD_0_23 => FB_RXD_0_23, + FB_RXD_0_22 => FB_RXD_0_22, + FB_RXD_0_21 => FB_RXD_0_21, + FB_RXD_0_20 => FB_RXD_0_20, + FB_RXD_0_19 => FB_RXD_0_19, + FB_RXD_0_18 => FB_RXD_0_18, + FB_RXD_0_17 => FB_RXD_0_17, + FB_RXD_0_16 => FB_RXD_0_16, + FB_RXD_0_15 => FB_RXD_0_15, + FB_RXD_0_14 => FB_RXD_0_14, + FB_RXD_0_13 => FB_RXD_0_13, + FB_RXD_0_12 => FB_RXD_0_12, + FB_RXD_0_11 => FB_RXD_0_11, + FB_RXD_0_10 => FB_RXD_0_10, + FB_RXD_0_9 => FB_RXD_0_9, + FB_RXD_0_8 => FB_RXD_0_8, + FB_RXD_0_7 => FB_RXD_0_7, + FB_RXD_0_6 => FB_RXD_0_6, + FB_RXD_0_5 => FB_RXD_0_5, + FB_RXD_0_4 => FB_RXD_0_4, + FB_RXD_0_3 => FB_RXD_0_3, + FB_RXD_0_2 => FB_RXD_0_2, + FB_RXD_0_1 => FB_RXD_0_1, + FB_RXD_0_0 => FB_RXD_0_0, + FF_TXD_1_23 => FF_TXD_1_23, + FF_TXD_1_22 => FF_TXD_1_22, + FF_TXD_1_21 => FF_TXD_1_21, + FF_TXD_1_20 => FF_TXD_1_20, + FF_TXD_1_19 => FF_TXD_1_19, + FF_TXD_1_18 => FF_TXD_1_18, + FF_TXD_1_17 => FF_TXD_1_17, + FF_TXD_1_16 => FF_TXD_1_16, + FF_TXD_1_15 => FF_TXD_1_15, + FF_TXD_1_14 => FF_TXD_1_14, + FF_TXD_1_13 => FF_TXD_1_13, + FF_TXD_1_12 => FF_TXD_1_12, + FF_TXD_1_11 => FF_TXD_1_11, + FF_TXD_1_10 => FF_TXD_1_10, + FF_TXD_1_9 => FF_TXD_1_9, + FF_TXD_1_8 => FF_TXD_1_8, + FF_TXD_1_7 => FF_TXD_1_7, + FF_TXD_1_6 => FF_TXD_1_6, + FF_TXD_1_5 => FF_TXD_1_5, + FF_TXD_1_4 => FF_TXD_1_4, + FF_TXD_1_3 => FF_TXD_1_3, + FF_TXD_1_2 => FF_TXD_1_2, + FF_TXD_1_1 => FF_TXD_1_1, + FF_TXD_1_0 => FF_TXD_1_0, + FB_RXD_1_23 => FB_RXD_1_23, + FB_RXD_1_22 => FB_RXD_1_22, + FB_RXD_1_21 => FB_RXD_1_21, + FB_RXD_1_20 => FB_RXD_1_20, + FB_RXD_1_19 => FB_RXD_1_19, + FB_RXD_1_18 => FB_RXD_1_18, + FB_RXD_1_17 => FB_RXD_1_17, + FB_RXD_1_16 => FB_RXD_1_16, + FB_RXD_1_15 => FB_RXD_1_15, + FB_RXD_1_14 => FB_RXD_1_14, + FB_RXD_1_13 => FB_RXD_1_13, + FB_RXD_1_12 => FB_RXD_1_12, + FB_RXD_1_11 => FB_RXD_1_11, + FB_RXD_1_10 => FB_RXD_1_10, + FB_RXD_1_9 => FB_RXD_1_9, + FB_RXD_1_8 => FB_RXD_1_8, + FB_RXD_1_7 => FB_RXD_1_7, + FB_RXD_1_6 => FB_RXD_1_6, + FB_RXD_1_5 => FB_RXD_1_5, + FB_RXD_1_4 => FB_RXD_1_4, + FB_RXD_1_3 => FB_RXD_1_3, + FB_RXD_1_2 => FB_RXD_1_2, + FB_RXD_1_1 => FB_RXD_1_1, + FB_RXD_1_0 => FB_RXD_1_0, + FF_TXD_2_23 => FF_TXD_2_23, + FF_TXD_2_22 => FF_TXD_2_22, + FF_TXD_2_21 => FF_TXD_2_21, + FF_TXD_2_20 => FF_TXD_2_20, + FF_TXD_2_19 => FF_TXD_2_19, + FF_TXD_2_18 => FF_TXD_2_18, + FF_TXD_2_17 => FF_TXD_2_17, + FF_TXD_2_16 => FF_TXD_2_16, + FF_TXD_2_15 => FF_TXD_2_15, + FF_TXD_2_14 => FF_TXD_2_14, + FF_TXD_2_13 => FF_TXD_2_13, + FF_TXD_2_12 => FF_TXD_2_12, + FF_TXD_2_11 => FF_TXD_2_11, + FF_TXD_2_10 => FF_TXD_2_10, + FF_TXD_2_9 => FF_TXD_2_9, + FF_TXD_2_8 => FF_TXD_2_8, + FF_TXD_2_7 => FF_TXD_2_7, + FF_TXD_2_6 => FF_TXD_2_6, + FF_TXD_2_5 => FF_TXD_2_5, + FF_TXD_2_4 => FF_TXD_2_4, + FF_TXD_2_3 => FF_TXD_2_3, + FF_TXD_2_2 => FF_TXD_2_2, + FF_TXD_2_1 => FF_TXD_2_1, + FF_TXD_2_0 => FF_TXD_2_0, + FB_RXD_2_23 => FB_RXD_2_23, + FB_RXD_2_22 => FB_RXD_2_22, + FB_RXD_2_21 => FB_RXD_2_21, + FB_RXD_2_20 => FB_RXD_2_20, + FB_RXD_2_19 => FB_RXD_2_19, + FB_RXD_2_18 => FB_RXD_2_18, + FB_RXD_2_17 => FB_RXD_2_17, + FB_RXD_2_16 => FB_RXD_2_16, + FB_RXD_2_15 => FB_RXD_2_15, + FB_RXD_2_14 => FB_RXD_2_14, + FB_RXD_2_13 => FB_RXD_2_13, + FB_RXD_2_12 => FB_RXD_2_12, + FB_RXD_2_11 => FB_RXD_2_11, + FB_RXD_2_10 => FB_RXD_2_10, + FB_RXD_2_9 => FB_RXD_2_9, + FB_RXD_2_8 => FB_RXD_2_8, + FB_RXD_2_7 => FB_RXD_2_7, + FB_RXD_2_6 => FB_RXD_2_6, + FB_RXD_2_5 => FB_RXD_2_5, + FB_RXD_2_4 => FB_RXD_2_4, + FB_RXD_2_3 => FB_RXD_2_3, + FB_RXD_2_2 => FB_RXD_2_2, + FB_RXD_2_1 => FB_RXD_2_1, + FB_RXD_2_0 => FB_RXD_2_0, + FF_TXD_3_23 => FF_TXD_3_23, + FF_TXD_3_22 => FF_TXD_3_22, + FF_TXD_3_21 => FF_TXD_3_21, + FF_TXD_3_20 => FF_TXD_3_20, + FF_TXD_3_19 => FF_TXD_3_19, + FF_TXD_3_18 => FF_TXD_3_18, + FF_TXD_3_17 => FF_TXD_3_17, + FF_TXD_3_16 => FF_TXD_3_16, + FF_TXD_3_15 => FF_TXD_3_15, + FF_TXD_3_14 => FF_TXD_3_14, + FF_TXD_3_13 => FF_TXD_3_13, + FF_TXD_3_12 => FF_TXD_3_12, + FF_TXD_3_11 => FF_TXD_3_11, + FF_TXD_3_10 => FF_TXD_3_10, + FF_TXD_3_9 => FF_TXD_3_9, + FF_TXD_3_8 => FF_TXD_3_8, + FF_TXD_3_7 => FF_TXD_3_7, + FF_TXD_3_6 => FF_TXD_3_6, + FF_TXD_3_5 => FF_TXD_3_5, + FF_TXD_3_4 => FF_TXD_3_4, + FF_TXD_3_3 => FF_TXD_3_3, + FF_TXD_3_2 => FF_TXD_3_2, + FF_TXD_3_1 => FF_TXD_3_1, + FF_TXD_3_0 => FF_TXD_3_0, + FB_RXD_3_23 => FB_RXD_3_23, + FB_RXD_3_22 => FB_RXD_3_22, + FB_RXD_3_21 => FB_RXD_3_21, + FB_RXD_3_20 => FB_RXD_3_20, + FB_RXD_3_19 => FB_RXD_3_19, + FB_RXD_3_18 => FB_RXD_3_18, + FB_RXD_3_17 => FB_RXD_3_17, + FB_RXD_3_16 => FB_RXD_3_16, + FB_RXD_3_15 => FB_RXD_3_15, + FB_RXD_3_14 => FB_RXD_3_14, + FB_RXD_3_13 => FB_RXD_3_13, + FB_RXD_3_12 => FB_RXD_3_12, + FB_RXD_3_11 => FB_RXD_3_11, + FB_RXD_3_10 => FB_RXD_3_10, + FB_RXD_3_9 => FB_RXD_3_9, + FB_RXD_3_8 => FB_RXD_3_8, + FB_RXD_3_7 => FB_RXD_3_7, + FB_RXD_3_6 => FB_RXD_3_6, + FB_RXD_3_5 => FB_RXD_3_5, + FB_RXD_3_4 => FB_RXD_3_4, + FB_RXD_3_3 => FB_RXD_3_3, + FB_RXD_3_2 => FB_RXD_3_2, + FB_RXD_3_1 => FB_RXD_3_1, + FB_RXD_3_0 => FB_RXD_3_0, + TCK_FMAC => TCK_FMAC, + COUT_21 => COUT_21, + COUT_20 => COUT_20, + COUT_19 => COUT_19, + COUT_18 => COUT_18, + COUT_17 => COUT_17, + COUT_16 => COUT_16, + COUT_15 => COUT_15, + COUT_14 => COUT_14, + COUT_13 => COUT_13, + COUT_12 => COUT_12, + COUT_11 => COUT_11, + COUT_10 => COUT_10, + COUT_9 => COUT_9, + COUT_8 => COUT_8, + COUT_7 => COUT_7, + COUT_6 => COUT_6, + COUT_5 => COUT_5, + COUT_4 => COUT_4, + COUT_3 => COUT_3, + COUT_2 => COUT_2, + COUT_1 => COUT_1, + COUT_0 => COUT_0, + CIN_12 => CIN_12, + CIN_11 => CIN_11, + CIN_10 => CIN_10, + CIN_9 => CIN_9, + CIN_8 => CIN_8, + CIN_7 => CIN_7, + CIN_6 => CIN_6, + CIN_5 => CIN_5, + CIN_4 => CIN_4, + CIN_3 => CIN_3, + CIN_2 => CIN_2, + CIN_1 => CIN_1, + CIN_0 => CIN_0, + TESTCLK_MACO => TESTCLK_MACO +); + +end PCSA_arch; + +--synopsys translate_on + +--synopsys translate_off +library SC; +use SC.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + + +entity serdes_gbe_0_100_ext is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt"); + port ( +-- serdes clk pins -- + refclkp, refclkn : in std_logic; + rxa_pclk, rxb_pclk : out std_logic; + hdinp_0, hdinn_0 : in std_logic; + hdoutp_0, hdoutn_0 : out std_logic; + tclk_0, rclk_0 : in std_logic; + tx_rst_0, rx_rst_0 : in std_logic; + ref_0_sclk, rx_0_sclk : out std_logic; + txd_0 : in std_logic_vector (15 downto 0); + tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0); + rxd_0 : out std_logic_vector (15 downto 0); + rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0); + tx_crc_init_0 : in std_logic_vector (1 downto 0); + rx_crc_eop_0 : out std_logic_vector (1 downto 0); + word_align_en_0, mca_align_en_0, felb_0 : in std_logic; + lsm_en_0 : in std_logic; + lsm_status_0 : out std_logic; + + + + mca_resync_01 : in std_logic; + quad_rst, serdes_rst : in std_logic; + ref_pclk : out std_logic); + +end serdes_gbe_0_100_ext; + +architecture serdes_gbe_0_100_ext_arch of serdes_gbe_0_100_ext is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; + +component PCSA +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINP0 : in std_logic; + HDINN0 : in std_logic; + HDINP1 : in std_logic; + HDINN1 : in std_logic; + HDINP2 : in std_logic; + HDINN2 : in std_logic; + HDINP3 : in std_logic; + HDINN3 : in std_logic; + HDOUTP0 : out std_logic; + HDOUTN0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTP3 : out std_logic; + HDOUTN3 : out std_logic; + REFCLKP : in std_logic; + REFCLKN : in std_logic; + RXREFCLKP : in std_logic; + RXREFCLKN : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_MACRO_RST : in std_logic; + + FFC_LANE_TX_RST0 : in std_logic; + FFC_LANE_TX_RST1 : in std_logic; + FFC_LANE_TX_RST2 : in std_logic; + FFC_LANE_TX_RST3 : in std_logic; + + FFC_LANE_RX_RST0 : in std_logic; + FFC_LANE_RX_RST1 : in std_logic; + FFC_LANE_RX_RST2 : in std_logic; + FFC_LANE_RX_RST3 : in std_logic; + + FFC_PCIE_EI_EN_0 : in std_logic; + FFC_PCIE_EI_EN_1 : in std_logic; + FFC_PCIE_EI_EN_2 : in std_logic; + FFC_PCIE_EI_EN_3 : in std_logic; + + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + + FFC_PCIE_TX_0 : in std_logic; + FFC_PCIE_TX_1 : in std_logic; + FFC_PCIE_TX_2 : in std_logic; + FFC_PCIE_TX_3 : in std_logic; + + FFC_PCIE_RX_0 : in std_logic; + FFC_PCIE_RX_1 : in std_logic; + FFC_PCIE_RX_2 : in std_logic; + FFC_PCIE_RX_3 : in std_logic; + + FFC_SD_0 : in std_logic; + FFC_SD_1 : in std_logic; + FFC_SD_2 : in std_logic; + FFC_SD_3 : in std_logic; + + FFC_EN_CGA_0 : in std_logic; + FFC_EN_CGA_1 : in std_logic; + FFC_EN_CGA_2 : in std_logic; + FFC_EN_CGA_3 : in std_logic; + + FFC_ALIGN_EN_0 : in std_logic; + FFC_ALIGN_EN_1 : in std_logic; + FFC_ALIGN_EN_2 : in std_logic; + FFC_ALIGN_EN_3 : in std_logic; + + FFC_AB_RESET : in std_logic; + FFC_CD_RESET : in std_logic; + + FFS_LS_STATUS_0 : out std_logic; + FFS_LS_STATUS_1 : out std_logic; + FFS_LS_STATUS_2 : out std_logic; + FFS_LS_STATUS_3 : out std_logic; + + FFS_AB_STATUS : out std_logic; + FFS_CD_STATUS : out std_logic; + + FFS_AB_ALIGNED : out std_logic; + FFS_CD_ALIGNED : out std_logic; + + FFS_AB_FAILED : out std_logic; + FFS_CD_FAILED : out std_logic; + + FFS_RLOS_LO0 : out std_logic; + FFS_RLOS_LO1 : out std_logic; + FFS_RLOS_LO2 : out std_logic; + FFS_RLOS_LO3 : out std_logic; + + FFC_FB_LB_0 : in std_logic; + FFC_FB_LB_1 : in std_logic; + FFC_FB_LB_2 : in std_logic; + FFC_FB_LB_3 : in std_logic; + + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + + FFS_CC_ORUN_0 : out std_logic; + FFS_CC_ORUN_1 : out std_logic; + FFS_CC_ORUN_2 : out std_logic; + FFS_CC_ORUN_3 : out std_logic; + + FFS_CC_URUN_0 : out std_logic; + FFS_CC_URUN_1 : out std_logic; + FFS_CC_URUN_2 : out std_logic; + FFS_CC_URUN_3 : out std_logic; + + FFC_CK_CORE_TX : in std_logic; + FFC_CK_CORE_RX : in std_logic; + RDATAO_7 : out std_logic; + RDATAO_6 : out std_logic; + RDATAO_5 : out std_logic; + RDATAO_4 : out std_logic; + RDATAO_3 : out std_logic; + RDATAO_2 : out std_logic; + RDATAO_1 : out std_logic; + RDATAO_0 : out std_logic; + INTO : out std_logic; + + ADDRI_7 : in std_logic; + ADDRI_6 : in std_logic; + ADDRI_5 : in std_logic; + ADDRI_4 : in std_logic; + ADDRI_3 : in std_logic; + ADDRI_2 : in std_logic; + ADDRI_1 : in std_logic; + ADDRI_0 : in std_logic; + WDATAI_7 : in std_logic; + WDATAI_6 : in std_logic; + WDATAI_5 : in std_logic; + WDATAI_4 : in std_logic; + WDATAI_3 : in std_logic; + WDATAI_2 : in std_logic; + WDATAI_1 : in std_logic; + WDATAI_0 : in std_logic; + RDI : in std_logic; + WSTBI : in std_logic; + + CS_CHIF_0 : in std_logic; + CS_CHIF_1 : in std_logic; + CS_CHIF_2 : in std_logic; + CS_CHIF_3 : in std_logic; + CS_QIF : in std_logic; + + QUAD_ID_1 : in std_logic; + QUAD_ID_0 : in std_logic; + + FF_SYSCLK_P1 : out std_logic; + + FF_SYSCLK0 : out std_logic; + FF_SYSCLK1 : out std_logic; + FF_SYSCLK2 : out std_logic; + FF_SYSCLK3 : out std_logic; + + FF_RXCLK_P1 : out std_logic; + FF_RXCLK_P2 : out std_logic; + + FF_RXCLK0 : out std_logic; + FF_RXCLK1 : out std_logic; + FF_RXCLK2 : out std_logic; + FF_RXCLK3 : out std_logic; + + QUAD_CLK : out std_logic; + + GRP_CLK_P1_3 : in std_logic; + GRP_CLK_P1_2 : in std_logic; + GRP_CLK_P1_1 : in std_logic; + GRP_CLK_P1_0 : in std_logic; + + GRP_CLK_P2_3 : in std_logic; + GRP_CLK_P2_2 : in std_logic; + GRP_CLK_P2_1 : in std_logic; + GRP_CLK_P2_0 : in std_logic; + + GRP_START_3 : in std_logic; + GRP_START_2 : in std_logic; + GRP_START_1 : in std_logic; + GRP_START_0 : in std_logic; + + GRP_DONE_3 : in std_logic; + GRP_DONE_2 : in std_logic; + GRP_DONE_1 : in std_logic; + GRP_DONE_0 : in std_logic; + + GRP_DESKEW_ERROR_3 : in std_logic; + GRP_DESKEW_ERROR_2 : in std_logic; + GRP_DESKEW_ERROR_1 : in std_logic; + GRP_DESKEW_ERROR_0 : in std_logic; + + IQA_START_LS : out std_logic; + IQA_DONE_LS : out std_logic; + IQA_AND_FP1_LS : out std_logic; + IQA_AND_FP0_LS : out std_logic; + IQA_OR_FP1_LS : out std_logic; + IQA_OR_FP0_LS : out std_logic; + IQA_RST_N : out std_logic; + + FF_TCLK0 : in std_logic; + FF_TCLK1 : in std_logic; + FF_TCLK2 : in std_logic; + FF_TCLK3 : in std_logic; + + FF_RCLK0 : in std_logic; + FF_RCLK1 : in std_logic; + FF_RCLK2 : in std_logic; + FF_RCLK3 : in std_logic; + TCK_FMACP : in std_logic; + + FF_TXD_0_23 : in std_logic; + FF_TXD_0_22 : in std_logic; + FF_TXD_0_21 : in std_logic; + FF_TXD_0_20 : in std_logic; + FF_TXD_0_19 : in std_logic; + FF_TXD_0_18 : in std_logic; + FF_TXD_0_17 : in std_logic; + FF_TXD_0_16 : in std_logic; + FF_TXD_0_15 : in std_logic; + FF_TXD_0_14 : in std_logic; + FF_TXD_0_13 : in std_logic; + FF_TXD_0_12 : in std_logic; + FF_TXD_0_11 : in std_logic; + FF_TXD_0_10 : in std_logic; + FF_TXD_0_9 : in std_logic; + FF_TXD_0_8 : in std_logic; + FF_TXD_0_7 : in std_logic; + FF_TXD_0_6 : in std_logic; + FF_TXD_0_5 : in std_logic; + FF_TXD_0_4 : in std_logic; + FF_TXD_0_3 : in std_logic; + FF_TXD_0_2 : in std_logic; + FF_TXD_0_1 : in std_logic; + FF_TXD_0_0 : in std_logic; + FB_RXD_0_23 : out std_logic; + FB_RXD_0_22 : out std_logic; + FB_RXD_0_21 : out std_logic; + FB_RXD_0_20 : out std_logic; + FB_RXD_0_19 : out std_logic; + FB_RXD_0_18 : out std_logic; + FB_RXD_0_17 : out std_logic; + FB_RXD_0_16 : out std_logic; + FB_RXD_0_15 : out std_logic; + FB_RXD_0_14 : out std_logic; + FB_RXD_0_13 : out std_logic; + FB_RXD_0_12 : out std_logic; + FB_RXD_0_11 : out std_logic; + FB_RXD_0_10 : out std_logic; + FB_RXD_0_9 : out std_logic; + FB_RXD_0_8 : out std_logic; + FB_RXD_0_7 : out std_logic; + FB_RXD_0_6 : out std_logic; + FB_RXD_0_5 : out std_logic; + FB_RXD_0_4 : out std_logic; + FB_RXD_0_3 : out std_logic; + FB_RXD_0_2 : out std_logic; + FB_RXD_0_1 : out std_logic; + FB_RXD_0_0 : out std_logic; + FF_TXD_1_23 : in std_logic; + FF_TXD_1_22 : in std_logic; + FF_TXD_1_21 : in std_logic; + FF_TXD_1_20 : in std_logic; + FF_TXD_1_19 : in std_logic; + FF_TXD_1_18 : in std_logic; + FF_TXD_1_17 : in std_logic; + FF_TXD_1_16 : in std_logic; + FF_TXD_1_15 : in std_logic; + FF_TXD_1_14 : in std_logic; + FF_TXD_1_13 : in std_logic; + FF_TXD_1_12 : in std_logic; + FF_TXD_1_11 : in std_logic; + FF_TXD_1_10 : in std_logic; + FF_TXD_1_9 : in std_logic; + FF_TXD_1_8 : in std_logic; + FF_TXD_1_7 : in std_logic; + FF_TXD_1_6 : in std_logic; + FF_TXD_1_5 : in std_logic; + FF_TXD_1_4 : in std_logic; + FF_TXD_1_3 : in std_logic; + FF_TXD_1_2 : in std_logic; + FF_TXD_1_1 : in std_logic; + FF_TXD_1_0 : in std_logic; + FB_RXD_1_23 : out std_logic; + FB_RXD_1_22 : out std_logic; + FB_RXD_1_21 : out std_logic; + FB_RXD_1_20 : out std_logic; + FB_RXD_1_19 : out std_logic; + FB_RXD_1_18 : out std_logic; + FB_RXD_1_17 : out std_logic; + FB_RXD_1_16 : out std_logic; + FB_RXD_1_15 : out std_logic; + FB_RXD_1_14 : out std_logic; + FB_RXD_1_13 : out std_logic; + FB_RXD_1_12 : out std_logic; + FB_RXD_1_11 : out std_logic; + FB_RXD_1_10 : out std_logic; + FB_RXD_1_9 : out std_logic; + FB_RXD_1_8 : out std_logic; + FB_RXD_1_7 : out std_logic; + FB_RXD_1_6 : out std_logic; + FB_RXD_1_5 : out std_logic; + FB_RXD_1_4 : out std_logic; + FB_RXD_1_3 : out std_logic; + FB_RXD_1_2 : out std_logic; + FB_RXD_1_1 : out std_logic; + FB_RXD_1_0 : out std_logic; + FF_TXD_2_23 : in std_logic; + FF_TXD_2_22 : in std_logic; + FF_TXD_2_21 : in std_logic; + FF_TXD_2_20 : in std_logic; + FF_TXD_2_19 : in std_logic; + FF_TXD_2_18 : in std_logic; + FF_TXD_2_17 : in std_logic; + FF_TXD_2_16 : in std_logic; + FF_TXD_2_15 : in std_logic; + FF_TXD_2_14 : in std_logic; + FF_TXD_2_13 : in std_logic; + FF_TXD_2_12 : in std_logic; + FF_TXD_2_11 : in std_logic; + FF_TXD_2_10 : in std_logic; + FF_TXD_2_9 : in std_logic; + FF_TXD_2_8 : in std_logic; + FF_TXD_2_7 : in std_logic; + FF_TXD_2_6 : in std_logic; + FF_TXD_2_5 : in std_logic; + FF_TXD_2_4 : in std_logic; + FF_TXD_2_3 : in std_logic; + FF_TXD_2_2 : in std_logic; + FF_TXD_2_1 : in std_logic; + FF_TXD_2_0 : in std_logic; + FB_RXD_2_23 : out std_logic; + FB_RXD_2_22 : out std_logic; + FB_RXD_2_21 : out std_logic; + FB_RXD_2_20 : out std_logic; + FB_RXD_2_19 : out std_logic; + FB_RXD_2_18 : out std_logic; + FB_RXD_2_17 : out std_logic; + FB_RXD_2_16 : out std_logic; + FB_RXD_2_15 : out std_logic; + FB_RXD_2_14 : out std_logic; + FB_RXD_2_13 : out std_logic; + FB_RXD_2_12 : out std_logic; + FB_RXD_2_11 : out std_logic; + FB_RXD_2_10 : out std_logic; + FB_RXD_2_9 : out std_logic; + FB_RXD_2_8 : out std_logic; + FB_RXD_2_7 : out std_logic; + FB_RXD_2_6 : out std_logic; + FB_RXD_2_5 : out std_logic; + FB_RXD_2_4 : out std_logic; + FB_RXD_2_3 : out std_logic; + FB_RXD_2_2 : out std_logic; + FB_RXD_2_1 : out std_logic; + FB_RXD_2_0 : out std_logic; + FF_TXD_3_23 : in std_logic; + FF_TXD_3_22 : in std_logic; + FF_TXD_3_21 : in std_logic; + FF_TXD_3_20 : in std_logic; + FF_TXD_3_19 : in std_logic; + FF_TXD_3_18 : in std_logic; + FF_TXD_3_17 : in std_logic; + FF_TXD_3_16 : in std_logic; + FF_TXD_3_15 : in std_logic; + FF_TXD_3_14 : in std_logic; + FF_TXD_3_13 : in std_logic; + FF_TXD_3_12 : in std_logic; + FF_TXD_3_11 : in std_logic; + FF_TXD_3_10 : in std_logic; + FF_TXD_3_9 : in std_logic; + FF_TXD_3_8 : in std_logic; + FF_TXD_3_7 : in std_logic; + FF_TXD_3_6 : in std_logic; + FF_TXD_3_5 : in std_logic; + FF_TXD_3_4 : in std_logic; + FF_TXD_3_3 : in std_logic; + FF_TXD_3_2 : in std_logic; + FF_TXD_3_1 : in std_logic; + FF_TXD_3_0 : in std_logic; + FB_RXD_3_23 : out std_logic; + FB_RXD_3_22 : out std_logic; + FB_RXD_3_21 : out std_logic; + FB_RXD_3_20 : out std_logic; + FB_RXD_3_19 : out std_logic; + FB_RXD_3_18 : out std_logic; + FB_RXD_3_17 : out std_logic; + FB_RXD_3_16 : out std_logic; + FB_RXD_3_15 : out std_logic; + FB_RXD_3_14 : out std_logic; + FB_RXD_3_13 : out std_logic; + FB_RXD_3_12 : out std_logic; + FB_RXD_3_11 : out std_logic; + FB_RXD_3_10 : out std_logic; + FB_RXD_3_9 : out std_logic; + FB_RXD_3_8 : out std_logic; + FB_RXD_3_7 : out std_logic; + FB_RXD_3_6 : out std_logic; + FB_RXD_3_5 : out std_logic; + FB_RXD_3_4 : out std_logic; + FB_RXD_3_3 : out std_logic; + FB_RXD_3_2 : out std_logic; + FB_RXD_3_1 : out std_logic; + FB_RXD_3_0 : out std_logic; + TCK_FMAC : out std_logic; + BS4PAD_0 : out std_logic; + BS4PAD_1 : out std_logic; + BS4PAD_2 : out std_logic; + BS4PAD_3 : out std_logic; + COUT_21 : out std_logic; + COUT_20 : out std_logic; + COUT_19 : out std_logic; + COUT_18 : out std_logic; + COUT_17 : out std_logic; + COUT_16 : out std_logic; + COUT_15 : out std_logic; + COUT_14 : out std_logic; + COUT_13 : out std_logic; + COUT_12 : out std_logic; + COUT_11 : out std_logic; + COUT_10 : out std_logic; + COUT_9 : out std_logic; + COUT_8 : out std_logic; + COUT_7 : out std_logic; + COUT_6 : out std_logic; + COUT_5 : out std_logic; + COUT_4 : out std_logic; + COUT_3 : out std_logic; + COUT_2 : out std_logic; + COUT_1 : out std_logic; + COUT_0 : out std_logic; + CIN_12 : in std_logic; + CIN_11 : in std_logic; + CIN_10 : in std_logic; + CIN_9 : in std_logic; + CIN_8 : in std_logic; + CIN_7 : in std_logic; + CIN_6 : in std_logic; + CIN_5 : in std_logic; + CIN_4 : in std_logic; + CIN_3 : in std_logic; + CIN_2 : in std_logic; + CIN_1 : in std_logic; + CIN_0 : in std_logic; + TESTCLK_MACO : in std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE; + attribute CH0_RX_MAXRATE: string; + attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3"; + attribute CH1_RX_MAXRATE: string; + attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3"; + attribute CH2_RX_MAXRATE: string; + attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3"; + attribute CH3_RX_MAXRATE: string; + attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3"; + attribute CH0_TX_MAXRATE: string; + attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2"; + attribute CH1_TX_MAXRATE: string; + attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2"; + attribute CH2_TX_MAXRATE: string; + attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2"; + attribute CH3_TX_MAXRATE: string; + attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2"; + attribute AMP_BOOST: string; + attribute AMP_BOOST of PCSA_INST : label is "DISABLED"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN"; + +signal fpsc_vlo : std_logic := '0'; + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSA_INST : PCSA +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + REFCLKP => refclkp, + REFCLKN => refclkn, + RXREFCLKP => fpsc_vlo, + RXREFCLKN => fpsc_vlo, + FFC_CK_CORE_RX => fpsc_vlo, + FFC_CK_CORE_TX => fpsc_vlo, + CS_CHIF_0 => fpsc_vlo, + CS_CHIF_1 => fpsc_vlo, + CS_CHIF_2 => fpsc_vlo, + CS_CHIF_3 => fpsc_vlo, + CS_QIF => fpsc_vlo, + QUAD_ID_0 => fpsc_vlo, + QUAD_ID_1 => fpsc_vlo, + ADDRI_0 => fpsc_vlo, + ADDRI_1 => fpsc_vlo, + ADDRI_2 => fpsc_vlo, + ADDRI_3 => fpsc_vlo, + ADDRI_4 => fpsc_vlo, + ADDRI_5 => fpsc_vlo, + ADDRI_6 => fpsc_vlo, + ADDRI_7 => fpsc_vlo, + WDATAI_0 => fpsc_vlo, + WDATAI_1 => fpsc_vlo, + WDATAI_2 => fpsc_vlo, + WDATAI_3 => fpsc_vlo, + WDATAI_4 => fpsc_vlo, + WDATAI_5 => fpsc_vlo, + WDATAI_6 => fpsc_vlo, + WDATAI_7 => fpsc_vlo, + RDI => fpsc_vlo, + WSTBI => fpsc_vlo, + GRP_CLK_P1_0 => fpsc_vlo, + GRP_CLK_P1_1 => fpsc_vlo, + GRP_CLK_P1_2 => fpsc_vlo, + GRP_CLK_P1_3 => fpsc_vlo, + GRP_CLK_P2_0 => fpsc_vlo, + GRP_CLK_P2_1 => fpsc_vlo, + GRP_CLK_P2_2 => fpsc_vlo, + GRP_CLK_P2_3 => fpsc_vlo, + GRP_START_0 => fpsc_vlo, + GRP_START_1 => fpsc_vlo, + GRP_START_2 => fpsc_vlo, + GRP_START_3 => fpsc_vlo, + GRP_DONE_0 => fpsc_vlo, + GRP_DONE_1 => fpsc_vlo, + GRP_DONE_2 => fpsc_vlo, + GRP_DONE_3 => fpsc_vlo, + GRP_DESKEW_ERROR_0 => fpsc_vlo, + GRP_DESKEW_ERROR_1 => fpsc_vlo, + GRP_DESKEW_ERROR_2 => fpsc_vlo, + GRP_DESKEW_ERROR_3 => fpsc_vlo, +-- to sysbusa + RDATAO_0 => open, + RDATAO_1 => open, + RDATAO_2 => open, + RDATAO_3 => open, + RDATAO_4 => open, + RDATAO_5 => open, + RDATAO_6 => open, + RDATAO_7 => open, + INTO => open, + QUAD_CLK => open, + IQA_START_LS => open, + IQA_DONE_LS => open, + IQA_AND_FP1_LS => open, + IQA_AND_FP0_LS => open, + IQA_OR_FP1_LS => open, + IQA_OR_FP0_LS => open, + IQA_RST_N => open, + + FF_TXD_0_19 => txd_0(15), + FF_TXD_0_18 => txd_0(14), + FF_TXD_0_17 => txd_0(13), + FF_TXD_0_16 => txd_0(12), + FF_TXD_0_15 => txd_0(11), + FF_TXD_0_14 => txd_0(10), + FF_TXD_0_13 => txd_0(9), + FF_TXD_0_12 => txd_0(8), + FF_TXD_0_7 => txd_0(7), + FF_TXD_0_6 => txd_0(6), + FF_TXD_0_5 => txd_0(5), + FF_TXD_0_4 => txd_0(4), + FF_TXD_0_3 => txd_0(3), + FF_TXD_0_2 => txd_0(2), + FF_TXD_0_1 => txd_0(1), + FF_TXD_0_0 => txd_0(0), + FB_RXD_0_19 => rxd_0(15), + FB_RXD_0_18 => rxd_0(14), + FB_RXD_0_17 => rxd_0(13), + FB_RXD_0_16 => rxd_0(12), + FB_RXD_0_15 => rxd_0(11), + FB_RXD_0_14 => rxd_0(10), + FB_RXD_0_13 => rxd_0(9), + FB_RXD_0_12 => rxd_0(8), + FB_RXD_0_7 => rxd_0(7), + FB_RXD_0_6 => rxd_0(6), + FB_RXD_0_5 => rxd_0(5), + FB_RXD_0_4 => rxd_0(4), + FB_RXD_0_3 => rxd_0(3), + FB_RXD_0_2 => rxd_0(2), + FB_RXD_0_1 => rxd_0(1), + FB_RXD_0_0 => rxd_0(0), + + FF_TXD_0_20 => tx_k_0(1), + FF_TXD_0_8 => tx_k_0(0), + FB_RXD_0_20 => rx_k_0(1), + FB_RXD_0_8 => rx_k_0(0), + + FF_TXD_0_21 => tx_force_disp_0(1), + FF_TXD_0_9 => tx_force_disp_0(0), + + FF_TXD_0_22 => tx_disp_sel_0(1), + FF_TXD_0_10 => tx_disp_sel_0(0), + + FF_TXD_0_23 => tx_crc_init_0(1), + FF_TXD_0_11 => tx_crc_init_0(0), + + FB_RXD_0_21 => rx_disp_err_detect_0(1), + FB_RXD_0_9 => rx_disp_err_detect_0(0), + + FB_RXD_0_22 => rx_cv_detect_0(1), + FB_RXD_0_10 => rx_cv_detect_0(0), + + FB_RXD_0_23 => rx_crc_eop_0(1), + FB_RXD_0_11 => rx_crc_eop_0(0), + + FF_TXD_1_19 => fpsc_vlo, + FF_TXD_1_18 => fpsc_vlo, + FF_TXD_1_17 => fpsc_vlo, + FF_TXD_1_16 => fpsc_vlo, + FF_TXD_1_15 => fpsc_vlo, + FF_TXD_1_14 => fpsc_vlo, + FF_TXD_1_13 => fpsc_vlo, + FF_TXD_1_12 => fpsc_vlo, + FF_TXD_1_7 => fpsc_vlo, + FF_TXD_1_6 => fpsc_vlo, + FF_TXD_1_5 => fpsc_vlo, + FF_TXD_1_4 => fpsc_vlo, + FF_TXD_1_3 => fpsc_vlo, + FF_TXD_1_2 => fpsc_vlo, + FF_TXD_1_1 => fpsc_vlo, + FF_TXD_1_0 => fpsc_vlo, + FB_RXD_1_19 => open, + FB_RXD_1_18 => open, + FB_RXD_1_17 => open, + FB_RXD_1_16 => open, + FB_RXD_1_15 => open, + FB_RXD_1_14 => open, + FB_RXD_1_13 => open, + FB_RXD_1_12 => open, + FB_RXD_1_7 => open, + FB_RXD_1_6 => open, + FB_RXD_1_5 => open, + FB_RXD_1_4 => open, + FB_RXD_1_3 => open, + FB_RXD_1_2 => open, + FB_RXD_1_1 => open, + FB_RXD_1_0 => open, + + FF_TXD_1_20 => fpsc_vlo, + FF_TXD_1_8 => fpsc_vlo, + FB_RXD_1_20 => open, + FB_RXD_1_8 => open, + + FF_TXD_1_21 => fpsc_vlo, + FF_TXD_1_9 => fpsc_vlo, + + FF_TXD_1_22 => fpsc_vlo, + FF_TXD_1_10 => fpsc_vlo, + FF_TXD_1_23 => fpsc_vlo, + FF_TXD_1_11 => fpsc_vlo, + + FB_RXD_1_21 => open, + FB_RXD_1_9 => open, + + FB_RXD_1_22 => open, + FB_RXD_1_10 => open, + + FB_RXD_1_23 => open, + FB_RXD_1_11 => open, + + FF_TXD_2_19 => fpsc_vlo, + FF_TXD_2_18 => fpsc_vlo, + FF_TXD_2_17 => fpsc_vlo, + FF_TXD_2_16 => fpsc_vlo, + FF_TXD_2_15 => fpsc_vlo, + FF_TXD_2_14 => fpsc_vlo, + FF_TXD_2_13 => fpsc_vlo, + FF_TXD_2_12 => fpsc_vlo, + FF_TXD_2_7 => fpsc_vlo, + FF_TXD_2_6 => fpsc_vlo, + FF_TXD_2_5 => fpsc_vlo, + FF_TXD_2_4 => fpsc_vlo, + FF_TXD_2_3 => fpsc_vlo, + FF_TXD_2_2 => fpsc_vlo, + FF_TXD_2_1 => fpsc_vlo, + FF_TXD_2_0 => fpsc_vlo, + FB_RXD_2_19 => open, + FB_RXD_2_18 => open, + FB_RXD_2_17 => open, + FB_RXD_2_16 => open, + FB_RXD_2_15 => open, + FB_RXD_2_14 => open, + FB_RXD_2_13 => open, + FB_RXD_2_12 => open, + FB_RXD_2_7 => open, + FB_RXD_2_6 => open, + FB_RXD_2_5 => open, + FB_RXD_2_4 => open, + FB_RXD_2_3 => open, + FB_RXD_2_2 => open, + FB_RXD_2_1 => open, + FB_RXD_2_0 => open, + + FF_TXD_2_20 => fpsc_vlo, + FF_TXD_2_8 => fpsc_vlo, + FB_RXD_2_20 => open, + FB_RXD_2_8 => open, + + FF_TXD_2_21 => fpsc_vlo, + FF_TXD_2_9 => fpsc_vlo, + + FF_TXD_2_22 => fpsc_vlo, + FF_TXD_2_10 => fpsc_vlo, + FF_TXD_2_23 => fpsc_vlo, + FF_TXD_2_11 => fpsc_vlo, + + FB_RXD_2_21 => open, + FB_RXD_2_9 => open, + + FB_RXD_2_22 => open, + FB_RXD_2_10 => open, + + FB_RXD_2_23 => open, + FB_RXD_2_11 => open, + + FF_TXD_3_19 => fpsc_vlo, + FF_TXD_3_18 => fpsc_vlo, + FF_TXD_3_17 => fpsc_vlo, + FF_TXD_3_16 => fpsc_vlo, + FF_TXD_3_15 => fpsc_vlo, + FF_TXD_3_14 => fpsc_vlo, + FF_TXD_3_13 => fpsc_vlo, + FF_TXD_3_12 => fpsc_vlo, + FF_TXD_3_7 => fpsc_vlo, + FF_TXD_3_6 => fpsc_vlo, + FF_TXD_3_5 => fpsc_vlo, + FF_TXD_3_4 => fpsc_vlo, + FF_TXD_3_3 => fpsc_vlo, + FF_TXD_3_2 => fpsc_vlo, + FF_TXD_3_1 => fpsc_vlo, + FF_TXD_3_0 => fpsc_vlo, + FB_RXD_3_19 => open, + FB_RXD_3_18 => open, + FB_RXD_3_17 => open, + FB_RXD_3_16 => open, + FB_RXD_3_15 => open, + FB_RXD_3_14 => open, + FB_RXD_3_13 => open, + FB_RXD_3_12 => open, + FB_RXD_3_7 => open, + FB_RXD_3_6 => open, + FB_RXD_3_5 => open, + FB_RXD_3_4 => open, + FB_RXD_3_3 => open, + FB_RXD_3_2 => open, + FB_RXD_3_1 => open, + FB_RXD_3_0 => open, + + FF_TXD_3_20 => fpsc_vlo, + FF_TXD_3_8 => fpsc_vlo, + FB_RXD_3_20 => open, + FB_RXD_3_8 => open, + + FF_TXD_3_21 => fpsc_vlo, + FF_TXD_3_9 => fpsc_vlo, + + FF_TXD_3_22 => fpsc_vlo, + FF_TXD_3_10 => fpsc_vlo, + FF_TXD_3_23 => fpsc_vlo, + FF_TXD_3_11 => fpsc_vlo, + + FB_RXD_3_21 => open, + FB_RXD_3_9 => open, + + FB_RXD_3_22 => open, + FB_RXD_3_10 => open, + + FB_RXD_3_23 => open, + FB_RXD_3_11 => open, + + HDINP0 => hdinp_0, + HDINN0 => hdinn_0, + HDOUTP0 => hdoutp_0, + HDOUTN0 => hdoutn_0, + FF_SYSCLK0 => ref_0_sclk, + FF_RXCLK0 => rx_0_sclk, + FFC_LANE_TX_RST0 => tx_rst_0, + FFC_LANE_RX_RST0 => rx_rst_0, + FF_TCLK0 => tclk_0, + FF_RCLK0 => rclk_0, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + HDOUTP1 => open, + HDOUTN1 => open, + FF_SYSCLK1 => open, + FF_RXCLK1 => open, + FFC_LANE_TX_RST1 => fpsc_vlo, + FFC_LANE_RX_RST1 => fpsc_vlo, + FF_TCLK1 => fpsc_vlo, + FF_RCLK1 => fpsc_vlo, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + HDOUTP2 => open, + HDOUTN2 => open, + FF_SYSCLK2 => open, + FF_RXCLK2 => open, + FFC_LANE_TX_RST2 => fpsc_vlo, + FFC_LANE_RX_RST2 => fpsc_vlo, + FF_TCLK2 => fpsc_vlo, + FF_RCLK2 => fpsc_vlo, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + HDOUTP3 => open, + HDOUTN3 => open, + FF_SYSCLK3 => open, + FF_RXCLK3 => open, + FFC_LANE_TX_RST3 => fpsc_vlo, + FFC_LANE_RX_RST3 => fpsc_vlo, + FF_TCLK3 => fpsc_vlo, + FF_RCLK3 => fpsc_vlo, + + FFC_PCIE_EI_EN_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCIE_TX_0 => fpsc_vlo, + FFC_PCIE_RX_0 => fpsc_vlo, + FFS_PCIE_CON_0 => open, + FFS_PCIE_DONE_0 => open, + FFC_PCIE_EI_EN_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCIE_TX_1 => fpsc_vlo, + FFC_PCIE_RX_1 => fpsc_vlo, + FFS_PCIE_CON_1 => open, + FFS_PCIE_DONE_1 => open, + FFC_PCIE_EI_EN_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCIE_TX_2 => fpsc_vlo, + FFC_PCIE_RX_2 => fpsc_vlo, + FFS_PCIE_CON_2 => open, + FFS_PCIE_DONE_2 => open, + FFC_PCIE_EI_EN_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCIE_TX_3 => fpsc_vlo, + FFC_PCIE_RX_3 => fpsc_vlo, + FFS_PCIE_CON_3 => open, + FFS_PCIE_DONE_3 => open, + + FFC_SD_0 => lsm_en_0, + FFC_SD_1 => fpsc_vlo, + FFC_SD_2 => fpsc_vlo, + FFC_SD_3 => fpsc_vlo, + + FFC_EN_CGA_0 => word_align_en_0, + FFC_EN_CGA_1 => fpsc_vlo, + FFC_EN_CGA_2 => fpsc_vlo, + FFC_EN_CGA_3 => fpsc_vlo, + + FFC_ALIGN_EN_0 => mca_align_en_0, + FFC_ALIGN_EN_1 => fpsc_vlo, + FFC_ALIGN_EN_2 => fpsc_vlo, + FFC_ALIGN_EN_3 => fpsc_vlo, + + FFC_FB_LB_0 => felb_0, + FFC_FB_LB_1 => fpsc_vlo, + FFC_FB_LB_2 => fpsc_vlo, + FFC_FB_LB_3 => fpsc_vlo, + + FFS_LS_STATUS_0 => lsm_status_0, + FFS_LS_STATUS_1 => open, + FFS_LS_STATUS_2 => open, + FFS_LS_STATUS_3 => open, + + FFS_CC_ORUN_0 => open, + FFS_CC_URUN_0 => open, + FFS_CC_ORUN_1 => open, + FFS_CC_URUN_1 => open, + FFS_CC_ORUN_2 => open, + FFS_CC_URUN_2 => open, + FFS_CC_ORUN_3 => open, + FFS_CC_URUN_3 => open, + + FFC_AB_RESET => mca_resync_01, + + FFS_AB_STATUS => open, + FFS_AB_ALIGNED => open, + FFS_AB_FAILED => open, + + FFC_CD_RESET => fpsc_vlo, + FFS_CD_STATUS => open, + + FFS_CD_ALIGNED => open, + FFS_CD_FAILED => open, + BS4PAD_0 => open, + BS4PAD_1 => open, + BS4PAD_2 => open, + BS4PAD_3 => open, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + TCK_FMAC => open, + TCK_FMACP => fpsc_vlo, + FF_SYSCLK_P1 => ref_pclk, + FF_RXCLK_P1 => rxa_pclk, + FF_RXCLK_P2 => rxb_pclk, + FFC_QUAD_RST => quad_rst, + FFS_RLOS_LO0 => open, + FFS_RLOS_LO1 => open, + FFS_RLOS_LO2 => open, + FFS_RLOS_LO3 => open, + COUT_21 => open, + COUT_20 => open, + COUT_19 => open, + COUT_18 => open, + COUT_17 => open, + COUT_16 => open, + COUT_15 => open, + COUT_14 => open, + COUT_13 => open, + COUT_12 => open, + COUT_11 => open, + COUT_10 => open, + COUT_9 => open, + COUT_8 => open, + COUT_7 => open, + COUT_6 => open, + COUT_5 => open, + COUT_4 => open, + COUT_3 => open, + COUT_2 => open, + COUT_1 => open, + COUT_0 => open, + CIN_12 => fpsc_vlo, + CIN_11 => fpsc_vlo, + CIN_10 => fpsc_vlo, + CIN_9 => fpsc_vlo, + CIN_8 => fpsc_vlo, + CIN_7 => fpsc_vlo, + CIN_6 => fpsc_vlo, + CIN_5 => fpsc_vlo, + CIN_4 => fpsc_vlo, + CIN_3 => fpsc_vlo, + CIN_2 => fpsc_vlo, + CIN_1 => fpsc_vlo, + CIN_0 => fpsc_vlo, + TESTCLK_MACO => fpsc_vlo, + FFC_MACRO_RST => serdes_rst); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_0_100_ext_arch ; diff --git a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd index 91e0f75..3bce0be 100755 --- a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd +++ b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd @@ -103,6 +103,49 @@ port( ); end component serdes_gbe_0_100; +component serdes_gbe_0_100_ext is +generic( + USER_CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt" +); +port( + refclkp : in std_logic; + refclkn : in std_logic; + rxrefclk : in std_logic; + refclk : in std_logic; + rxa_pclk : out std_logic; + rxb_pclk : out std_logic; + hdinp_0 : in std_logic; + hdinn_0 : in std_logic; + hdoutp_0 : out std_logic; + hdoutn_0 : out std_logic; + tclk_0 : in std_logic; + rclk_0 : in std_logic; + tx_rst_0 : in std_logic; + rx_rst_0 : in std_logic; + ref_0_sclk : out std_logic; + rx_0_sclk : out std_logic; + txd_0 : in std_logic_vector(15 downto 0); + tx_k_0 : in std_logic_vector(1 downto 0); + tx_force_disp_0 : in std_logic_vector(1 downto 0); + tx_disp_sel_0 : in std_logic_vector(1 downto 0); + rxd_0 : out std_logic_vector(15 downto 0); + rx_k_0 : out std_logic_vector(1 downto 0); + rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); + rx_cv_detect_0 : out std_logic_vector(1 downto 0); + tx_crc_init_0 : in std_logic_vector(1 downto 0); + rx_crc_eop_0 : out std_logic_vector(1 downto 0); + word_align_en_0 : in std_logic; + mca_align_en_0 : in std_logic; + felb_0 : in std_logic; + lsm_en_0 : in std_logic; + lsm_status_0 : out std_logic; + mca_resync_01 : in std_logic; + quad_rst : in std_logic; + serdes_rst : in std_logic; + ref_pclk : out std_logic +); +end component; + component serdes_gbe_0_200 is generic( USER_CONFIG_FILE : String := "serdes_gbe_0_200.txt" @@ -227,6 +270,7 @@ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); -- sys signal buf_med_dataready_out : std_logic; -- sysclk signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); -- sysclk signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); -- sysclk +signal buf_med_read_out : std_logic; signal last_rx : std_logic_vector(8 downto 0); --tx fifo signals @@ -238,6 +282,7 @@ signal last_fifo_tx_empty : std_logic; -- tx_halfclk signal fifo_tx_wr_en : std_logic; -- sysclk signal fifo_tx_din : std_logic_vector(17 downto 0); -- sysclk signal fifo_tx_full : std_logic; -- sysclk +signal fifo_tx_afull : std_logic; -- sysclk --link status @@ -267,7 +312,8 @@ signal send_reset_words : std_logic; -- sysclk signal send_reset_q : std_logic; -- tx_halfclk signal reset_i : std_logic; -- sysclk - +signal make_trbnet_reset_q : std_logic; +signal send_reset_words_q : std_logic; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -321,13 +367,17 @@ port map( -- receive komma character status bits for LSM THE_RX_K_SYNC: signal_sync -generic map( DEPTH => 2, WIDTH => 2 ) +generic map( DEPTH => 2, WIDTH => 4 ) port map( - RESET => reset_i, -- should not harm - D_IN => rx_k, - CLK0 => rx_halfclk, - CLK1 => sysclk, - D_OUT => rx_k_q + RESET => reset_i, -- should not harm + D_IN(1 downto 0) => rx_k, + D_IN(2) => make_trbnet_reset, + D_IN(3) => send_reset_words, + CLK0 => rx_halfclk, + CLK1 => sysclk, + D_OUT(1 downto 0) => rx_k_q, + D_OUT(2) => make_trbnet_reset_q, + D_OUT(3) => send_reset_words_q ); -- Delay for ALLOW signals @@ -429,7 +479,7 @@ gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO refclkn => SD_REFCLK_N_IN, -- not used here rxrefclk => CLK, -- raw 200MHz clock refclk => CLK, -- raw 200MHz clock - rxa_pclk => open, --rx_halfclk, -- clock multiplier set by data bus width + rxa_pclk => rx_halfclk, -- clock multiplier set by data bus width rxb_pclk => open, hdinp_0 => SD_RXD_P_IN, -- SerDes I/O hdinn_0 => SD_RXD_N_IN, -- SerDes I/O @@ -439,8 +489,8 @@ gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO rclk_0 => rx_halfclk, -- 100MHz tx_rst_0 => '0', --JM101206 lane_rst, -- async reset rx_rst_0 => '0', --lane_rst, -- async reset --reset when sd_los=0 and disp_err=1 or cv=1 - ref_0_sclk => tx_halfclk, - rx_0_sclk => rx_halfclk, + ref_0_sclk => open, --tx_halfclk, + rx_0_sclk => open, --rx_halfclk, txd_0 => tx_data, tx_k_0 => tx_k, tx_force_disp_0 => b"00", -- BUGBUG @@ -459,7 +509,7 @@ gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO mca_resync_01 => '0', -- not needed quad_rst => '0', -- hands off - kills registers! serdes_rst => '0', --JM101203 quad_rst, -- unknown if will work - ref_pclk => open --tx_halfclk -- clock multiplier set by data bus width + ref_pclk => tx_halfclk -- clock multiplier set by data bus width ); end generate; @@ -505,13 +555,13 @@ gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YE end generate; gen_serdes_0_100_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_NO generate - THE_SERDES: serdes_100_ext + THE_SERDES: serdes_gbe_0_100_ext port map( - refclkp => SD_REFCLK_P_IN, -- not used here - refclkn => SD_REFCLK_N_IN, -- not used here - rxrefclk => CLK, -- raw 200MHz clock - refclk => CLK, -- raw 200MHz clock - rxa_pclk => open, --rx_halfclk, -- clock multiplier set by data bus width + refclkp => SD_REFCLK_P_IN, + refclkn => SD_REFCLK_N_IN, + rxrefclk => '0', -- raw 100MHz clock + refclk => '0', -- raw 100MHz clock + rxa_pclk => rx_halfclk, -- clock multiplier set by data bus width rxb_pclk => open, hdinp_0 => SD_RXD_P_IN, -- SerDes I/O hdinn_0 => SD_RXD_N_IN, -- SerDes I/O @@ -521,8 +571,8 @@ gen_serdes_0_100_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = rclk_0 => rx_halfclk, -- 100MHz tx_rst_0 => '0', --JM101206 lane_rst, -- async reset rx_rst_0 => '0', --lane_rst, -- async reset --SM: reset when sd_los=0 and disp_err=1 or cv=1 - ref_0_sclk => tx_halfclk, - rx_0_sclk => rx_halfclk, + ref_0_sclk => open,--tx_halfclk, + rx_0_sclk => open,--rx_halfclk, txd_0 => tx_data, tx_k_0 => tx_k, tx_force_disp_0 => b"00", -- BUGBUG @@ -541,7 +591,7 @@ gen_serdes_0_100_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = mca_resync_01 => '0', -- not needed quad_rst => '0', -- hands off - kills registers! serdes_rst => '0', --JM101203 quad_rst, -- unknown if will work - ref_pclk => open --tx_halfclk -- clock multiplier set by data bus width + ref_pclk => tx_halfclk -- clock multiplier set by data bus width ); end generate; @@ -610,6 +660,7 @@ end process THE_RX_PACKETS_PROC; buf_med_data_out <= fifo_rx_dout(15 downto 0); -- OK buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_delay; -- OK buf_med_packet_num_out <= rx_counter; -- OK +buf_med_read_out <= tx_allow_delay and not fifo_tx_afull; -- OK -- Output registering THE_SYNC_PROC: process( SYSCLK ) @@ -625,7 +676,7 @@ begin end if; end process THE_SYNC_PROC; -MED_READ_OUT <= tx_allow_delay; -- OK +MED_READ_OUT <= buf_med_read_out; ------------------------------------------------------------------------- ------------------------------------------------------------------------- @@ -635,7 +686,7 @@ MED_READ_OUT <= tx_allow_delay; -- OK fifo_tx_reset <= reset_i or not tx_allow_delay; -- async signal, does not matter fifo_tx_din <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0)& MED_DATA_IN; -- OK -fifo_tx_wr_en <= MED_DATAREADY_IN and tx_allow_delay; -- OK +fifo_tx_wr_en <= MED_DATAREADY_IN and buf_med_read_out; -- OK fifo_tx_rd_en <= tx_allow_q; -- OK --TX Fifo & Data output to Serdes @@ -653,7 +704,8 @@ port map( write_clock_in => sysclk, write_enable_in => fifo_tx_wr_en, -- OK write_data_in => fifo_tx_din, -- OK - full_out => fifo_tx_full -- OK + full_out => fifo_tx_full, -- OK + almost_full_out => fifo_tx_afull ); -- empty -> read clock -- full -> write clock @@ -684,9 +736,9 @@ end process THE_SERDES_INPUT_PROC; ------------------------------------------------------------------------- -- Reset sequencer -THE_CNT_RESET_PROC: process( SYSCLK ) +THE_CNT_RESET_PROC: process( rx_halfclk ) begin - if rising_edge(SYSCLK) then + if rising_edge(rx_halfclk) then if( reset_i = '1' ) then -- OK send_reset_words <= '0'; make_trbnet_reset <= '0'; @@ -722,7 +774,7 @@ begin rx_led <= '0'; end if; - if ( tx_k(0) = '0' ) then + if (MED_DATAREADY_IN = '1' ) then tx_led <= '1'; elsif( led_counter = 0 ) then tx_led <= '0'; @@ -731,9 +783,9 @@ begin end if; end process THE_LED_PROC; -stat_op(15) <= send_reset_words; +stat_op(15) <= send_reset_words_q; stat_op(14) <= buf_stat_op(14); -stat_op(13) <= make_trbnet_reset; +stat_op(13) <= make_trbnet_reset_q; stat_op(12) <= '0'; stat_op(11) <= tx_led; --tx led stat_op(10) <= rx_led; --rx led @@ -755,8 +807,8 @@ stat_debug(30) <= rx_allow_delay; stat_debug(31) <= lane_rst; stat_debug(41 downto 32) <= (others => '0'); stat_debug(42) <= sysclk; -stat_debug(43) <= tx_halfclk; -stat_debug(44) <= rx_halfclk; +stat_debug(43) <= '0'; --tx_halfclk; +stat_debug(44) <= '0'; --rx_halfclk; stat_debug(46 downto 45) <= tx_k; stat_debug(47) <= tx_allow; stat_debug(59 downto 48) <= (others => '0'); diff --git a/special/trb_net_bridge_pcie_apl.vhd b/special/trb_net_bridge_pcie_apl.vhd new file mode 100644 index 0000000..8902010 --- /dev/null +++ b/special/trb_net_bridge_pcie_apl.vhd @@ -0,0 +1,399 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + + +entity trb_net_bridge_pcie_apl is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --TrbNet connect + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + + --Internal Data Bus + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(63 downto 0); + BUS_RDAT_OUT : out std_logic_vector(63 downto 0); + BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; +-- BUS_CTI_IN : in std_logic_vector(2 downto 0); + BUS_ACK_OUT : out std_logic; + + EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0); + SEND_RESET_OUT : out std_logic; + --DMA interface + + --Debug + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); +end entity; + + +--address range is 100 to FFF +-- (c is channel number * 2 + 1 if active part) + +--sending data. sending is released when 1c0 is written +--1c0 wr (3..0) Dtype (8) short transfer sender_control 9bit used +--1c1 wr target address sender_target 16bit used +--1c2 wr Errorbits sender_error 32bit used +--1c3 w sender data fifo sender_data 16bit used +--1c4 r sender fifo status (9..0 datacount, 16 full, 17 empty) +--1c5 wr Extended Trigger Information sender_trigger_information 16bit +--1cF r status (0)transfer running sender_status 1bit used + +--received data +--2c3 r receiver data fifo, (20..18)type receiver_data 16bit used +--2c4 r receiver fifo status (9..0 datacount, 16 full, 17 empty) + + +--3c0 (7..0) seq_num apis_tatus + +--700 - 71F DMA configuration + + + +architecture trb_net_bridge_pcie_apl_arch of trb_net_bridge_pcie_apl is + signal fifo_net_to_pci_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_dout : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_din : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); + signal fifo_net_to_pci_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_net_to_pci_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_read : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_write : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_valid_read : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_dout : std_logic_vector(18*2**c_MUX_WIDTH-1 downto 0); + signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); + signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); + type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(10 downto 0); + signal fifo_pci_to_net_data_count : data_count_t; + signal fifo_net_to_pci_data_count : data_count_t; + signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal sender_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + signal api_status : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); + + signal channel_address : integer range 0 to 7; +-- signal comb_channel_address : integer range 0 to 7; +-- signal last_CPU_ADDRESS : std_logic_vector(15 downto 0); + + signal next_CPU_DATA_OUT: std_logic_vector(31 downto 0); + signal buf_CPU_DATA_OUT : std_logic_vector(31 downto 0); + signal last_fifo_read : std_logic; + signal buf_CPU_DATAREADY_OUT : std_logic; + signal b_CPU_DATAREADY_OUT : std_logic; + + + signal bus_ack_i : std_logic; + signal bus_data_i : std_logic_vector(63 downto 0); + signal bus_rdat_i : std_logic_vector(63 downto 0); + signal bus_read_i : std_logic; + signal bus_write_i : std_logic; + signal bus_stb_rising : std_logic; + signal bus_stb_last : std_logic; + signal bus_write_last : std_logic; + signal bus_read_last : std_logic; + + signal send_reset_counter : unsigned(10 downto 0); + +begin + + + STAT(9 downto 0) <= BUS_ADDR_IN(9 downto 0); + STAT(10) <= bus_read_i; + STAT(11) <= bus_write_i; + STAT(12) <= bus_ack_i; + STAT(13) <= fifo_net_to_pci_read(1); + STAT(15 downto 14) <= BUS_WDAT_IN(1 downto 0); + STAT(16) <= fifo_pci_to_net_read(1); + STAT(17) <= fifo_pci_to_net_valid_read(1); + STAT(18) <= fifo_pci_to_net_empty(1); + STAT(19) <= fifo_pci_to_net_write(1); + STAT(20) <= APL_READ_IN(1); + STAT(21) <= fifo_pci_to_net_full(1); + STAT(22) <= RESET; + STAT(23) <= '0'; + STAT(24) <= fifo_net_to_pci_empty(1); + STAT(25) <= fifo_net_to_pci_read(1); + STAT(26) <= fifo_net_to_pci_write(1); + STAT(31 downto 27) <= (others => '0'); + +-------------------------------- +-- r/w registers +-------------------------------- + + process(CLK) + begin + if rising_edge(CLK) then + bus_stb_last <= BUS_STB_IN; + bus_read_last <= bus_read_i; + bus_write_last <= bus_write_i; + end if; + end process; + + bus_stb_rising <= BUS_STB_IN and not bus_stb_last; + bus_read_i <= not BUS_WE_IN and bus_stb_rising; + bus_write_i <= BUS_WE_IN and bus_stb_rising; + + channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 4))); +-- comb_channel_address <= conv_integer(CPU_ADDRESS(6 downto 4)); + + read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count, + fifo_pci_to_net_data_count, BUS_ADDR_IN, bus_read_i, bus_write_i, api_status, + fifo_net_to_pci_full, fifo_net_to_pci_empty, fifo_pci_to_net_full, fifo_pci_to_net_empty, + bus_data_i, BUS_WDAT_IN, channel_address, CTRL) + variable tmp : std_logic_vector(7 downto 0); + begin + bus_data_i <= (others => '0'); + tmp := BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0); + case tmp is + --middle nibble is dont care + when x"10" => + bus_data_i <= x"00000000" & sender_control(channel_address*32+31 downto channel_address*32); + when x"11" => + bus_data_i <= x"00000000" & sender_target(channel_address*32+31 downto channel_address*32); + when x"12" => + bus_data_i <= x"00000000" & sender_error(channel_address*32+31 downto channel_address*32); + when x"14" => + bus_data_i <= x"00000000" & x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) + & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0); + when x"1F" => + bus_data_i <= x"00000000" & sender_status(channel_address*32+31 downto channel_address*32); + when x"24" => + bus_data_i <= x"00000000" & x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) + & "00000" & fifo_net_to_pci_data_count(channel_address)(10 downto 0); + when x"30" => + bus_data_i <= x"00000000" & api_status(channel_address*32+31 downto channel_address*32); + when others => + bus_data_i <= x"00000000" & x"10000000"; --"1000000000000000000" & CTRL(31 downto 19); + end case; + end process; + + + write_regs : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + sender_control <= (others => '0'); + sender_target <= (others => '0'); + sender_error <= (others => '0'); + else + if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" then + case BUS_ADDR_IN(3 downto 0) is + --middle nibble is dont care + when x"0" => + sender_control(channel_address*32+8 downto channel_address*32) <= BUS_WDAT_IN(8 downto 0); + when x"1" => + sender_target(channel_address*32+15 downto channel_address*32) <= BUS_WDAT_IN(15 downto 0); + when x"2" => + sender_error(channel_address*32+31 downto channel_address*32) <= BUS_WDAT_IN(31 downto 0); + when others => null; + end case; + end if; + end if; + end if; + end process; + + + proc_save_trigger_info : process(CLK) + begin + if rising_edge(CLK) then + if BUS_ADDR_IN = x"00000115" and bus_write_i = '1' then + EXT_TRIGGER_INFO <= BUS_WDAT_IN(15 downto 0); + end if; + end if; + end process; + + +-------------------------------- +-- connection to API +-------------------------------- + + + process(CLK) + begin + if rising_edge(CLK) then + APL_SEND_OUT <= next_APL_SEND_OUT; + end if; + end process; + + gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate + + + api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); + api_status(i*32+31 downto i*32+8) <= (others => '0'); + sender_status(i*32) <= APL_RUN_IN(i); + sender_status(i*32+31 downto i*32+1) <= (others => '0'); + + + --connection to API + next_APL_SEND_OUT(i) <= '1' when BUS_ADDR_IN(11 downto 8) = "0001" + and BUS_ADDR_IN(7 downto 4) = std_logic_vector(to_unsigned(i,4)) + and BUS_ADDR_IN(3 downto 0) = "0000" + and bus_write_last = '1' else '0'; + + APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i); + APL_DATA_OUT((i+1)*16-1 downto i*16) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH-1 downto i*18); + APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*18+c_DATA_WIDTH+1 downto i*18+c_DATA_WIDTH); + APL_PACKET_NUM_OUT(i*3+2) <= '0'; + APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8); + APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32); + APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32); + APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); + fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost, but transfer size is limited anyhow + + + --connection from API + fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= fifo_net_to_pci_data_count(i)(6 downto 0); + fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); + fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); + + fifo_net_to_pci_din(18*i+c_DATA_WIDTH-1 downto 18*i) <= APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + fifo_net_to_pci_din(18*i+c_DATA_WIDTH) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i); + fifo_net_to_pci_din(18*i+c_DATA_WIDTH+1) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2); + fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i) and not fifo_net_to_pci_full(i); + APL_READ_OUT(i) <= not fifo_net_to_pci_full(i); + + end generate; + + + +-------------------------------- +-- fifo as bridge to pci +-------------------------------- + + + gen_incoming_fifos : for i in 0 to 2**(c_MUX_WIDTH)-1 generate + + FIFO_NET_TO_PCI: trb_net16_fifo + generic map( + USE_VENDOR_CORES => c_YES, + USE_DATA_COUNT => c_YES, + DEPTH => 6 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + READ_ENABLE_IN => fifo_net_to_pci_read(i), + WRITE_ENABLE_IN => fifo_net_to_pci_write(i), + DATA_IN => fifo_net_to_pci_din(18*i+15 downto 18*i), + PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16), + DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), + PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), + DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(10 downto 0), + full_out => fifo_net_to_pci_full(i), + empty_out => fifo_net_to_pci_empty(i) + ); + + FIFO_PCI_TO_NET: trb_net16_fifo + generic map( + USE_VENDOR_CORES => c_YES, + USE_DATA_COUNT => c_YES, + DEPTH => 6 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + READ_ENABLE_IN => fifo_pci_to_net_read(i), + WRITE_ENABLE_IN => fifo_pci_to_net_write(i), + DATA_IN => BUS_WDAT_IN(15 downto 0), + PACKET_NUM_IN => BUS_WDAT_IN(17 downto 16), + DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i), + PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16), + DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(10 downto 0), + full_out => fifo_pci_to_net_full(i), + empty_out => fifo_pci_to_net_empty(i) + ); + + end generate; + + proc_valid_read : process(CLK) + begin + if rising_edge(CLK) then + fifo_pci_to_net_valid_read <= fifo_pci_to_net_read and not fifo_pci_to_net_empty; + fifo_net_to_pci_valid_read <= fifo_net_to_pci_read and not fifo_net_to_pci_empty; + end if; + end process; + + proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, bus_write_i, channel_address) + begin + fifo_net_to_pci_read <= (others => '0'); + fifo_pci_to_net_write <= (others => '0'); + if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then + fifo_net_to_pci_read(channel_address) <= bus_read_i; + end if; + if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"13" then + fifo_pci_to_net_write(channel_address) <= bus_write_i; + end if; + end process; + + proc_register_cpu_output : process(CLK) + begin + if rising_edge(CLK) then + BUS_RDAT_OUT <= bus_rdat_i; + BUS_ACK_OUT <= bus_ack_i; + end if; + end process; + + process(BUS_ADDR_IN, bus_data_i, fifo_net_to_pci_dout, bus_read_i, bus_write_i, channel_address) + begin + if BUS_ADDR_IN(11 downto 8) & BUS_ADDR_IN(3 downto 0) = x"23" then + bus_rdat_i <= fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32) & fifo_net_to_pci_dout(channel_address*32+31 downto channel_address*32); + bus_ack_i <= (bus_read_last or bus_write_i); + else + bus_rdat_i <= bus_data_i(31 downto 0) & bus_data_i(31 downto 0); + bus_ack_i <= (bus_read_i or bus_write_i); + end if; + end process; + + +-------------------------------- +-- network reset +-------------------------------- + SEND_RESET_OUT <= not send_reset_counter(10); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + send_reset_counter <= (others => '1'); + elsif BUS_ADDR_IN = x"00000010" and bus_write_i = '1' and BUS_WDAT_IN(15) = '1' then + send_reset_counter <= (others => '0'); + elsif send_reset_counter(10) = '0' then + send_reset_counter <= send_reset_counter + to_unsigned(1,1); + end if; + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/special/trb_net_bridge_pcie_endpoint.vhd b/special/trb_net_bridge_pcie_endpoint.vhd new file mode 100644 index 0000000..e873b49 --- /dev/null +++ b/special/trb_net_bridge_pcie_endpoint.vhd @@ -0,0 +1,541 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net_bridge_pcie_endpoint is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO) + ); + port( + RESET : in std_logic; + CLK: in std_logic; + + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(63 downto 0); + BUS_RDAT_OUT : out std_logic_vector(63 downto 0); + BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; +-- BUS_CTI_IN : in std_logic_vector(2 downto 0); + BUS_ACK_OUT : out std_logic; + + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + SEND_RESET_OUT : out std_logic; + STAT : out std_logic_vector(31 downto 0); + STAT_ENDP : out std_logic_vector(31 downto 0); + STAT_API1 : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture trb_net_bridge_pcie_endpoint_arch of trb_net_bridge_pcie_endpoint is + + + signal APL_STAT : std_logic_vector(31 downto 0); + + signal APL_DATA_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_IN : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_DATAREADY_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SHORT_TRANSFER_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DTYPE_IN : std_logic_vector(2**(c_MUX_WIDTH)*4-1 downto 0); + signal APL_SEND_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_DATA_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal APL_PACKET_NUM_OUT : std_logic_vector(2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal APL_TYP_OUT : std_logic_vector(2**(c_MUX_WIDTH)*3-1 downto 0); + signal APL_DATAREADY_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_READ_IN : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_RUN_OUT : std_logic_vector(2**(c_MUX_WIDTH)-1 downto 0); + signal APL_SEQNR_OUT : std_logic_vector(2**(c_MUX_WIDTH)*8-1 downto 0); + signal APL_TARGET_ADDRESS_OUT : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_ERROR_PATTERN_IN : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal APL_TARGET_ADDRESS_IN : std_logic_vector(2**(c_MUX_WIDTH)*16-1 downto 0); + signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0); + + signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH)*32-1 downto 0); + + signal CLK_EN : std_logic; + + signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0); + signal m_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0); + signal MPLEX_CTRL : std_logic_vector (31 downto 0); + + signal apl_to_buf_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal tmp_apl_to_buf_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_INIT_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_INIT_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_INIT_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal apl_to_buf_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal apl_to_buf_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + signal buf_to_apl_REPLY_DATA : std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + signal buf_to_apl_REPLY_READ : std_logic_vector(2**(c_MUX_WIDTH-1)-1 downto 0); + + + signal STAT_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal STAT_INIT_BUFFER : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_GEN : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal CTRL_LOCKED : std_logic_vector(32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal RESET_i : std_logic; + signal RESET_CNT : std_logic_vector(1 downto 0); + signal counter : std_logic_vector(12 downto 0); + signal buf_MED_DATAREADY_OUT : std_logic; + + signal reg_extended_trigger_information : std_logic_vector(15 downto 0); + +begin + CLK_EN <= '1'; + APL_MY_ADDRESS_IN <= x"F00C"; + RESET_i <= RESET; + + + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + + MPLEX_CTRL <= (others => '0'); + THE_MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT => m_DATA_IN, + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, + INT_READ_IN => m_READ_OUT, + INT_DATAREADY_IN => m_DATAREADY_OUT, + INT_DATA_IN => m_DATA_OUT, + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, + INT_READ_OUT => m_READ_IN, + CTRL => MPLEX_CTRL + ); + + gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + gen_used_channel : if USE_CHANNELS(i) = c_YES generate + IOBUF: trb_net16_iobuf + generic map ( + USE_CHECKSUM => cfg_USE_CHECKSUM(i) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET_i, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(i*c_DATA_WIDTH+15 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH), + MED_READ_OUT => m_READ_OUT(i), + MED_ERROR_IN => MED_ERROR_IN, + -- Internal direction port + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + -- Status and control port + STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32), + STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32) + ); + end generate; + gen_not_used_channel : if USE_CHANNELS(i) = c_NO generate + apl_to_buf_INIT_READ(i) <= '0'; + apl_to_buf_INIT_DATAREADY(i) <= '0'; + apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_DATAREADY(i) <= '0'; + apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_READ(i) <= '0'; + apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_INIT_READ(i) <= '0'; + buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_REPLY_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_READ(i) <= '0'; + buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0'); + STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0'); + STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0'); + + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => m_DATAREADY_IN(i), + MED_DATA_IN => m_DATA_IN(i*16+15 downto i*16), + MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*3+2 downto i*3), + MED_READ_OUT => m_READ_OUT(i), + + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1) + ); + end generate; + end generate; + + CTRL_GEN <= (others => '0'); + + gen_pas_apis : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate + gen_used_api : if USE_CHANNELS(i) = c_YES generate + gen_passive_api : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_NO generate + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i), + APL_READ_OUT => APL_READ_OUT(2*i), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+1)*4-1 downto 2*i*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+1)*32-1 downto 2*i*32), + APL_SEND_IN => APL_SEND_IN(2*i), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+1)*16-1 downto 2*i*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+1)*c_DATA_WIDTH-1 downto 2*i*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+1)*c_NUM_WIDTH-1 downto 2*i*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+1)*3-1 downto 2*i*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i), + APL_READ_IN => APL_READ_IN(2*i), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+1)*8-1 downto 2*i*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + CTRL_SEQNR_RESET => '0', + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32) + ); + + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => tmp_apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + CTRL_SEQNR_RESET => '0', + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + end generate; + gen_auto_answer : if AUTO_ANSWER_INCOMING_REQUESTS(i) = c_YES generate + DAT_ACTIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => c_FIFO_BRAM, + FIFO_TO_APL_DEPTH => c_FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS => c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_DATAREADY_IN => APL_DATAREADY_IN(2*i+1), + APL_READ_OUT => APL_READ_OUT(2*i+1), + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(2*i+1), + APL_DTYPE_IN => APL_DTYPE_IN((2*i+2)*4-1 downto (2*i+1)*4), + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((2*i+2)*32-1 downto (2*i+1)*32), + APL_SEND_IN => APL_SEND_IN(2*i+1), + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((2*i+2)*16-1 downto (2*i+1)*16), + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH), + APL_TYP_OUT => APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3), + APL_DATAREADY_OUT => APL_DATAREADY_OUT(2*i+1), + APL_READ_IN => APL_READ_IN(2*i+1), + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT(2*i+1), + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_LENGTH_IN => x"FFFF", + APL_SEQNR_OUT => APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + CTRL_SEQNR_RESET => '0', + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) + ); + + + + + + + end generate; + end generate; + gen_no_api : if USE_CHANNELS(i) = c_NO generate + APL_READ_OUT(2*i+1) <= '1'; + APL_DATA_OUT((2*i+2)*c_DATA_WIDTH-1 downto (2*i+1)*c_DATA_WIDTH) <= (others => '0'); + APL_PACKET_NUM_OUT((2*i+2)*c_NUM_WIDTH-1 downto (2*i+1)*c_NUM_WIDTH) <= (others => '0'); + APL_TYP_OUT((2*i+2)*3-1 downto (2*i+1)*3) <= (others => '0'); + APL_DATAREADY_OUT(2*i+1) <= '0'; + APL_RUN_OUT(2*i+1) <= '0'; + APL_SEQNR_OUT((2*i+2)*8-1 downto (2*i+1)*8) <= (others => '0'); + buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); + buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) <= (others => '0'); + end generate; + end generate; + +--Add additional word for trigger information + apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16) <= tmp_apl_to_buf_INIT_DATA(apl_to_buf_INIT_DATA'left downto 16); + + proc_add_trigger_info : process(tmp_apl_to_buf_INIT_DATA, apl_to_buf_INIT_PACKET_NUM,reg_extended_trigger_information) + begin + if apl_to_buf_INIT_PACKET_NUM(2 downto 0) = c_F0 then + apl_to_buf_INIT_DATA(15 downto 0) <= reg_extended_trigger_information; + else + apl_to_buf_INIT_DATA(15 downto 0) <= tmp_apl_to_buf_INIT_DATA(15 downto 0); + end if; + end process; + + + + + APL : trb_net_bridge_pcie_apl + port map( + CLK => CLK, + RESET => RESET_i, + CLK_EN => CLK_EN, + APL_DATA_OUT => APL_DATA_IN, + APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN, + APL_DATAREADY_OUT => APL_DATAREADY_IN, + APL_READ_IN => APL_READ_OUT, + APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN, + APL_DTYPE_OUT => APL_DTYPE_IN, + APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN, + APL_SEND_OUT => APL_SEND_IN, + APL_DATA_IN => APL_DATA_OUT, + APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT, + APL_TYP_IN => APL_TYP_OUT, + APL_DATAREADY_IN => APL_DATAREADY_OUT, + APL_READ_OUT => APL_READ_IN, + APL_RUN_IN => APL_RUN_OUT, + APL_SEQNR_IN => APL_SEQNR_OUT, + APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN, + EXT_TRIGGER_INFO => reg_extended_trigger_information, + BUS_ADDR_IN => BUS_ADDR_IN, + BUS_WDAT_IN => BUS_WDAT_IN, + BUS_RDAT_OUT => BUS_RDAT_OUT, + BUS_SEL_IN => BUS_SEL_IN, + BUS_WE_IN => BUS_WE_IN, + BUS_CYC_IN => BUS_CYC_IN, + BUS_STB_IN => BUS_STB_IN, + BUS_LOCK_IN => BUS_LOCK_IN, +-- BUS_CTI_IN => BUS_CTI_IN, + BUS_ACK_OUT => BUS_ACK_OUT, + SEND_RESET_OUT => SEND_RESET_OUT, + STAT => STAT, + CTRL => (others => '0') + ); + +STAT_ENDP(0) <= APL_SEND_IN(1); +STAT_ENDP(4 downto 1) <= BUS_ADDR_IN(3 downto 0); +STAT_ENDP(5) <= BUS_WE_IN; +STAT_ENDP(6) <= APL_READ_OUT(1); +STAT_ENDP(7) <= buf_MED_DATAREADY_OUT; +STAT_ENDP(11 downto 8) <= APL_DATA_OUT(51 downto 48); +STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_OUT(4 downto 3); +STAT_ENDP(14) <= APL_DATAREADY_OUT(3); +STAT_ENDP(15) <= buf_to_apl_REPLY_DATAREADY(0); +STAT_ENDP(16) <= APL_READ_IN(3); + +STAT_ENDP(17) <= '0'; +STAT_ENDP(18) <= '0'; + +STAT_ENDP(21 downto 19) <= APL_PACKET_NUM_OUT(11 downto 9); +STAT_ENDP(22) <= APL_DATAREADY_OUT(3); +STAT_ENDP(23) <= APL_READ_IN(3); +STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48); + + +STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(19 downto 16); +STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(19 downto 16); + +STAT_API1(11) <= apl_to_buf_REPLY_READ(3); +STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3); +STAT_API1(13) <= apl_to_buf_INIT_DATAREADY(3); +STAT_API1(14) <= buf_to_apl_INIT_READ(3); +STAT_API1(31 downto 15) <= (others => '0'); + + +--STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32); + +end architecture; \ No newline at end of file diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 359fdd2..cacd049 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -883,8 +883,6 @@ begin proc_global_time : process(CLK) begin if rising_edge(CLK) then --- global_time(15 downto 0) <= next_global_time(15 downto 0); --- global_time_overflow <= '0'; TIMER_MS_TICK <= '0'; if global_time_write = '1' then global_time_i <= saved_Reg_high & saved_Reg_low; @@ -893,13 +891,6 @@ begin if global_time_i(9 downto 0) = "0000000000" then TIMER_MS_TICK <= '1'; end if; --- next_global_time(15 downto 0) <= global_time(15 downto 0) + 1; --- if or_all(global_time(15 downto 0)) = '1' then --- global_time_overflow <= '1'; --- end if; --- elsif global_time_overflow = '1' then --- global_time_buf <= '0'; --- global_time(31 downto 16) <= global_time(31 downto 16) + 1; end if; end if; end process; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index be4886a..833156f 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1,2964 +1,3047 @@ -library ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -library work; -use work.trb_net_std.all; - -package trb_net_components is - - - ---This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names - - - -component trb_net16_med_scm_sfp_gbe is -generic( - SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE - EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE - USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE -); -port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); -end component trb_net16_med_scm_sfp_gbe; - - - - - - component adc_ltc2308_readout is - generic( - CLOCK_FREQUENCY : integer := 100 --MHz - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - ADC_SCK : out std_logic; - ADC_SDI : out std_logic; - ADC_SDO : in std_logic; - ADC_CONVST : out std_logic; - - DAT_ADDR_IN : in std_logic_vector(5 downto 0); - DAT_READ_EN_IN : in std_logic; - DAT_WRITE_EN_IN : in std_logic; - DAT_DATA_OUT : out std_logic_vector(31 downto 0); - DAT_DATA_IN : in std_logic_vector(31 downto 0); - DAT_DATAREADY_OUT : out std_logic; - DAT_NO_MORE_DATA_OUT : out std_logic; - DAT_WRITE_ACK_OUT : out std_logic; - DAT_UNKNOWN_ADDR_OUT : out std_logic; - DAT_TIMEOUT_IN : in std_logic; - - STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - - component trb_net16_addresses is - generic( - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - RAM_DATA_IN : in std_logic_vector(15 downto 0); - RAM_DATA_OUT : out std_logic_vector(15 downto 0); - RAM_ADDR_IN : in std_logic_vector(2 downto 0); - RAM_WR_IN : in std_logic; - API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - ADDRESS_REJECTED : out std_logic; - DONT_UNDERSTAND_OUT : out std_logic; - API_SEND_OUT : out std_logic; - ADDRESS_OUT : out std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(15 downto 0) - ); - end component; - - - - - - - component trb_net16_api_base is - generic ( - API_TYPE : integer range 0 to 1 := c_API_PASSIVE; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; - ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF" - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN : in std_logic; - APL_READ_OUT : out std_logic; - APL_SHORT_TRANSFER_IN : in std_logic; - APL_DTYPE_IN : in std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - APL_SEND_IN : in std_logic; - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); - APL_DATAREADY_OUT : out std_logic; - APL_READ_IN : in std_logic; - -- APL Control port - APL_RUN_OUT : out std_logic; - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_LENGTH_IN : in std_logic_vector (15 downto 0); - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - -- master_data_out and slave_data_in are only used in active API for termination - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - CTRL_SEQNR_RESET : in std_logic; - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - - - - component trb_net16_api_ipu_streaming is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Internal direction port - - FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - FEE_INIT_DATAREADY_OUT : out std_logic; - FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - FEE_INIT_READ_IN : in std_logic; - - FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - FEE_REPLY_DATAREADY_IN : in std_logic; - FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - FEE_REPLY_READ_OUT : out std_logic; - - CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - CTS_INIT_DATAREADY_IN : in std_logic; - CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - CTS_INIT_READ_OUT : out std_logic; - - CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - CTS_REPLY_DATAREADY_OUT : out std_logic; - CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - CTS_REPLY_READ_IN : in std_logic; - - --Event information coming from CTS - CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - CTS_CODE_OUT : out std_logic_vector (7 downto 0); - CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - CTS_START_READOUT_OUT : out std_logic; - - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_IN : in std_logic_vector (31 downto 0); - CTS_DATAREADY_IN : in std_logic; - CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM - CTS_READ_OUT : out std_logic; - CTS_LENGTH_IN : in std_logic_vector (15 downto 0); - CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - - -- Data from Frontends - FEE_DATA_OUT : out std_logic_vector (15 downto 0); - FEE_DATAREADY_OUT : out std_logic; - FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready - FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - FEE_BUSY_OUT : out std_logic; - - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - CTRL_SEQNR_RESET : in std_logic - - ); - end component; - - - - - - component trb_net_CRC is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - CRC_OUT : out std_logic_vector(15 downto 0); - CRC_match : out std_logic - ); - end component; - - - component trb_net_CRC8 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - CRC_OUT : out std_logic_vector(7 downto 0); - CRC_match : out std_logic - ); - end component; - - component ddr_off is - port ( - Clk: in std_logic; - Data: in std_logic_vector(1 downto 0); - Q: out std_logic_vector(0 downto 0) - ); - end component; - - - - component dll_in100_out100 is - port ( - clk: in std_logic; - aluhold: in std_logic; - clkop: out std_logic; - clkos: out std_logic; - lock: out std_logic - ); - end component; - - - component dll_in200_out100 is - port ( - clk: in std_logic; - aluhold: in std_logic; - clkop: out std_logic; - clkos: out std_logic; - lock: out std_logic - ); - end component; - - - component trb_net16_dummy_fifo is - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(1 downto 0); - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic - ); - end component; - - - - - - component trb_net16_endpoint_hades_full is - generic ( - USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - IBUF_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); - IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; - INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); - APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; - TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; - REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers - REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - --standard values for output registers - REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); - --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR - REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; - CLOCK_FREQUENCY : integer range 1 to 200 := 100 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic := '1'; - - -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_STAT_OP_IN : in std_logic_vector(15 downto 0); - MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); - - -- LVL1 trigger APL - TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received - - LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid - LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received - LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received - LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) - - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; - LVL1_TRG_RELEASE_IN : in std_logic := '0'; - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT : out std_logic; - TRG_TIMEOUT_DETECTED_OUT : out std_logic; - TRG_SPURIOUS_TRG_OUT : out std_logic; - TRG_MISSING_TMG_TRG_OUT : out std_logic; - TRG_SPIKE_DETECTED_OUT : out std_logic; - --Data Port - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); - --start strobe - IPU_START_READOUT_OUT : out std_logic; - --detector data, equipped with DHDR - IPU_DATA_IN : in std_logic_vector (31 downto 0); - IPU_DATAREADY_IN : in std_logic; - --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_IN : in std_logic; - --will be low every second cycle due to 32bit -> 16bit conversion - IPU_READ_OUT : out std_logic; - IPU_LENGTH_IN : in std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); - REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); - COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); - STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); - CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - --following ports only used when using internal data port - REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - REGIO_DATAREADY_IN : in std_logic := '0'; - REGIO_NO_MORE_DATA_IN : in std_logic := '0'; - REGIO_WRITE_ACK_IN : in std_logic := '0'; - REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; - REGIO_TIMEOUT_OUT : out std_logic; - --IDRAM is used if no 1-wire interface, onewire used otherwise - REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); - REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; - REGIO_IDRAM_WR_IN : in std_logic := '0'; - REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor - REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; - REGIO_ONEWIRE_MONITOR_OUT : out std_logic; - REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); - - GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds - LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick - --Debugging & Status information - STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); - STAT_DEBUG_1 : out std_logic_vector (31 downto 0); - STAT_DEBUG_2 : out std_logic_vector (31 downto 0); - MED_STAT_OP : out std_logic_vector (15 downto 0); - CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); - IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); - STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); - DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) - ); - end component; - - - component trb_net16_endpoint_hades_full_handler is - generic ( - IBUF_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); - APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; - REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers - REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR - REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; - TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; - CLOCK_FREQUENCY : integer range 1 to 200 := 100; - --Configure data handler - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; - TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic := '1'; - - -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_STAT_OP_IN : in std_logic_vector(15 downto 0); - MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN : in std_logic; - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid - LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received - LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received - LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) - - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only - - --Response from FEE - FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT : out std_logic; - TRG_TIMEOUT_DETECTED_OUT : out std_logic; - TRG_SPURIOUS_TRG_OUT : out std_logic; - TRG_MISSING_TMG_TRG_OUT : out std_logic; - TRG_SPIKE_DETECTED_OUT : out std_logic; - - --Slow Control Port - --common registers - REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0); - REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0); - --user defined registers - REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0'); - REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0); - REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); - REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - --internal data port - BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0); - BUS_DATA_OUT : out std_logic_vector(32-1 downto 0); - BUS_READ_ENABLE_OUT : out std_logic; - BUS_WRITE_ENABLE_OUT : out std_logic; - BUS_TIMEOUT_OUT : out std_logic; - BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - BUS_DATAREADY_IN : in std_logic := '0'; - BUS_WRITE_ACK_IN : in std_logic := '0'; - BUS_NO_MORE_DATA_IN : in std_logic := '0'; - BUS_UNKNOWN_ADDR_IN : in std_logic := '0'; - --Onewire - ONEWIRE_INOUT : inout std_logic; --temperature sensor - ONEWIRE_MONITOR_IN : in std_logic := '0'; - ONEWIRE_MONITOR_OUT : out std_logic; - --Config endpoint id, if not statically assigned - REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0'); - - --Timing registers - TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds - TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger - TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick - - --Debugging & Status information - STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); - STAT_DEBUG_1 : out std_logic_vector (31 downto 0); - STAT_DEBUG_2 : out std_logic_vector (31 downto 0); - STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0); - STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0); - CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); - IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); - STAT_ONEWIRE : out std_logic_vector (31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); - DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) - ); - end component; - - component trb_net16_endpoint_hades_cts is - generic( - USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); - IBUF_DEPTH : channel_config_t := (1,6,6,6); - FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6); - INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); - REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES); - REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); - USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); - APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers - REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - --standard values for output registers - REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001"; - --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000"; - REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; - REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; - REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR - REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; - CLOCK_FREQUENCY : integer range 1 to 200 := 100 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; - - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - - MED_STAT_OP_IN : in std_logic_vector(15 downto 0); - MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); - - --LVL1 trigger - TRG_SEND_IN : in std_logic; - TRG_TYPE_IN : in std_logic_vector (3 downto 0); - TRG_NUMBER_IN : in std_logic_vector (15 downto 0); - TRG_INFORMATION_IN : in std_logic_vector (23 downto 0); - TRG_RND_CODE_IN : in std_logic_vector (7 downto 0); - TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - TRG_BUSY_OUT : out std_logic; - - --IPU Channel - IPU_SEND_IN : in std_logic; - IPU_TYPE_IN : in std_logic_vector (3 downto 0); - IPU_NUMBER_IN : in std_logic_vector (15 downto 0); - IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); - IPU_RND_CODE_IN : in std_logic_vector (7 downto 0); - -- Receiver port - IPU_DATA_OUT : out std_logic_vector (31 downto 0); - IPU_DATAREADY_OUT : out std_logic; - IPU_READ_IN : in std_logic; - IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - IPU_BUSY_OUT : out std_logic; - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); - REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); - COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); - STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); - CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - --following ports only used when using internal data port - REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - REGIO_DATAREADY_IN : in std_logic := '0'; - REGIO_NO_MORE_DATA_IN : in std_logic := '0'; - REGIO_WRITE_ACK_IN : in std_logic := '0'; - REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; - REGIO_TIMEOUT_OUT : out std_logic; - REGIO_ONEWIRE_INOUT : inout std_logic; - REGIO_ONEWIRE_MONITOR_OUT : out std_logic; - REGIO_ONEWIRE_MONITOR_IN : in std_logic; - REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); - TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received - GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds - LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick - STAT_DEBUG_1 : out std_logic_vector(31 downto 0); - STAT_DEBUG_2 : out std_logic_vector(31 downto 0) - ); - - end component; - - - - - component etrax_interface is - generic( - STATUS_REGISTERS : integer := 4; - CONTROL_REGISTERS : integer := 4 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - --Connection to Etrax - ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); - ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0); - ETRAX_BUS_BUSY : out std_logic; - --Connection to internal FPGA logic (all addresses above 0x100) - INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - INTERNAL_READ_OUT : out std_logic; - INTERNAL_WRITE_OUT : out std_logic; - INTERNAL_DATAREADY_IN : in std_logic; - INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0); - --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl) - FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0); - FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); - --Reset FPGA via Etrax - EXTERNAL_RESET : out std_logic; - STAT : out std_logic_vector(15 downto 0) - ); - end component; - - - - - - - - - component trb_net16_fifo is - generic ( +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; + +package trb_net_components is + + + +--This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names + + + +component trb_net16_med_scm_sfp_gbe is +generic( + SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE + EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE + USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE +); +port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end component trb_net16_med_scm_sfp_gbe; + + + + + + component adc_ltc2308_readout is + generic( + CLOCK_FREQUENCY : integer := 100 --MHz + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + ADC_SCK : out std_logic; + ADC_SDI : out std_logic; + ADC_SDO : in std_logic; + ADC_CONVST : out std_logic; + + DAT_ADDR_IN : in std_logic_vector(5 downto 0); + DAT_READ_EN_IN : in std_logic; + DAT_WRITE_EN_IN : in std_logic; + DAT_DATA_OUT : out std_logic_vector(31 downto 0); + DAT_DATA_IN : in std_logic_vector(31 downto 0); + DAT_DATAREADY_OUT : out std_logic; + DAT_NO_MORE_DATA_OUT : out std_logic; + DAT_WRITE_ACK_OUT : out std_logic; + DAT_UNKNOWN_ADDR_OUT : out std_logic; + DAT_TIMEOUT_IN : in std_logic; + + STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component trb_net16_addresses is + generic( + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_ADDR_IN : in std_logic_vector(2 downto 0); + RAM_WR_IN : in std_logic; + API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + ADDRESS_REJECTED : out std_logic; + DONT_UNDERSTAND_OUT : out std_logic; + API_SEND_OUT : out std_logic; + ADDRESS_OUT : out std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_LENGTH_IN : in std_logic_vector (15 downto 0); + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + CTRL_SEQNR_RESET : in std_logic; + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component trb_net16_api_ipu_streaming is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Internal direction port + + FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_INIT_DATAREADY_OUT : out std_logic; + FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_INIT_READ_IN : in std_logic; + + FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_REPLY_DATAREADY_IN : in std_logic; + FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_REPLY_READ_OUT : out std_logic; + + CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_INIT_DATAREADY_IN : in std_logic; + CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + CTS_INIT_READ_OUT : out std_logic; + + CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_REPLY_DATAREADY_OUT : out std_logic; + CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + CTS_REPLY_READ_IN : in std_logic; + + --Event information coming from CTS + CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + CTS_CODE_OUT : out std_logic_vector (7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN : in std_logic_vector (31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector (15 downto 0); + CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + + -- Data from Frontends + FEE_DATA_OUT : out std_logic_vector (15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready + FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + FEE_BUSY_OUT : out std_logic; + + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + CTRL_SEQNR_RESET : in std_logic + + ); + end component; + + + component trb_net_bridge_pcie_apl is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --TrbNet connect + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + + --Internal Data Bus + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(63 downto 0); + BUS_RDAT_OUT : out std_logic_vector(63 downto 0); + BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; + BUS_CTI_IN : in std_logic_vector(2 downto 0); + BUS_ACK_OUT : out std_logic; + + EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0); + SEND_RESET_OUT : out std_logic; + --DMA interface + + --Debug + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); + end component; + + + component trb_net_bridge_pcie_endpoint is + generic( + USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO) + ); + port( + RESET : in std_logic; + CLK: in std_logic; + + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(63 downto 0); + BUS_RDAT_OUT : out std_logic_vector(63 downto 0); + BUS_SEL_IN : in std_logic_vector(7 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; + BUS_CTI_IN : in std_logic_vector(2 downto 0); + BUS_ACK_OUT : out std_logic; + + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + SEND_RESET_OUT : out std_logic; + STAT : out std_logic_vector(31 downto 0); + STAT_ENDP : out std_logic_vector(31 downto 0); + STAT_API1 : out std_logic_vector(31 downto 0) + ); + end component; + + + component trb_net_CRC is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + CRC_OUT : out std_logic_vector(15 downto 0); + CRC_match : out std_logic + ); + end component; + + + component trb_net_CRC8 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_match : out std_logic + ); + end component; + + component ddr_off is + port ( + Clk: in std_logic; + Data: in std_logic_vector(1 downto 0); + Q: out std_logic_vector(0 downto 0) + ); + end component; + + + + component dll_in100_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); + end component; + + + component dll_in200_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); + end component; + + + component trb_net16_dummy_fifo is + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + + + + + component trb_net16_endpoint_hades_full is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received + + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received + LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT : out std_logic; + TRG_TIMEOUT_DETECTED_OUT : out std_logic; + TRG_SPURIOUS_TRG_OUT : out std_logic; + TRG_MISSING_TMG_TRG_OUT : out std_logic; + TRG_SPIKE_DETECTED_OUT : out std_logic; + --Data Port + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT : out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + REGIO_IDRAM_WR_IN : in std_logic := '0'; + REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor + REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + MED_STAT_OP : out std_logic_vector (15 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + + component trb_net16_endpoint_hades_full_handler is + generic ( + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; + CLOCK_FREQUENCY : integer range 1 to 200 := 100; + --Configure data handler + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only + + --Response from FEE + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT : out std_logic; + TRG_TIMEOUT_DETECTED_OUT : out std_logic; + TRG_SPURIOUS_TRG_OUT : out std_logic; + TRG_MISSING_TMG_TRG_OUT : out std_logic; + TRG_SPIKE_DETECTED_OUT : out std_logic; + + --Slow Control Port + --common registers + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0); + REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0); + --user defined registers + REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0'); + REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0); + REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --internal data port + BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic; + BUS_WRITE_ENABLE_OUT : out std_logic; + BUS_TIMEOUT_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + BUS_DATAREADY_IN : in std_logic := '0'; + BUS_WRITE_ACK_IN : in std_logic := '0'; + BUS_NO_MORE_DATA_IN : in std_logic := '0'; + BUS_UNKNOWN_ADDR_IN : in std_logic := '0'; + --Onewire + ONEWIRE_INOUT : inout std_logic; --temperature sensor + ONEWIRE_MONITOR_IN : in std_logic := '0'; + ONEWIRE_MONITOR_OUT : out std_logic; + --Config endpoint id, if not statically assigned + REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0'); + + --Timing registers + TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds + TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger + TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick + + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0); + STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + component trb_net16_endpoint_hades_cts is + generic( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (1,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6); + INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; + REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + --LVL1 trigger + TRG_SEND_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector (3 downto 0); + TRG_NUMBER_IN : in std_logic_vector (15 downto 0); + TRG_INFORMATION_IN : in std_logic_vector (23 downto 0); + TRG_RND_CODE_IN : in std_logic_vector (7 downto 0); + TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + TRG_BUSY_OUT : out std_logic; + + --IPU Channel + IPU_SEND_IN : in std_logic; + IPU_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_RND_CODE_IN : in std_logic_vector (7 downto 0); + -- Receiver port + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + IPU_BUSY_OUT : out std_logic; + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + REGIO_ONEWIRE_MONITOR_IN : in std_logic; + REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick + STAT_DEBUG_1 : out std_logic_vector(31 downto 0); + STAT_DEBUG_2 : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + component etrax_interface is + generic( + STATUS_REGISTERS : integer := 4; + CONTROL_REGISTERS : integer := 4 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + --Connection to Etrax + ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0); + ETRAX_BUS_BUSY : out std_logic; + --Connection to internal FPGA logic (all addresses above 0x100) + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + INTERNAL_READ_OUT : out std_logic; + INTERNAL_WRITE_OUT : out std_logic; + INTERNAL_DATAREADY_IN : in std_logic; + INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0); + --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl) + FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0); + FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); + --Reset FPGA via Etrax + EXTERNAL_RESET : out std_logic; + STAT : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + + + + component trb_net16_fifo is + generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; - USE_DATA_COUNT : integer range 0 to 1 := c_NO; - DEPTH : integer := 6 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(1 downto 0); - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + USE_DATA_COUNT : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); READ_ENABLE_IN : in std_logic; - DATA_COUNT_OUT : out std_logic_vector(10 downto 0); - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic - ); - end component; - - - - - - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port( read_clock_in : in std_logic; - write_clock_in : in std_logic; - read_enable_in : in std_logic; - write_enable_in : in std_logic; - fifo_gsr_in : in std_logic; - write_data_in : in std_logic_vector(17 downto 0); - read_data_out : out std_logic_vector(17 downto 0); - full_out : out std_logic; - empty_out : out std_logic; - fifostatus_out : out std_logic_vector(3 downto 0); - valid_read_out : out std_logic; - almost_empty_out : out std_logic; - almost_full_out : out std_logic - ); - end component; - - - - - - - component fifo_dualclock_width_16_reg is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic); - end component; - - - - --- component trb_net16_gbe_buf is --- generic( --- DO_SIMULATION : integer range 0 to 1 := 1; --- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 --- ); --- port( --- CLK : in std_logic; --- TEST_CLK : in std_logic; -- only for simulation! --- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode --- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode --- RESET : in std_logic; --- GSR_N : in std_logic; --- -- Debug --- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); --- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); --- -- configuration interface --- IP_CFG_START_IN : in std_logic; --- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); --- IP_CFG_DONE_OUT : out std_logic; --- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); --- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); --- IP_CFG_MEM_CLK_OUT : out std_logic; --- MR_RESET_IN : in std_logic; --- MR_MODE_IN : in std_logic; --- MR_RESTART_IN : in std_logic; --- -- gk 29.03.10 --- SLV_ADDR_IN : in std_logic_vector(7 downto 0); --- SLV_READ_IN : in std_logic; --- SLV_WRITE_IN : in std_logic; --- SLV_BUSY_OUT : out std_logic; --- SLV_ACK_OUT : out std_logic; --- SLV_DATA_IN : in std_logic_vector(31 downto 0); --- SLV_DATA_OUT : out std_logic_vector(31 downto 0); --- -- gk 22.04.10 --- -- registers setup interface --- BUS_ADDR_IN : in std_logic_vector(7 downto 0); --- BUS_DATA_IN : in std_logic_vector(31 downto 0); --- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 --- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_ACK_OUT : out std_logic; -- gk 26.04.10 --- -- gk 23.04.10 --- LED_PACKET_SENT_OUT : out std_logic; --- LED_AN_DONE_N_OUT : out std_logic; --- -- CTS interface --- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --- CTS_CODE_IN : in std_logic_vector (7 downto 0); --- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --- CTS_START_READOUT_IN : in std_logic; --- CTS_DATA_OUT : out std_logic_vector (31 downto 0); --- CTS_DATAREADY_OUT : out std_logic; --- CTS_READOUT_FINISHED_OUT : out std_logic; --- CTS_READ_IN : in std_logic; --- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); --- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); --- -- Data payload interface --- FEE_DATA_IN : in std_logic_vector (15 downto 0); --- FEE_DATAREADY_IN : in std_logic; --- FEE_READ_OUT : out std_logic; --- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --- FEE_BUSY_IN : in std_logic; --- --SFP Connection --- SFP_RXD_P_IN : in std_logic; --- SFP_RXD_N_IN : in std_logic; --- SFP_TXD_P_OUT : out std_logic; --- SFP_TXD_N_OUT : out std_logic; --- SFP_REFCLK_P_IN : in std_logic; --- SFP_REFCLK_N_IN : in std_logic; --- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) --- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) --- SFP_TXDIS_OUT : out std_logic; -- SFP disable --- -- debug ports --- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) --- ); --- end component; - - - - component handler_data is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; - TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - - --LVL1 Handler - LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts - LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type - LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number - LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_OUT : out std_logic; - - --FEE - FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - - --IPU Handler - IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); - IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); - - IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0); - IPU_HDR_DATA_READ_IN : in std_logic; - IPU_HDR_DATA_EMPTY_OUT : out std_logic; - - TMG_TRG_ERROR_IN : in std_logic; - --Status - STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); - - --Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - - end component; - - - - - - component handler_ipu is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - - --From Data Handler - DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); - DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); - DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); - DAT_HDR_DATA_READ_OUT : out std_logic; - DAT_HDR_DATA_EMPTY_IN : in std_logic; - - --To IPU Channel - IPU_NUMBER_IN : in std_logic_vector (15 downto 0); - IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); - IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - IPU_START_READOUT_IN : in std_logic; - IPU_DATA_OUT : out std_logic_vector (31 downto 0); - IPU_DATAREADY_OUT : out std_logic; - IPU_READOUT_FINISHED_OUT : out std_logic; - IPU_READ_IN : in std_logic; - IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - - --Debug - STATUS_OUT : out std_logic_vector(31 downto 0) - ); - - end component; - - - - component handler_lvl1 is - generic( - TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES - ); - port( - RESET : in std_logic; - RESET_STATS_IN : in std_logic; - CLOCK : in std_logic; - --Timing Trigger - LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics - LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger - --LVL1_handler connection - LVL1_TRG_RECEIVED_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS - LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS - - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release - LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter - LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter - - --FEE logic / Data Handler - LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid - LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received - LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received - LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) - LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected - LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); - LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10 - LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10 - LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10 - SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10 - - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE - LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE - - --Stat/Control - STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers - TRG_ENABLE_IN : in std_logic; -- trigger enable flag - TRG_INVERT_IN : in std_logic; -- trigger invert flag - COUNTERS_STATUS_OUT : out std_logic_vector (63 downto 0); - --Debug - DEBUG_OUT : out std_logic_vector (15 downto 0) - ); - end component; - - - - - - component handler_trigger_and_data is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; - TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - RESET_IPU : in std_logic; - - --To Endpoint - --Timing Trigger (registered) - LVL1_VALID_TRIGGER_IN : in std_logic; - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - --LVL1_handler connection - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_OUT : out std_logic; - - --IPU channel - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); - IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); - IPU_START_READOUT_IN : in std_logic; - IPU_DATA_OUT : out std_logic_vector(31 downto 0); - IPU_DATAREADY_OUT : out std_logic; - IPU_READOUT_FINISHED_OUT : out std_logic; - IPU_READ_IN : in std_logic; - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - - --To FEE - --FEE to Trigger - FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - - --Data Input from FEE - FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - - TMG_TRG_ERROR_IN : in std_logic; - --Status Registers - STATUS_OUT : out std_logic_vector(127 downto 0); - STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); - TIMER_TICKS_IN : in std_logic_vector(1 downto 0); - STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0); - STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); - STATISTICS_READY_OUT : out std_logic; - STATISTICS_READ_IN : in std_logic; - STATISTICS_UNKNOWN_OUT : out std_logic; - - --Debug - DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); - DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0) - - ); - end component; - - - - - - - - component trb_net16_ibuf is - generic ( - DEPTH : integer range 0 to 7 := c_FIFO_BRAM; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_READ_IN : in std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_READ_IN : in std_logic; - INT_ERROR_OUT : out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); - STAT_BUFFER : out std_logic_vector (31 downto 0); - CTRL_STAT : in std_logic_vector (15 downto 0) - ); - end component; - - - - - - - component fifo_36x512 is - port ( - Data: in std_logic_vector(35 downto 0); - Clock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(35 downto 0); - Empty: out std_logic; - Full: out std_logic - ); - end component; - - ---component fifo_var_oreg is - --generic( - --FIFO_WIDTH : integer range 1 to 64 := 36; - --FIFO_DEPTH : integer range 1 to 16 := 8 - --); - --port( - --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); - --Clock : in std_logic; - --WrEn : in std_logic; - --RdEn : in std_logic; - --Reset : in std_logic; - --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); - --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); - --WCNT : out std_logic_vector(FIFO_DEPTH downto 0); - --Empty : out std_logic; - --Full : out std_logic; - --AlmostFull : out std_logic - --); ---end component; - - - - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - -- Status and control port - STAT_GEN : out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0); - CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0'); - STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); - TIMER_TICKS_IN : in std_logic_vector (1 downto 0); - CTRL_STAT : in std_logic_vector (15 downto 0) - ); - end component; - - - - - - - component trb_net16_io_multiplexer is - generic( - USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO) - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in STD_LOGIC; - MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out STD_LOGIC; - MED_DATAREADY_OUT : out STD_LOGIC; - MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in STD_LOGIC; - -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL : in STD_LOGIC_VECTOR (31 downto 0); - STAT : out STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - - - - - component trb_net16_ipudata is - generic( - DO_CHECKS : integer range c_NO to c_YES := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - API_LENGTH_OUT : out std_logic_vector (15 downto 0); - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - - --Information received with request - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); - IPU_CODE_OUT : out std_logic_vector (7 downto 0); - --start strobe - IPU_START_READOUT_OUT: out std_logic; - --detector data, equipped with DHDR - IPU_DATA_IN : in std_logic_vector (31 downto 0); - IPU_DATAREADY_IN : in std_logic; - --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_IN : in std_logic; - --will be low every second cycle due to 32bit -> 16bit conversion - IPU_READ_OUT : out std_logic; - IPU_LENGTH_IN : in std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - - STAT_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; - -component trb_net16_gbe_buf is -generic( - DO_SIMULATION : integer range 0 to 1 := 1; - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - RESET : in std_logic; - GSR_N : in std_logic; - -- Debug - STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); - STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); - -- configuration interface - IP_CFG_START_IN : in std_logic; - IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); - IP_CFG_DONE_OUT : out std_logic; - IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); - IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); - IP_CFG_MEM_CLK_OUT : out std_logic; - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_RESTART_IN : in std_logic; - -- gk 29.03.10 - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- gk 23.04.10 - LED_PACKET_SENT_OUT : out std_logic; - LED_AN_DONE_N_OUT : out std_logic; - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - --SFP Connection - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_REFCLK_P_IN : in std_logic; - SFP_REFCLK_N_IN : in std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable - -- debug ports - ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - - - - - component ipu_dummy is - port( CLK_IN : in std_logic; -- 100MHz local clock - CLEAR_IN : in std_logic; - RESET_IN : in std_logic; -- synchronous reset - -- Slow control signals - MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value - MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value - CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control - -- IPU channel connections - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_IN : in std_logic; -- gimme data! - IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_OUT : out std_logic; -- data is valid - IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM - IPU_READ_IN : in std_logic; -- read strobe, low every second cycle - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern - -- DHDR buffer - LVL1_FIFO_RD_OUT : out std_logic; - LVL1_FIFO_EMPTY_IN : in std_logic; - LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); - LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - component trb_net16_lsm_sfp is - generic( - CHECK_FOR_CV : integer := c_YES - ); - port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available - -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct) - SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation - RX_ALLOW_OUT : out std_logic; -- allow normal receive operation - SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order) - -- debug signals - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - - - - component trb_net16_med_8_SDR_OS is - generic( - TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - -- Media direction port - TX_DATA_OUT : out std_logic_vector (7 downto 0); - TX_CLK_OUT : out std_logic; - TX_CTRL_OUT : out std_logic_vector (1 downto 0); - RX_DATA_IN : in std_logic_vector (7 downto 0); - RX_CLK_IN : in std_logic; - RX_CTRL_IN : in std_logic_vector (1 downto 0); - - -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT: out std_logic_vector (31 downto 0); - CTRL: in std_logic_vector (31 downto 0) - ); - end component; - - - - - - - - component trb_net16_med_ecp_fot is - port( - CLK : in std_logic; - CLK_25 : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - CLEAR : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - --SFP Connection - TXP : out std_logic; - TXN : out std_logic; - RXP : in std_logic; - RXN : in std_logic; - SD : in std_logic; - - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_REG_OUT : out std_logic_vector(127 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (15 downto 0) - ); - end component; - - - - - - - - - component trb_net16_med_ecp_fot_4 is - generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO - -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" - ); - port( - CLK : in std_logic; - CLK_25 : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(3 downto 0); - MED_READ_OUT : out std_logic_vector(3 downto 0); - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); - MED_READ_IN : in std_logic_vector(3 downto 0); - --SFP Connection - TXP : out std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - RXN : in std_logic_vector(3 downto 0); - SD : in std_logic_vector(3 downto 0); - -- Status and control port - STAT_OP : out std_logic_vector (63 downto 0); - CTRL_OP : in std_logic_vector (63 downto 0); - STAT_REG_OUT : out std_logic_vector(127 downto 0); - STAT_DEBUG : out std_logic_vector (255 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - - - component trb_net16_med_ecp_fot_4_ctc is - generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO - -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" - ); - port( - CLK : in std_logic; - CLK_25 : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - CLEAR : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(3 downto 0); - MED_READ_OUT : out std_logic_vector(3 downto 0); - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); - MED_READ_IN : in std_logic_vector(3 downto 0); - - --SFP Connection - TXP : out std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - RXN : in std_logic_vector(3 downto 0); - SD : in std_logic_vector(3 downto 0); - - -- Status and control port - STAT_OP : out std_logic_vector (63 downto 0); - CTRL_OP : in std_logic_vector (63 downto 0); - STAT_REG_OUT : out std_logic_vector (511 downto 0); - STAT_DEBUG : out std_logic_vector (255 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - - - component trb_net16_med_ecp_sfp is - generic( - SERDES_NUM : integer range 0 to 3 := 0; - EXT_CLOCK : integer range 0 to 1 := c_NO - ); - port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - - - component trb_net16_med_ecp_sfp_gbe is - generic( - SERDES_NUM : integer range 0 to 3 := 0; - EXT_CLOCK : integer range 0 to 1 := c_NO; - USE_200_MHZ : integer range 0 to 1 := c_NO - ); - port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - - component trb_net16_med_ecp_sfp_4 is - generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO - -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" - ); - port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(3 downto 0); - MED_READ_OUT : out std_logic_vector(3 downto 0); - MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); - MED_READ_IN : in std_logic_vector(3 downto 0); - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic_vector(3 downto 0); - SD_RXD_N_IN : in std_logic_vector(3 downto 0); - SD_TXD_P_OUT : out std_logic_vector(3 downto 0); - SD_TXD_N_OUT : out std_logic_vector(3 downto 0); - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); - SD_LOS_IN : in std_logic_vector(3 downto 0); - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); - -- Status and control port - STAT_OP : out std_logic_vector (4*16-1 downto 0); - CTRL_OP : in std_logic_vector (4*16-1 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - component trb_net16_med_ecp_sfp_4_gbe is - generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO - -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" - ); - port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(3 downto 0); - MED_READ_OUT : out std_logic_vector(3 downto 0); - MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); - MED_READ_IN : in std_logic_vector(3 downto 0); - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic_vector(3 downto 0); - SD_RXD_N_IN : in std_logic_vector(3 downto 0); - SD_TXD_P_OUT : out std_logic_vector(3 downto 0); - SD_TXD_N_OUT : out std_logic_vector(3 downto 0); - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); - SD_LOS_IN : in std_logic_vector(3 downto 0); - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); - -- Status and control port - STAT_OP : out std_logic_vector (4*16-1 downto 0); - CTRL_OP : in std_logic_vector (4*16-1 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) - ); - end component; - - - - - - component trb_net16_med_16_CC is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; - - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); - end component; - - - - - component trb_net16_med_16_IC is - generic( - DATA_CLK_OUT_PHASE : std_logic := '1' - ); - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_CLK_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; - DATA_CLK_IN : in std_logic; - - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); - end component; - - - - - component trb_net16_med_tlk is - port ( - RESET : in std_logic; - CLK : in std_logic; - TLK_CLK : in std_logic; - TLK_ENABLE : out std_logic; - TLK_LCKREFN : out std_logic; - TLK_LOOPEN : out std_logic; - TLK_PRBSEN : out std_logic; - TLK_RXD : in std_logic_vector(15 downto 0); - TLK_RX_CLK : in std_logic; - TLK_RX_DV : in std_logic; - TLK_RX_ER : in std_logic; - TLK_TXD : out std_logic_vector(15 downto 0); - TLK_TX_EN : out std_logic; - TLK_TX_ER : out std_logic; - SFP_LOS : in std_logic; - SFP_TX_DIS : out std_logic; - MED_DATAREADY_IN : in std_logic; - MED_READ_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - STAT : out std_logic_vector (63 downto 0); - STAT_MONITOR : out std_logic_vector ( 100 downto 0); - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) - --connect STAT(0) to LED - ); - end component; - - - - - - component trb_net_onewire is - generic( - USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; - CLK_PERIOD : integer := 10 --clk period in ns - ); - port( - CLK : in std_logic; - RESET : in std_logic; - READOUT_ENABLE_IN : in std_logic := '1'; - --connection to 1-wire interface - ONEWIRE : inout std_logic; - MONITOR_OUT : out std_logic; - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - - component trb_net_onewire_listener is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - MONITOR_IN : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - - component trb_net16_obuf is - generic ( - DATA_COUNT_WIDTH : integer := 5; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - CTRL_SETTINGS : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0); - TIMER_TICKS_IN : in std_logic_vector (1 downto 0) - ); - end component; - - - - - - - - - component trb_net16_obuf_nodata is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - --STAT - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; - - - - - component pll_in100_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic - ); - end component; - - - - component pll_in100_out20 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; - - - component pll_in200_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic - ); - end component; - - - component pll_in100_out25 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; - - - component pll25 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLKOP : out std_logic; - CLKOK : out std_logic; - LOCK : out std_logic - ); - end component; - - - - - - - component pll_in25_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; - - - - - - - component trb_net_pattern_gen is - generic ( - WIDTH : integer := 6 - ); - port( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) - ); - end component; - - - - - - - component trb_net_priority_arbiter is - generic ( - WIDTH : integer := 2 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (9 downto 0) - ); - end component; - - - - component pulse_sync is - port( - CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; - PULSE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - PULSE_B_OUT : out std_logic - ); - end component; - - - - component ram_dp is - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; - - - - - component ram_dp_rw - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; - - - - - component trb_net16_regIO is - generic ( - NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); - --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - CLOCK_FREQ : integer range 1 to 200 := 100 --MHz - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - - --Port to write Unique ID (-> 1-wire) - IDRAM_DATA_IN : in std_logic_vector(15 downto 0); - IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); - IDRAM_WR_IN : in std_logic; - - --Informations - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - TRIGGER_MONITOR : in std_logic; - GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds - LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK : out std_logic; --1 tick every microsecond - TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds - - --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); - --Custom Register in / out - REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); - COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0); - COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0); - STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); - CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); - --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - DAT_READ_ENABLE_OUT : out std_logic; - DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATAREADY_IN : in std_logic; - DAT_NO_MORE_DATA_IN : in std_logic; - DAT_WRITE_ACK_IN : in std_logic; - DAT_UNKNOWN_ADDR_IN : in std_logic; - DAT_TIMEOUT_OUT : out std_logic; - - --Additional write access to ctrl registers - STAT : out std_logic_vector(31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) - ); - end component; - - - - - - component trb_net16_regio_bus_handler is - generic( - PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; - PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); - PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) - ); - port( - CLK : in std_logic; - RESET : in std_logic; - DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - DAT_READ_ENABLE_IN : in std_logic; -- read pulse - DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse - DAT_TIMEOUT_IN : in std_logic; -- access timed out - DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested - DAT_WRITE_ACK_OUT : out std_logic; -- data accepted - DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - - BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); - BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); - BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - - BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); - BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - - STAT_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; - - - - - component trb_net_reset_handler is - generic( - RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff" - ); - port( - CLEAR_IN : in std_logic; -- reset input (high active, async) - CLEAR_N_IN : in std_logic; -- reset input (low active, async) - CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock - PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) - RESET_IN : in std_logic; -- general reset signal (SYSCLK) - TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK) - CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! - RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK) - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - - - component rom_16x8 is - generic( - INIT0 : std_logic_vector(15 downto 0) := x"0000"; - INIT1 : std_logic_vector(15 downto 0) := x"0000"; - INIT2 : std_logic_vector(15 downto 0) := x"0000"; - INIT3 : std_logic_vector(15 downto 0) := x"0000"; - INIT4 : std_logic_vector(15 downto 0) := x"0000"; - INIT5 : std_logic_vector(15 downto 0) := x"0000"; - INIT6 : std_logic_vector(15 downto 0) := x"0000"; - INIT7 : std_logic_vector(15 downto 0) := x"0000" - ); - port( - CLK : in std_logic; - a : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(15 downto 0) - ); - end component; - - - - component trb_net16_rx_control is - port( - RESET_IN : in std_logic; - QUAD_RST_IN : in std_logic; - -- raw data from SerDes receive path - CLK_IN : in std_logic; - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - RX_CV_IN : in std_logic; - RX_DISP_ERR_IN : in std_logic; - RX_ALLOW_IN : in std_logic; - -- media interface - SYSCLK_IN : in std_logic; -- 100MHz master clock - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - -- request retransmission in case of error while receiving - REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse - REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); - -- command decoding - START_RETRANSMIT_OUT : out std_logic; - START_POSITION_OUT : out std_logic_vector( 7 downto 0); - -- reset handling - SEND_RESET_WORDS_OUT : out std_logic; - MAKE_TRBNET_RESET_OUT : out std_logic; - -- Status signals - PACKET_TIMEOUT_OUT : out std_logic; - ENABLE_CORRECTION_IN : in std_logic; - -- Debugging - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(95 downto 0) - ); - end component; - - - - - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - DEBUG_OUT : out std_logic_vector(15 downto 0); - STAT_BUFFER : out STD_LOGIC - ); - end component; - - - - - - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := 18; - VERSION: integer := std_SBUF_VERSION); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - - - component trb_net_sbuf2 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - - component trb_net_sbuf3 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - - component trb_net_sbuf4 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - - component trb_net_sbuf5 is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- input - COMB_DATAREADY_IN : in std_logic; - COMB_next_READ_OUT : out std_logic; - COMB_DATA_IN : in std_logic_vector(18 downto 0); - -- output - SYN_DATAREADY_OUT : out std_logic; - SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word - SYN_READ_IN : in std_logic; - -- Status and control port - DEBUG : out std_logic_vector(7 downto 0); - DEBUG_BSM : out std_logic_vector(3 downto 0); - DEBUG_WCNT : out std_logic_vector(4 downto 0); - STAT_BUFFER : out std_logic - ); - end component; - - component trb_net_sbuf6 is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- input - COMB_DATAREADY_IN : in std_logic; - COMB_next_READ_OUT : out std_logic; - COMB_DATA_IN : in std_logic_vector(18 downto 0); - -- output - SYN_DATAREADY_OUT : out std_logic; - SYN_DATA_OUT : out std_logic_vector(18 downto 0); - SYN_READ_IN : in std_logic; - -- Status and control port - DEBUG : out std_logic_vector(7 downto 0); - DEBUG_BSM : out std_logic_vector(3 downto 0); - DEBUG_WCNT : out std_logic_vector(4 downto 0); - STAT_BUFFER : out std_logic - ); - end component; - - component slv_mac_memory is - port( - CLK : in std_logic; - RESET : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(7 downto 0); - MEM_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - - - component slv_register is - generic( - RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - - - component spi_databus_memory is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - BUS_ADDR_IN : in std_logic_vector(5 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_ACK_OUT : out std_logic; - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - -- state machine connections - BRAM_ADDR_IN : in std_logic_vector(7 downto 0); - BRAM_WR_D_OUT : out std_logic_vector(7 downto 0); - BRAM_RD_D_IN : in std_logic_vector(7 downto 0); - BRAM_WE_IN : in std_logic; - -- Status lines - STAT : out std_logic_vector(63 downto 0) -- DEBUG - ); - end component; - - - component spi_dpram_32_to_8 is - port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(7 downto 0); - AddressA: in std_logic_vector(5 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(7 downto 0)); - end component; - - - component spi_slim is - port( - SYSCLK : in std_logic; -- 100MHz sysclock - RESET : in std_logic; -- synchronous reset - -- Command interface - START_IN : in std_logic; -- one start pulse - BUSY_OUT : out std_logic; -- SPI transactions are ongoing - CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte - ADL_IN : in std_logic_vector(7 downto 0); -- low address byte - ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte - ADH_IN : in std_logic_vector(7 downto 0); -- high address byte - MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD) - TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next - TX_RD_OUT : out std_logic; - RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte - RX_WR_OUT : out std_logic; - TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD - -- SPI interface - SPI_SCK_OUT : out std_logic; - SPI_CS_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - -- DEBUG - CLK_EN_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - - component spi_master is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_BUSY_OUT : out std_logic; - BUS_ACK_OUT : out std_logic; - BUS_ADDR_IN : in std_logic_vector(0 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - -- BRAM for read/write data - BRAM_A_OUT : out std_logic_vector(7 downto 0); - BRAM_WR_D_IN : in std_logic_vector(7 downto 0); - BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); - BRAM_WE_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - - - - - - component signal_sync is - generic( - WIDTH : integer := 1; -- - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; - - - - - - - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := c_YES; - --even when 0, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) - ); - end component; - - - - - - component trb_net16_term_buf is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic - ); - end component; - - - - - - component trb_net16_term_ibuf is - generic( - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - -- Internal direction port - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - INT_ERROR_OUT: out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0) - ); - end component; - - - - - component trb_net16_trigger is - generic ( - USE_TRG_PORT : integer range 0 to 1 := c_YES; - --even when NO, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high only - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- Trigger information output - TRG_TYPE_OUT : out std_logic_vector (3 downto 0); - TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); - TRG_CODE_OUT : out std_logic_vector (7 downto 0); - TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0); - TRG_RECEIVED_OUT : out std_logic; - TRG_RELEASE_IN : in std_logic; - TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) - ); - end component; - - - - component trb_net16_tx_control is - port( - TXCLK_IN : in std_logic; - RXCLK_IN : in std_logic; - SYSCLK_IN : in std_logic; - RESET_IN : in std_logic; - - TX_DATA_IN : in std_logic_vector(15 downto 0); - TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); - TX_WRITE_IN : in std_logic; - TX_READ_OUT : out std_logic; - - TX_DATA_OUT : out std_logic_vector( 7 downto 0); - TX_K_OUT : out std_logic; - - REQUEST_RETRANSMIT_IN : in std_logic; - REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); - - START_RETRANSMIT_IN : in std_logic; - START_POSITION_IN : in std_logic_vector( 7 downto 0); - - SEND_LINK_RESET_IN : in std_logic; - TX_ALLOW_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); - end component; - - - - - component wide_adder_17x16 is - generic( - SIZE : integer := 16; - WORDS: integer := 17 --fixed - ); - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); - START_IN : in std_logic; - VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); - RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); - OVERFLOW_OUT : out std_logic; - READY_OUT : out std_logic - ); - end component; - - - component trb_net_bridge_etrax_apl is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); - APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); - APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); - CPU_READ : in STD_LOGIC; - CPU_WRITE : in STD_LOGIC; - CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); - CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); - CPU_DATAREADY_OUT : out std_logic; - CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); - STAT : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (31 downto 0) - ); - end component; - - + DATA_COUNT_OUT : out std_logic_vector(10 downto 0); + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + + + + + component trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); + port( read_clock_in : in std_logic; + write_clock_in : in std_logic; + read_enable_in : in std_logic; + write_enable_in : in std_logic; + fifo_gsr_in : in std_logic; + write_data_in : in std_logic_vector(17 downto 0); + read_data_out : out std_logic_vector(17 downto 0); + full_out : out std_logic; + empty_out : out std_logic; + fifostatus_out : out std_logic_vector(3 downto 0); + valid_read_out : out std_logic; + almost_empty_out : out std_logic; + almost_full_out : out std_logic + ); + end component; + + + + + + + component fifo_dualclock_width_16_reg is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); + end component; + + + + +-- component trb_net16_gbe_buf is +-- generic( +-- DO_SIMULATION : integer range 0 to 1 := 1; +-- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +-- ); +-- port( +-- CLK : in std_logic; +-- TEST_CLK : in std_logic; -- only for simulation! +-- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode +-- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode +-- RESET : in std_logic; +-- GSR_N : in std_logic; +-- -- Debug +-- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); +-- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); +-- -- configuration interface +-- IP_CFG_START_IN : in std_logic; +-- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); +-- IP_CFG_DONE_OUT : out std_logic; +-- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); +-- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); +-- IP_CFG_MEM_CLK_OUT : out std_logic; +-- MR_RESET_IN : in std_logic; +-- MR_MODE_IN : in std_logic; +-- MR_RESTART_IN : in std_logic; +-- -- gk 29.03.10 +-- SLV_ADDR_IN : in std_logic_vector(7 downto 0); +-- SLV_READ_IN : in std_logic; +-- SLV_WRITE_IN : in std_logic; +-- SLV_BUSY_OUT : out std_logic; +-- SLV_ACK_OUT : out std_logic; +-- SLV_DATA_IN : in std_logic_vector(31 downto 0); +-- SLV_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- gk 22.04.10 +-- -- registers setup interface +-- BUS_ADDR_IN : in std_logic_vector(7 downto 0); +-- BUS_DATA_IN : in std_logic_vector(31 downto 0); +-- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 +-- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 +-- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 +-- BUS_ACK_OUT : out std_logic; -- gk 26.04.10 +-- -- gk 23.04.10 +-- LED_PACKET_SENT_OUT : out std_logic; +-- LED_AN_DONE_N_OUT : out std_logic; +-- -- CTS interface +-- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); +-- CTS_CODE_IN : in std_logic_vector (7 downto 0); +-- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); +-- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); +-- CTS_START_READOUT_IN : in std_logic; +-- CTS_DATA_OUT : out std_logic_vector (31 downto 0); +-- CTS_DATAREADY_OUT : out std_logic; +-- CTS_READOUT_FINISHED_OUT : out std_logic; +-- CTS_READ_IN : in std_logic; +-- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); +-- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); +-- -- Data payload interface +-- FEE_DATA_IN : in std_logic_vector (15 downto 0); +-- FEE_DATAREADY_IN : in std_logic; +-- FEE_READ_OUT : out std_logic; +-- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); +-- FEE_BUSY_IN : in std_logic; +-- --SFP Connection +-- SFP_RXD_P_IN : in std_logic; +-- SFP_RXD_N_IN : in std_logic; +-- SFP_TXD_P_OUT : out std_logic; +-- SFP_TXD_N_OUT : out std_logic; +-- SFP_REFCLK_P_IN : in std_logic; +-- SFP_REFCLK_N_IN : in std_logic; +-- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) +-- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) +-- SFP_TXDIS_OUT : out std_logic; -- SFP disable +-- -- debug ports +-- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +-- ); +-- end component; + + + + component handler_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --LVL1 Handler + LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts + LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type + LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --IPU Handler + IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + + IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_HDR_DATA_READ_IN : in std_logic; + IPU_HDR_DATA_EMPTY_OUT : out std_logic; + + TMG_TRG_ERROR_IN : in std_logic; + --Status + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + + component handler_ipu is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --From Data Handler + DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); + DAT_HDR_DATA_READ_OUT : out std_logic; + DAT_HDR_DATA_EMPTY_IN : in std_logic; + + --To IPU Channel + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + + --Debug + STATUS_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + component handler_lvl1 is + generic( + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES + ); + port( + RESET : in std_logic; + RESET_STATS_IN : in std_logic; + CLOCK : in std_logic; + --Timing Trigger + LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics + LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS + LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS + + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release + LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter + LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected + LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); + LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10 + LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10 + LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10 + SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10 + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE + LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE + + --Stat/Control + STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers + TRG_ENABLE_IN : in std_logic; -- trigger enable flag + TRG_INVERT_IN : in std_logic; -- trigger invert flag + COUNTERS_STATUS_OUT : out std_logic_vector (63 downto 0); + --Debug + DEBUG_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + + + + + component handler_trigger_and_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + RESET_IPU : in std_logic; + + --To Endpoint + --Timing Trigger (registered) + LVL1_VALID_TRIGGER_IN : in std_logic; + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + --LVL1_handler connection + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --IPU channel + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + + --To FEE + --FEE to Trigger + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + + --Data Input from FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + TMG_TRG_ERROR_IN : in std_logic; + --Status Registers + STATUS_OUT : out std_logic_vector(127 downto 0); + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); + STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0); + STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); + STATISTICS_READY_OUT : out std_logic; + STATISTICS_READ_IN : in std_logic; + STATISTICS_UNKNOWN_OUT : out std_logic; + + --Debug + DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); + DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0) + + ); + end component; + + + + + + + + component trb_net16_ibuf is + generic ( + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_READ_IN : in std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_READ_IN : in std_logic; + INT_ERROR_OUT : out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0); + CTRL_STAT : in std_logic_vector (15 downto 0) + ); + end component; + + + + + + + component fifo_36x512 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic + ); + end component; + + +--component fifo_var_oreg is + --generic( + --FIFO_WIDTH : integer range 1 to 64 := 36; + --FIFO_DEPTH : integer range 1 to 16 := 8 + --); + --port( + --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); + --Clock : in std_logic; + --WrEn : in std_logic; + --RdEn : in std_logic; + --Reset : in std_logic; + --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); + --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); + --WCNT : out std_logic_vector(FIFO_DEPTH downto 0); + --Empty : out std_logic; + --Full : out std_logic; + --AlmostFull : out std_logic + --); +--end component; + + + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0'); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); + TIMER_TICKS_IN : in std_logic_vector (1 downto 0); + CTRL_STAT : in std_logic_vector (15 downto 0) + ); + end component; + + + + + + + component trb_net16_io_multiplexer is + generic( + USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO) + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + + + + + component trb_net16_ipudata is + generic( + DO_CHECKS : integer range c_NO to c_YES := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_LENGTH_OUT : out std_logic_vector (15 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + + --Information received with request + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_CODE_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + + + + + component ipu_dummy is + port( CLK_IN : in std_logic; -- 100MHz local clock + CLEAR_IN : in std_logic; + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value + MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value + CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + -- DHDR buffer + LVL1_FIFO_RD_OUT : out std_logic; + LVL1_FIFO_EMPTY_IN : in std_logic; + LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + component trb_net16_lsm_sfp is + generic( + CHECK_FOR_CV : integer := c_YES + ); + port( + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available + -- status signals + SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) + SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) + SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) + SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) + SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct) + SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD) + -- control signals + FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset + LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset + TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation + RX_ALLOW_OUT : out std_logic; -- allow normal receive operation + SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order) + -- debug signals + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + + + component trb_net16_med_8_SDR_OS is + generic( + TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + + -- Media direction port + TX_DATA_OUT : out std_logic_vector (7 downto 0); + TX_CLK_OUT : out std_logic; + TX_CTRL_OUT : out std_logic_vector (1 downto 0); + RX_DATA_IN : in std_logic_vector (7 downto 0); + RX_CLK_IN : in std_logic; + RX_CTRL_IN : in std_logic_vector (1 downto 0); + + -- Status and control port + STAT_OP: out std_logic_vector (15 downto 0); + CTRL_OP: in std_logic_vector (15 downto 0); + + STAT: out std_logic_vector (31 downto 0); + CTRL: in std_logic_vector (31 downto 0) + ); + end component; + + + + + + + + component trb_net16_med_ecp_fot is + port( + CLK : in std_logic; + CLK_25 : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + CLEAR : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + --SFP Connection + TXP : out std_logic; + TXN : out std_logic; + RXP : in std_logic; + RXN : in std_logic; + SD : in std_logic; + + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_REG_OUT : out std_logic_vector(127 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (15 downto 0) + ); + end component; + + + + + + + + + component trb_net16_med_ecp_fot_4 is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; + CLK_25 : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + --SFP Connection + TXP : out std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + RXN : in std_logic_vector(3 downto 0); + SD : in std_logic_vector(3 downto 0); + -- Status and control port + STAT_OP : out std_logic_vector (63 downto 0); + CTRL_OP : in std_logic_vector (63 downto 0); + STAT_REG_OUT : out std_logic_vector(127 downto 0); + STAT_DEBUG : out std_logic_vector (255 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + component trb_net16_med_ecp_fot_4_ctc is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; + CLK_25 : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + CLEAR : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + + --SFP Connection + TXP : out std_logic_vector(3 downto 0); + TXN : out std_logic_vector(3 downto 0); + RXP : in std_logic_vector(3 downto 0); + RXN : in std_logic_vector(3 downto 0); + SD : in std_logic_vector(3 downto 0); + + -- Status and control port + STAT_OP : out std_logic_vector (63 downto 0); + CTRL_OP : in std_logic_vector (63 downto 0); + STAT_REG_OUT : out std_logic_vector (511 downto 0); + STAT_DEBUG : out std_logic_vector (255 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + component trb_net16_med_ecp_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + component trb_net16_med_ecp_sfp_gbe is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO; + USE_200_MHZ : integer range 0 to 1 := c_NO + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + component trb_net16_med_ecp_sfp_4 is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); + SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + component trb_net16_med_ecp_sfp_4_gbe is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); + SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + + component trb_net16_med_16_CC is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); + end component; + + + + + component trb_net16_med_16_IC is + generic( + DATA_CLK_OUT_PHASE : std_logic := '1' + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_CLK_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + DATA_CLK_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); + end component; + + + + + component trb_net16_med_tlk is + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + MED_DATAREADY_IN : in std_logic; + MED_READ_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + STAT : out std_logic_vector (63 downto 0); + STAT_MONITOR : out std_logic_vector ( 100 downto 0); + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) + --connect STAT(0) to LED + ); + end component; + + + + + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic := '1'; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + MONITOR_OUT : out std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component trb_net_onewire_listener is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + MONITOR_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component trb_net16_obuf is + generic ( + DATA_COUNT_WIDTH : integer := 5; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + CTRL_SETTINGS : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0); + TIMER_TICKS_IN : in std_logic_vector (1 downto 0) + ); + end component; + + + + + + + + + component trb_net16_obuf_nodata is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + --STAT + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) + ); + end component; + + + + + component pll_in100_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic + ); + end component; + + + + component pll_in100_out20 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + + component pll_in200_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic + ); + end component; + + + component pll_in100_out25 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + + component pll25 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + CLKOK : out std_logic; + LOCK : out std_logic + ); + end component; + + + + + + + component pll_in25_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + + + + + + component trb_net_pattern_gen is + generic ( + WIDTH : integer := 6 + ); + port( + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) + ); + end component; + + + + + + + component trb_net_priority_arbiter is + generic ( + WIDTH : integer := 2 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL: in STD_LOGIC_VECTOR (9 downto 0) + ); + end component; + + + + component pulse_sync is + port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); + end component; + + + + component ram_dp is + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + dout1 : out std_logic_vector(width-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); + end component; + + + + + component ram_dp_rw + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); + end component; + + + + + component trb_net16_regIO is + generic ( + NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + + --Port to write Unique ID (-> 1-wire) + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + + --Informations + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + TRIGGER_MONITOR : in std_logic; + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK : out std_logic; --1 tick every microsecond + TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds + + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); + --Internal Data Port + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + DAT_WRITE_ACK_IN : in std_logic; + DAT_UNKNOWN_ADDR_IN : in std_logic; + DAT_TIMEOUT_OUT : out std_logic; + + --Additional write access to ctrl registers + STAT : out std_logic_vector(31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + component trb_net16_regio_bus_handler is + generic( + PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; + PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); + PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + ); + port( + CLK : in std_logic; + RESET : in std_logic; + DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + DAT_READ_ENABLE_IN : in std_logic; -- read pulse + DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse + DAT_TIMEOUT_IN : in std_logic; -- access timed out + DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested + DAT_WRITE_ACK_OUT : out std_logic; -- data accepted + DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + + BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + + BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); + BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component trb_net_reset_handler is + generic( + RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff" + ); + port( + CLEAR_IN : in std_logic; -- reset input (high active, async) + CLEAR_N_IN : in std_logic; -- reset input (low active, async) + CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock + PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) + RESET_IN : in std_logic; -- general reset signal (SYSCLK) + TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK) + CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! + RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK) + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + + + component rom_16x8 is + generic( + INIT0 : std_logic_vector(15 downto 0) := x"0000"; + INIT1 : std_logic_vector(15 downto 0) := x"0000"; + INIT2 : std_logic_vector(15 downto 0) := x"0000"; + INIT3 : std_logic_vector(15 downto 0) := x"0000"; + INIT4 : std_logic_vector(15 downto 0) := x"0000"; + INIT5 : std_logic_vector(15 downto 0) := x"0000"; + INIT6 : std_logic_vector(15 downto 0) := x"0000"; + INIT7 : std_logic_vector(15 downto 0) := x"0000" + ); + port( + CLK : in std_logic; + a : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(15 downto 0) + ); + end component; + + + + component trb_net16_rx_control is + port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- command decoding + START_RETRANSMIT_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(95 downto 0) + ); + end component; + + + + + component trb_net16_sbuf is + generic ( + VERSION : integer := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + DEBUG_OUT : out std_logic_vector(15 downto 0); + STAT_BUFFER : out STD_LOGIC + ); + end component; + + + + + + component trb_net_sbuf is + generic ( + DATA_WIDTH : integer := 18; + VERSION: integer := std_SBUF_VERSION); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + + component trb_net_sbuf2 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + component trb_net_sbuf3 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + component trb_net_sbuf4 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + component trb_net_sbuf5 is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- input + COMB_DATAREADY_IN : in std_logic; + COMB_next_READ_OUT : out std_logic; + COMB_DATA_IN : in std_logic_vector(18 downto 0); + -- output + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG : out std_logic_vector(7 downto 0); + DEBUG_BSM : out std_logic_vector(3 downto 0); + DEBUG_WCNT : out std_logic_vector(4 downto 0); + STAT_BUFFER : out std_logic + ); + end component; + + component trb_net_sbuf6 is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- input + COMB_DATAREADY_IN : in std_logic; + COMB_next_READ_OUT : out std_logic; + COMB_DATA_IN : in std_logic_vector(18 downto 0); + -- output + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(18 downto 0); + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG : out std_logic_vector(7 downto 0); + DEBUG_BSM : out std_logic_vector(3 downto 0); + DEBUG_WCNT : out std_logic_vector(4 downto 0); + STAT_BUFFER : out std_logic + ); + end component; + + component slv_mac_memory is + port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + + + component slv_register is + generic( + RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + + + component spi_databus_memory is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_ADDR_IN : in std_logic_vector(5 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- state machine connections + BRAM_ADDR_IN : in std_logic_vector(7 downto 0); + BRAM_WR_D_OUT : out std_logic_vector(7 downto 0); + BRAM_RD_D_IN : in std_logic_vector(7 downto 0); + BRAM_WE_IN : in std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG + ); + end component; + + + component spi_dpram_32_to_8 is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(7 downto 0); + AddressA: in std_logic_vector(5 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(7 downto 0)); + end component; + + + component spi_slim is + port( + SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + ADL_IN : in std_logic_vector(7 downto 0); -- low address byte + ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte + ADH_IN : in std_logic_vector(7 downto 0); -- high address byte + MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD) + TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next + TX_RD_OUT : out std_logic; + RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte + RX_WR_OUT : out std_logic; + TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + component spi_master is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(0 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- BRAM for read/write data + BRAM_A_OUT : out std_logic_vector(7 downto 0); + BRAM_WR_D_IN : in std_logic_vector(7 downto 0); + BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); + BRAM_WE_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + + + + + + component signal_sync is + generic( + WIDTH : integer := 1; -- + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + ); + end component; + + + + + + + + component trb_net16_term is + generic ( + USE_APL_PORT : integer range 0 to 1 := c_YES; + --even when 0, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) + ); + end component; + + + + + + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic + ); + end component; + + + + + + component trb_net16_term_ibuf is + generic( + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + -- Internal direction port + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + INT_ERROR_OUT: out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0) + ); + end component; + + + + + component trb_net16_trigger is + generic ( + USE_TRG_PORT : integer range 0 to 1 := c_YES; + --even when NO, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high only + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + + -- Trigger information output + TRG_TYPE_OUT : out std_logic_vector (3 downto 0); + TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); + TRG_CODE_OUT : out std_logic_vector (7 downto 0); + TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0); + TRG_RECEIVED_OUT : out std_logic; + TRG_RELEASE_IN : in std_logic; + TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) + ); + end component; + + + + component trb_net16_tx_control is + port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); + + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component wide_adder_17x16 is + generic( + SIZE : integer := 16; + WORDS: integer := 17 --fixed + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); + START_IN : in std_logic; + VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); + OVERFLOW_OUT : out std_logic; + READY_OUT : out std_logic + ); + end component; + + + component trb_net_bridge_etrax_apl is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_READ : in STD_LOGIC; + CPU_WRITE : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); + end component; + + end package; \ No newline at end of file diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd index 6f0020f..2bf6ebb 100644 --- a/trb_net_onewire.vhd +++ b/trb_net_onewire.vhd @@ -83,7 +83,6 @@ begin next_output_tmp <= output_tmp; inc_bitcounter <= '0'; next_send_bit <= send_bit; - next_recv_bit <= '0'; next_recv_bit_ready <= '0'; next_send_rom <= send_rom; next_conv_temp <= conv_temp; -- 2.43.0