From fbe82de045ff7c42d710876e2d8c2fc601bdd4d8 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 30 Sep 2010 15:50:19 +0000 Subject: [PATCH] *** empty log message *** --- basics/signal_delay.vhd | 22 + media_interfaces/trb_net16_lsm_sfp.vhd | 7 +- media_interfaces/trb_net16_med_ecp_fot.vhd | 647 ++++++++++------ .../trb_net16_med_ecp_fot_4_ctc.vhd | 721 ++++++++++++------ media_interfaces/trb_net16_rx_checker.vhd | 9 +- .../trb_net16_rx_comma_handler.vhd | 11 +- media_interfaces/trb_net16_rx_control.vhd | 30 +- .../trb_net16_rx_full_packets.vhd | 14 +- media_interfaces/trb_net16_tx_control.vhd | 266 ++++--- special/handler_data.vhd | 3 +- special/handler_lvl1.vhd | 5 +- special/spi_master.vhd | 2 +- testbenches/tb_fot_interface.vhd | 290 +++++++ testbenches/tb_trb_net16_tx_control.vhd | 271 +++++-- trb_net16_endpoint_hades_full.vhd | 276 ++++--- trb_net16_endpoint_hades_full_handler.vhd | 6 +- trb_net16_hub_base.vhd | 156 ++-- trb_net16_hub_func.vhd | 11 +- trb_net16_hub_ipu_logic.vhd | 42 +- trb_net16_hub_logic.vhd | 149 ++-- trb_net16_hub_streaming_port.vhd | 4 +- trb_net16_io_multiplexer.vhd | 36 +- trb_net16_iobuf.vhd | 6 +- trb_net16_obuf.vhd | 40 +- trb_net16_rx_packets.vhd | 12 +- trb_net_components.vhd | 93 ++- trb_net_std.vhd | 2 +- 27 files changed, 2160 insertions(+), 971 deletions(-) create mode 100644 basics/signal_delay.vhd create mode 100644 testbenches/tb_fot_interface.vhd diff --git a/basics/signal_delay.vhd b/basics/signal_delay.vhd new file mode 100644 index 0000000..0e3ad4f --- /dev/null +++ b/basics/signal_delay.vhd @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.trb_net_std.all; + +entity delay_signal is + generic( + INPUT_WIDTH : integer; + MAX_DEPTH : integer + ); + port( + ); +end entity; + +architecture arch of delay_signal is + +begin + +end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index ea34c51..5b20cc6 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -210,11 +210,6 @@ begin next_lane_rst <= '1'; end if; when WPAR => --- if ( (sfp_missing_in = '1') or ( sfp_los_in = '1') ) then --- NEXT_STATE <= SLEEP; -- SFP has been removed --- next_lane_rst <= '1'; --- next_ce_tctr <= '1'; --- els if( (sd_rxclk_bad_in = '0') and (sd_txclk_bad_in = '0') ) then -- NEXT_STATE <= WLOS; -- PLLs locked, signal present next_rst_tctr <= '1'; @@ -404,7 +399,7 @@ stat_op(8) <= '0'; stat_op(9) <= link_status_led; stat_op(10) <= '0'; -- Rx LED, made outside LSM stat_op(11) <= '0'; -- Tx LED, made outside LSM -stat_op(12) <= '0'; -- unused +stat_op(12) <= '1' when sd_cv_in /= "00" and CURRENT_STATE = LINK else '0'; -- CV found when in link state stat_op(13) <= '0'; stat_op(14) <= reset_me; -- reset out stat_op(15) <= '0'; -- protocol error diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 11d4091..202d74f 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -35,7 +35,7 @@ entity trb_net16_med_ecp_fot is -- Status and control port STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0); - STAT_REG_OUT : out std_logic_vector (31 downto 0); + STAT_REG_OUT : out std_logic_vector (127 downto 0); STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (15 downto 0) ); @@ -43,7 +43,9 @@ end entity; architecture trb_net16_med_ecp_fot_arch of trb_net16_med_ecp_fot is +-- Placer Directives attribute HGROUP : string; +-- for whole architecture attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; component serdes_fot_0 is @@ -91,65 +93,108 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; ); end component; - signal buf_med_data_out : std_logic_vector(15 downto 0); - signal buf_med_dataready_out : std_logic; + + signal link_error : std_logic_vector(7 downto 0); + signal link_error_q : std_logic_vector(7 downto 0); + signal reg_link_error : std_logic_vector(7 downto 0); + signal ffs_plol : std_logic; + signal link_ok : std_logic; + signal link_ok_q : std_logic; + signal tx_data : std_logic_vector(8-1 downto 0); + signal rx_data : std_logic_vector(8-1 downto 0); + signal ff_rxfullclk : std_logic; + signal ff_txfullclk : std_logic; + signal rx_k : std_logic; + signal tx_k : std_logic; + signal lane_rst : std_logic; + signal lane_rst_qtx : std_logic; + signal quad_rst : std_logic; + signal quad_rst_qtx : std_logic; + + signal byte_waiting : std_logic; + signal byte_buffer : std_logic_vector(8-1 downto 0); + signal fifo_reset : std_logic; + signal tx_fifo_dout : std_logic_vector(16-1 downto 0); + signal tx_fifo_data_in : std_logic_vector(16-1 downto 0); + signal tx_fifo_read_en : std_logic; + signal tx_fifo_write_en : std_logic; + signal tx_fifo_empty : std_logic; + signal tx_fifo_full : std_logic; + + signal tx_fifo_valid_read : std_logic; + signal tx_allow : std_logic; + signal tx_allow_del : std_logic; + signal tx_allow_qtx : std_logic; + + signal rx_data_reg : std_logic_vector(8-1 downto 0); + signal buf_rx_data_reg : std_logic_vector(8-1 downto 0); + signal buf_rx_data : std_logic_vector(8-1 downto 0); + signal buf_rx_k : std_logic; + signal rx_fifo_write_en : std_logic; + signal rx_fifo_read_en : std_logic; + signal rx_fifo_empty : std_logic; + signal rx_fifo_full : std_logic; + signal rx_fifo_dout : std_logic_vector(8-1 downto 0); + signal is_idle_word : std_logic; + signal rx_starting : std_logic; + signal rx_allow : std_logic; + signal rx_allow_del : std_logic; + signal rx_allow_qrx : std_logic; + signal sd_q : std_logic; + signal last_rx_fifo_read_en : std_logic; + signal last_rx_fifo_empty : std_logic; + signal last_last_rx_fifo_read_en : std_logic; + signal last_last_rx_fifo_empty : std_logic; + signal last_rx_fifo_dout : std_logic_vector(7 downto 0); + signal tx_fifo_valid_read_q : std_logic; + + signal buf_med_dataready_out : std_logic; + signal buf_med_read_out : std_logic; + signal buf_med_data_out : std_logic_vector(16-1 downto 0); signal buf_med_packet_num_out : std_logic_vector(2 downto 0); + signal byte_select : std_logic; + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal sfp_los : std_logic; + + signal led_counter : std_logic_vector(13 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + + signal FSM_STAT_OP : std_logic_vector(16-1 downto 0); + signal FSM_STAT_DEBUG : std_logic_vector(64-1 downto 0); + signal FSM_CTRL_OP : std_logic_vector(16-1 downto 0); - signal link_error : std_logic_vector(7 downto 0); - signal link_error_q : std_logic_vector(7 downto 0); - signal reg_link_error : std_logic_vector(7 downto 0); - signal ffs_plol : std_logic; - signal link_ok : std_logic; - signal link_ok_q : std_logic; - signal tx_data : std_logic_vector(8-1 downto 0); - signal rx_data : std_logic_vector(8-1 downto 0); - signal ff_rxfullclk : std_logic; - signal ff_txfullclk : std_logic; - signal rx_k : std_logic; - signal tx_k : std_logic; - signal lane_rst : std_logic; - signal lane_rst_qtx : std_logic; - signal quad_rst : std_logic; - signal quad_rst_qtx : std_logic; - - signal tx_allow : std_logic; - signal rx_allow : std_logic; - signal tx_allow_qtx : std_logic; - signal rx_allow_qrx : std_logic; - signal sd_q : std_logic; - signal sfp_los : std_logic; - - signal led_counter : std_logic_vector(11 downto 0); - signal rx_led : std_logic; - signal tx_led : std_logic; - - signal FSM_STAT_OP : std_logic_vector(16-1 downto 0); - signal FSM_STAT_DEBUG : std_logic_vector(64-1 downto 0); - signal FSM_CTRL_OP : std_logic_vector(16-1 downto 0); + signal send_reset_q : std_logic; + signal reset_word_cnt : std_logic_vector(4 downto 0); + signal send_reset_words : std_logic; + signal send_reset_words_q : std_logic; + signal make_trbnet_reset : std_logic; + signal make_trbnet_reset_q: std_logic; signal request_retransmit_i : std_logic; signal request_position_i : std_logic_vector( 7 downto 0); signal start_retransmit_i : std_logic; signal start_position_i : std_logic_vector( 7 downto 0); - signal packet_timeout_i : std_logic; signal debug_txcontrol_i : std_logic_vector(31 downto 0); signal debug_rxcontrol_i : std_logic_vector(31 downto 0); - signal send_reset_words : std_logic; - signal make_trbnet_reset : std_logic; + signal packet_timeout_i : std_logic; signal last_tx_k : std_logic; signal request_cnt_i : unsigned(7 downto 0); signal reset_rx_control : std_logic; - signal send_reset_words_ext : std_logic; - signal ffs_plol_low_stable : std_logic; - signal ffs_plol_counter : std_logic_vector(18 downto 0); - signal tx_lane_reset_q : std_logic; - signal tx_lane_reset : std_logic; + signal ffs_plol_low_stable : std_logic; + signal ffs_plol_counter : std_logic_vector(18 downto 0); + signal tx_lane_reset : std_logic; + + signal statreg_txcontrol_i : std_logic_vector(31 downto 0); + signal statreg_rxcontrol_i : std_logic_vector(63 downto 0); + begin ------------------------------------------------------------------------ ---Serdes ------------------------------------------------------------------------ + + --ff_rxfullclk <= clk_25; + --ff_rxfullclk <= ff_txfullclk; + THE_SERDES: serdes_fot_0 port map( core_txrefclk => CLK_25, @@ -172,7 +217,7 @@ begin ff_disp_err_ch0 => link_error(0), ff_cv_ch0 => link_error(1), ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst_qtx, --lane_rst(0), + ffc_lane_tx_rst_ch0 => tx_lane_reset, ffc_lane_rx_rst_ch0 => lane_rst_qtx, ffc_txpwdnb_ch0 => '1', ffc_rxpwdnb_ch0 => '1', @@ -197,10 +242,10 @@ begin ----------------------------------------------------------------------- THE_TX_CONTROL : trb_net16_tx_control port map( - TXCLK_IN => CLK_25, + TXCLK_IN => ff_txfullclk, RXCLK_IN => ff_rxfullclk, SYSCLK_IN => CLK, - RESET_IN => lane_rst, + RESET_IN => tx_lane_reset, TX_DATA_IN => MED_DATA_IN, TX_WRITE_IN => MED_DATAREADY_IN, @@ -213,13 +258,41 @@ begin REQUEST_POSITION_IN => request_position_i, START_RETRANSMIT_IN => start_retransmit_i, START_POSITION_IN => start_position_i, - SEND_LINK_RESET_IN => send_reset_words_ext, + SEND_LINK_RESET_IN => CTRL_OP(15), TX_ALLOW_IN => tx_allow, - DEBUG_OUT => debug_txcontrol_i + DEBUG_OUT => debug_txcontrol_i, + STAT_REG_OUT => statreg_txcontrol_i ); + +----------------------------------------------------------------------- +--TX Reset +----------------------------------------------------------------------- + + tx_lane_reset <= not ffs_plol_low_stable or RESET; + + proc_plol_stable : process(CLEAR, CLK_25) + begin + if CLEAR = '1' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif rising_edge(CLK_25) then + if ffs_plol = '1' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif ffs_plol_counter(18) = '1' then + ffs_plol_low_stable <= '1'; + ffs_plol_counter <= ffs_plol_counter; + else + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= ffs_plol_counter + 1; + end if; + end if; + end process; + + ----------------------------------------------------------------------- --RX Control ----------------------------------------------------------------------- @@ -233,7 +306,7 @@ begin RX_K_IN => rx_k, RX_CV_IN => link_error(1), RX_DISP_ERR_IN => link_error(0), - RX_ALLOW_IN => rx_allow_qrx, + RX_ALLOW_IN => rx_allow, -- media interface SYSCLK_IN => CLK, MED_DATA_OUT => buf_med_data_out, @@ -253,155 +326,282 @@ begin PACKET_TIMEOUT_OUT => packet_timeout_i, -- Debugging ENABLE_CORRECTION_IN => CTRL_OP(8), - DEBUG_OUT => debug_rxcontrol_i + DEBUG_OUT => debug_rxcontrol_i, + STAT_REG_OUT => statreg_rxcontrol_i ); -reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); +reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); + +MED_DATA_OUT <= buf_med_data_out; +MED_DATAREADY_OUT <= buf_med_dataready_out; +MED_PACKET_NUM_OUT <= buf_med_packet_num_out; + +-- +-- +-- ----------------------------------------------------------------------- +-- --RX Control (25) +-- ----------------------------------------------------------------------- +-- +-- THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport +-- generic map( +-- USE_STATUS_FLAGS => c_NO +-- ) +-- port map( +-- read_clock_in => clk, +-- write_clock_in => ff_rxfullclk, +-- read_enable_in => rx_fifo_read_en, +-- write_enable_in => rx_fifo_write_en, +-- fifo_gsr_in => fifo_reset, +-- write_data_in => "00" & x"00" & rx_data_reg(7 downto 0), +-- read_data_out(7 downto 0) => rx_fifo_dout, +-- full_out => rx_fifo_full, +-- empty_out => rx_fifo_empty +-- ); +-- +-- THE_WRITE_RX_FIFO_PROC: process( ff_rxfullclk ) +-- begin +-- if( rising_edge(ff_rxfullclk) ) then +-- buf_rx_data(7 downto 0) <= rx_data(7 downto 0); +-- buf_rx_k <= rx_k; +-- if( (reset = '1') or (rx_allow_qrx = '0') ) then +-- rx_fifo_write_en <= '0'; +-- is_idle_word <= '1'; +-- rx_starting <= '1'; +-- else +-- rx_data_reg(7 downto 0) <= buf_rx_data(7 downto 0); +-- if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then +-- rx_fifo_write_en <= '1'; +-- else +-- rx_fifo_write_en <= '0'; +-- end if; +-- if ( buf_rx_k = '1' ) then +-- is_idle_word <= '1'; +-- rx_starting <= '0'; +-- elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then +-- is_idle_word <= '0'; +-- end if; +-- end if; +-- end if; +-- end process THE_WRITE_RX_FIFO_PROC; +-- +-- +-- THE_CNT_RESET_PROC : process( ff_rxfullclk ) +-- begin +-- if rising_edge(ff_rxfullclk) then +-- if reset = '1' then +-- send_reset_words <= '0'; +-- make_trbnet_reset <= '0'; +-- reset_word_cnt(4 downto 0) <= (others => '0'); +-- else +-- send_reset_words <= '0'; +-- make_trbnet_reset <= '0'; +-- if buf_rx_data(7 downto 0) = x"FE" and buf_rx_k = '1' then +-- if reset_word_cnt(4) = '0' then +-- reset_word_cnt(4 downto 0) <= reset_word_cnt(4 downto 0) + 1; +-- else +-- send_reset_words <= '1'; +-- end if; +-- else +-- reset_word_cnt(4 downto 0) <= (others => '0'); +-- make_trbnet_reset <= reset_word_cnt(4); +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- --RX Control (100) +-- --------------------- +-- process( clk ) +-- begin +-- if( rising_edge(clk) ) then +-- if( reset = '1' ) then +-- buf_med_dataready_out <= '0'; +-- byte_select <= '0'; +-- last_rx_fifo_read_en <= '0'; +-- else +-- last_rx_fifo_read_en <= rx_fifo_read_en; +-- last_rx_fifo_empty <= rx_fifo_empty; +-- last_last_rx_fifo_read_en <= last_rx_fifo_read_en; +-- last_last_rx_fifo_empty <= last_rx_fifo_empty; +-- last_rx_fifo_dout <= rx_fifo_dout; +-- buf_med_dataready_out <= '0'; +-- if( (last_last_rx_fifo_empty = '0') and (last_last_rx_fifo_read_en = '1') ) then +-- if( byte_select = '1' ) then +-- buf_MED_DATA_OUT(15 downto 0) <= last_rx_fifo_dout(7 downto 0) +-- & buf_MED_DATA_OUT(7 downto 0); +-- buf_MED_DATAREADY_OUT <= '1'; +-- else +-- buf_MED_DATA_OUT(15 downto 0) <= x"00" & last_rx_fifo_dout(7 downto 0); +-- end if; +-- byte_select <= not byte_select; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- rx_fifo_read_en <= rx_allow_del and not rx_fifo_empty; +-- MED_DATA_OUT(15 downto 0) <= buf_MED_DATA_OUT(15 downto 0); +-- MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; +-- MED_PACKET_NUM_OUT <= rx_counter; +-- +-- --rx packet counter +-- --------------------- +-- THE_RX_PACKETS_PROC: process( clk ) +-- begin +-- if( rising_edge(clk) ) then +-- if( (reset = '1') or (rx_allow = '0') ) then +-- rx_counter <= c_H0; +-- else +-- if( buf_med_dataready_out = '1' ) then +-- if( rx_counter = c_max_word_number ) then +-- rx_counter <= (others => '0'); +-- else +-- rx_counter <= rx_counter + 1; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; + + + +--Link State machine +--------------------- + + + CLK_TO_TX_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset, + D_IN(0) => lane_rst, + D_IN(1) => quad_rst, + CLK0 => CLK, + CLK1 => ff_txfullclk, + D_OUT(0) => lane_rst_qtx, + D_OUT(1) => quad_rst_qtx + ); + + RX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 9 + ) + port map( + RESET => reset, + D_IN(7 downto 0) => link_error, + D_IN(8) => link_ok, + CLK0 => ff_rxfullclk, + CLK1 => CLK, + D_OUT(7 downto 0) => link_error_q, + D_OUT(8) => link_ok_q + ); + + SYNC_INPUT_TO_CLK : signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset, + D_IN(0) => sd, + D_IN(1) => rx_allow, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => sd_q, + D_OUT(1) => rx_allow_del + ); + + THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => RESET, + D_IN(0) => rx_allow, + CLK0 => CLK, + CLK1 => ff_rxfullclk, + D_OUT(0) => rx_allow_qrx + ); + + + SYNC_RESET_DETECT_1 : signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => send_reset_words, + D_IN(1) => make_trbnet_reset, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => send_reset_words_q, + D_OUT(1) => make_trbnet_reset_q + ); ------------------------------------------------------------------------ ---Link State Machine ------------------------------------------------------------------------ - THE_SFP_LSM: trb_net16_lsm_sfp - generic map( - CHECK_FOR_CV => c_NO - ) - port map( - SYSCLK => CLK, - RESET => reset, - CLEAR => clear, - SFP_MISSING_IN => '0', - SFP_LOS_IN => sfp_los, - SD_LINK_OK_IN => link_ok_q, - SD_LOS_IN => link_error_q(2), - SD_TXCLK_BAD_IN => ffs_plol, - SD_RXCLK_BAD_IN => link_error_q(7), - SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN => "10", - SD_CV_IN(0) => link_error_q(1), - SD_CV_IN(1) => '0', - FULL_RESET_OUT => quad_rst, - LANE_RESET_OUT => lane_rst, - TX_ALLOW_OUT => tx_allow, - RX_ALLOW_OUT => rx_allow, - SWAP_BYTES_OUT => open, - STAT_OP => FSM_STAT_OP(15 downto 0), - CTRL_OP => FSM_CTRL_OP(15 downto 0), - STAT_DEBUG => FSM_STAT_DEBUG(31 downto 0) - ); +--LED Signals +--------------------- + THE_TX_RX_LED_PROC: process( CLK ) + begin + if( rising_edge(CLK) ) then + led_counter <= led_counter + 1; + if ( buf_med_dataready_out = '1' ) then + rx_led <= '1'; + elsif( led_counter = 0 ) then + rx_led <= '0'; + end if; + if( MED_DATAREADY_IN = '1' ) then + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + end if; + end process; ------------------------------------------------------------------------ ---I/O ------------------------------------------------------------------------ +----------------------------------------------------------- +--Link State Machine +----------------------------------------------------------- + + THE_SFP_LSM: trb_net16_lsm_sfp + generic map( + CHECK_FOR_CV => c_NO + ) + port map( + SYSCLK => CLK, + RESET => reset, + CLEAR => clear, + SFP_MISSING_IN => '0', + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok_q, + SD_LOS_IN => link_error_q(2), + SD_TXCLK_BAD_IN => tx_lane_reset, + SD_RXCLK_BAD_IN => link_error_q(7), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => "10", + SD_CV_IN(0) => link_error_q(1), + SD_CV_IN(1) => '0', + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => open, + STAT_OP => FSM_STAT_OP(15 downto 0), + CTRL_OP => FSM_CTRL_OP(15 downto 0), + STAT_DEBUG => FSM_STAT_DEBUG(31 downto 0) + ); - MED_DATA_OUT <= buf_med_data_out; - MED_PACKET_NUM_OUT <= buf_med_packet_num_out; - MED_DATAREADY_OUT <= buf_med_dataready_out; + sfp_los <= not sd_q; FSM_CTRL_OP <= CTRL_OP; ------------------------------------------------------------------------ ---Synchronizer ------------------------------------------------------------------------ - - CLK_TO_RX_SYNC : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => '0', - D_IN(0) => rx_allow, - CLK0 => CLK, - CLK1 => ff_rxfullclk, - D_OUT(0)=> rx_allow_qrx - ); - - - CLK_TO_TX_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 4 - ) - port map( - RESET => '0', - D_IN(0) => tx_allow, - D_IN(1) => lane_rst, - D_IN(2) => quad_rst, - D_IN(3) => CTRL_OP(15), - CLK0 => CLK, - CLK1 => ff_txfullclk, - D_OUT(0) => tx_allow_qtx, - D_OUT(1) => lane_rst_qtx, - D_OUT(2) => quad_rst_qtx, - D_OUT(3) => send_reset_words_ext - ); - - RX_TO_CLK_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 9 - ) - port map( - RESET => '0', - D_IN(7 downto 0) => link_error, - D_IN(8) => link_ok, - CLK0 => ff_rxfullclk, - CLK1 => CLK, - D_OUT(7 downto 0) => link_error_q, - D_OUT(8) => link_ok_q - ); - - TX_TO_CLK_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => '0', - D_IN(0) => tx_lane_reset, - CLK0 => CLK_25, - CLK1 => CLK, - D_OUT(0) => tx_lane_reset_q - ); - - SYNC_INPUT_TO_CLK : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => '0', - D_IN(0) => sd, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => sd_q - ); - - sfp_los <= not sd_q; ----------------------------------------------------------------------- ---LED Signals ------------------------------------------------------------------------ - THE_TX_RX_LED_PROC: process( CLK_25 ) - begin - if( rising_edge(CLK_25) ) then - led_counter <= led_counter + 1; - last_tx_k <= tx_k; - if ( buf_med_dataready_out = '1' ) then - rx_led <= '1'; - elsif( led_counter = 0 ) then - rx_led <= '0'; - end if; - if( tx_k = '0' and last_tx_k = '0') then - tx_led <= '1'; - elsif led_counter = 0 then - tx_led <= '0'; - end if; - end if; - end process; ------------------------------------------------------------------------ --Statistics ----------------------------------------------------------------------- @@ -414,55 +614,40 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); end if; end process; ------------------------------------------------------------------------ ---TX Reset ------------------------------------------------------------------------ +----------------------------------------------------------- +--Debugging +----------------------------------------------------------- - tx_lane_reset <= ffs_plol or quad_rst_qtx or not ffs_plol_low_stable ; + STAT_REG_OUT(31 downto 0) <= statreg_txcontrol_i; + STAT_REG_OUT(95 downto 32) <= statreg_rxcontrol_i; + STAT_REG_OUT(127 downto 96) <= (others => '0'); - process(CLK_25) - begin - if rising_edge(CLK_25) then - if ffs_plol = '0' then - ffs_plol_low_stable <= '0'; - ffs_plol_counter <= (others => '0'); - elsif ffs_plol_counter(18 downto 17) /= "11" then - ffs_plol_low_stable <= ffs_plol_counter(18); - ffs_plol_counter <= ffs_plol_counter + 1; - end if; - end if; - end process; ------------------------------------------------------------------------ ---Debugging ------------------------------------------------------------------------ - STAT_REG_OUT(11 downto 0) <= (others => '0'); --reserved for trigger information - STAT_REG_OUT(23 downto 12) <= (others => '0'); - STAT_REG_OUT(31 downto 24) <= (others => '0'); - - STAT_OP(7 downto 0) <= FSM_STAT_OP(7 downto 0); - STAT_OP(8) <= start_retransmit_i; - STAT_OP(9) <= FSM_STAT_OP(9); - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= request_retransmit_i when CTRL_OP(8) = '1' else (link_error(1) and not send_reset_words and tx_allow); - STAT_OP(13) <= make_trbnet_reset; - STAT_OP(14) <= FSM_STAT_OP(14); - STAT_OP(15) <= send_reset_words; - - STAT_DEBUG(15 downto 0) <= FSM_STAT_DEBUG(15 downto 0); - process(CLK) + STAT_OP(7 downto 0) <= FSM_STAT_OP(7 downto 0); + STAT_OP(8) <= start_retransmit_i; + STAT_OP(9) <= FSM_STAT_OP(9); + STAT_OP(10) <= rx_led; + STAT_OP(11) <= tx_led; + STAT_OP(12) <= request_retransmit_i when CTRL_OP(8) = '1' else link_error_q(1) and not send_reset_words_q and tx_allow; + STAT_OP(13) <= make_trbnet_reset_q; + STAT_OP(14) <= FSM_STAT_OP(14); + STAT_OP(15) <= send_reset_words_q; + + STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0); + STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); + STAT_DEBUG(40) <= rx_fifo_write_en; + STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; + STAT_DEBUG(49) <= tx_k; + STAT_DEBUG(62 downto 50) <= debug_txcontrol_i(12 downto 0); + STAT_DEBUG(63) <= tx_lane_reset; + + PROC_LED : process(ff_rxfullclk) begin - if rising_edge(CLK) then - STAT_DEBUG(16) <= request_retransmit_i; - STAT_DEBUG(17) <= start_retransmit_i; - STAT_DEBUG(25 downto 18) <= rx_data; - STAT_DEBUG(26) <= rx_k; - STAT_DEBUG(31 downto 27) <= (others => '0'); + if rising_edge(ff_rxfullclk) then + buf_rx_data_reg <= rx_data_reg; end if; end process; - STAT_DEBUG(47 downto 32) <= debug_txcontrol_i(15 downto 0); - STAT_DEBUG(63 downto 48) <= debug_rxcontrol_i(15 downto 0); + end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index 57115b6..744c2db 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -8,10 +8,10 @@ use work.trb_net_std.all; use work.trb_net_components.all; entity trb_net16_med_ecp_fot_4_ctc is -generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO -); -port( + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + ); + port( CLK : in std_logic; CLK_25 : in std_logic; CLK_EN : in std_logic; @@ -36,25 +36,20 @@ port( SD : in std_logic_vector(3 downto 0); -- Status and control port - STAT_OP : out std_logic_vector (63 downto 0); + STAT_OP : out std_logic_vector (63 downto 0); CTRL_OP : in std_logic_vector (63 downto 0); - STAT_REG_OUT : out std_logic_vector(127 downto 0); - STAT_DEBUG : out std_logic_vector (255 downto 0); + STAT_REG_OUT : out std_logic_vector (511 downto 0); + STAT_DEBUG : out std_logic_vector (255 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) ); end entity; architecture trb_net16_med_ecp_fot_4_ctc_arch of trb_net16_med_ecp_fot_4_ctc is -attribute HGROUP : string; -attribute HGROUP of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "GROUP_PCS"; -attribute syn_sharing : string; -attribute syn_sharing of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "false"; - component serdes_fot_full_quad_ctc is generic( USER_CONFIG_FILE : String := "serdes_fot_full_quad_ctc.txt" ); -PORT( +port( core_txrefclk : in std_logic; core_rxrefclk : in std_logic; hdinp0 : in std_logic; @@ -187,43 +182,91 @@ PORT( end component; -type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0); +component lattice_ecp2m_fifo_8x8_dualport +port( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(7 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + + +component lattice_ecp2m_fifo_16x8_dualport +port( + Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(15 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component; + +component trb_net16_rx_packets is +port( + -- Resets + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- data stream from SerDes + CLK_IN : in std_logic; -- SerDes RX clock + RX_ALLOW_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component trb_net16_rx_packets; +type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0); signal link_error : link_error_t; signal link_error_q : link_error_t; -signal reg_link_error : link_error_t; signal ffs_plol : std_logic; signal link_ok : std_logic_vector(3 downto 0); signal link_ok_q : std_logic_vector(3 downto 0); signal tx_data : std_logic_vector(8*4-1 downto 0); signal rx_data : std_logic_vector(8*4-1 downto 0); -signal ff_rxfullclk : std_logic_vector(3 downto 0); signal ff_txfullclk : std_logic; signal rx_k : std_logic_vector(3 downto 0); signal tx_k : std_logic_vector(3 downto 0); -signal last_tx_k : std_logic_vector(3 downto 0); signal lane_rst : std_logic_vector(3 downto 0); signal lane_rst_qtx : std_logic_vector(3 downto 0); signal quad_rst : std_logic_vector(3 downto 0); -signal quad_rst_qtx : std_logic_vector(3 downto 0); +signal reset_rx_control : std_logic_vector(3 downto 0); signal tx_allow : std_logic_vector(3 downto 0); -signal tx_allow_qtx : std_logic_vector(3 downto 0); - - signal rx_allow : std_logic_vector(3 downto 0); -signal rx_allow_qtx : std_logic_vector(3 downto 0); - signal sd_q : std_logic_vector(3 downto 0); +signal sfp_los : std_logic_vector(3 downto 0); signal buf_med_dataready_out : std_logic_vector(3 downto 0); -signal buf_med_read_out : std_logic_vector(3 downto 0); -signal buf_med_data_out : std_logic_vector(16*4-1 downto 0); -signal buf_med_packet_num_out : std_logic_vector(3*4-1 downto 0); -signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); -signal sfp_los : std_logic_vector(3 downto 0); +signal buf_med_data_out : std_logic_vector(63 downto 0); +signal buf_med_packet_num_out : std_logic_vector(11 downto 0); -signal led_counter : std_logic_vector(14 downto 0); + +signal led_counter : std_logic_vector(15 downto 0); signal rx_led : std_logic_vector(3 downto 0); signal tx_led : std_logic_vector(3 downto 0); @@ -231,32 +274,38 @@ signal FSM_STAT_OP : std_logic_vector(4*16-1 downto 0); signal FSM_STAT_DEBUG : std_logic_vector(4*32-1 downto 0); signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0); -signal packet_timeout_i : std_logic_vector(3 downto 0); signal send_reset_words : std_logic_vector(3 downto 0); signal make_trbnet_reset : std_logic_vector(3 downto 0); -signal debug_txcontrol_i : std_logic_vector(127 downto 0); + +signal packet_timeout : std_logic_vector(3 downto 0); +signal rx_bsm : std_logic_vector(15 downto 0); signal debug_rxcontrol_i : std_logic_vector(127 downto 0); signal request_retransmit_i : std_logic_vector(3 downto 0); -signal start_retransmit_i : std_logic_vector(3 downto 0); signal request_position_i : std_logic_vector(31 downto 0); +signal start_retransmit_i : std_logic_vector(3 downto 0); signal start_position_i : std_logic_vector(31 downto 0); -signal send_reset_words_ext : std_logic_vector(3 downto 0); -signal request_cnt_i : link_error_t; -signal reset_rx_control : std_logic_vector(3 downto 0); -signal enable_correction_i : std_logic_vector(3 downto 0); +signal debug_txcontrol_i : std_logic_vector(127 downto 0); -signal ffs_plol_low_stable : std_logic; -signal ffs_plol_counter : std_logic_vector(18 downto 0); -signal tx_lane_reset_q : std_logic_vector(3 downto 0); signal tx_lane_reset : std_logic; +signal ffs_plol_counter : std_logic_vector(18 downto 0); +signal ffs_plol_low_stable : std_logic; -attribute syn_keep : boolean; +signal statreg_rxcontrol_i : std_logic_vector(255 downto 0); +signal statreg_txcontrol_i : std_logic_vector(127 downto 0); + + +attribute HGROUP : string; +attribute syn_sharing : string; +attribute syn_keep : boolean; attribute syn_preserve : boolean; +attribute HGROUP of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "GROUP_PCS"; +attribute syn_sharing of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "false"; attribute syn_keep of led_counter : signal is true; attribute syn_preserve of led_counter : signal is true; + begin gen_normal_serdes : if REVERSE_ORDER = c_NO generate THE_SERDES: serdes_fot_full_quad_ctc @@ -280,8 +329,8 @@ gen_normal_serdes : if REVERSE_ORDER = c_NO generate ff_disp_err_ch0 => link_error(0)(0), ff_cv_ch0 => link_error(0)(1), ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst(0),--tx_lane_reset, -- - ffc_lane_rx_rst_ch0 => lane_rst(0), + ffc_lane_tx_rst_ch0 => tx_lane_reset, --lane_rst(0), + ffc_lane_rx_rst_ch0 => lane_rst_qtx(0), ffc_txpwdnb_ch0 => '1', ffc_rxpwdnb_ch0 => '1', ffs_rlos_lo_ch0 => link_error(0)(2), @@ -309,8 +358,8 @@ gen_normal_serdes : if REVERSE_ORDER = c_NO generate ff_disp_err_ch1 => link_error(1)(0), ff_cv_ch1 => link_error(1)(1), ffc_rrst_ch1 => '0', - ffc_lane_tx_rst_ch1 => lane_rst(1), - ffc_lane_rx_rst_ch1 => lane_rst(1), + ffc_lane_tx_rst_ch1 => tx_lane_reset, --lane_rst(1), + ffc_lane_rx_rst_ch1 => lane_rst_qtx(1), ffc_txpwdnb_ch1 => '1', ffc_rxpwdnb_ch1 => '1', ffs_rlos_lo_ch1 => link_error(1)(2), @@ -338,8 +387,8 @@ gen_normal_serdes : if REVERSE_ORDER = c_NO generate ff_disp_err_ch2 => link_error(2)(0), ff_cv_ch2 => link_error(2)(1), ffc_rrst_ch2 => '0', - ffc_lane_tx_rst_ch2 => lane_rst(2), - ffc_lane_rx_rst_ch2 => lane_rst(2), + ffc_lane_tx_rst_ch2 => tx_lane_reset, --lane_rst(2), + ffc_lane_rx_rst_ch2 => lane_rst_qtx(2), ffc_txpwdnb_ch2 => '1', ffc_rxpwdnb_ch2 => '1', ffs_rlos_lo_ch2 => link_error(2)(2), @@ -367,8 +416,8 @@ gen_normal_serdes : if REVERSE_ORDER = c_NO generate ff_disp_err_ch3 => link_error(3)(0), ff_cv_ch3 => link_error(3)(1), ffc_rrst_ch3 => '0', - ffc_lane_tx_rst_ch3 => lane_rst(3), - ffc_lane_rx_rst_ch3 => lane_rst(3), + ffc_lane_tx_rst_ch3 => tx_lane_reset, --lane_rst(3), + ffc_lane_rx_rst_ch3 => lane_rst_qtx(3), ffc_txpwdnb_ch3 => '1', ffc_rxpwdnb_ch3 => '1', ffs_rlos_lo_ch3 => link_error(3)(2), @@ -410,8 +459,8 @@ THE_SERDES: serdes_fot_full_quad_ctc ff_disp_err_ch0 => link_error(3)(0), ff_cv_ch0 => link_error(3)(1), ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst(3), - ffc_lane_rx_rst_ch0 => lane_rst(3), + ffc_lane_tx_rst_ch0 => tx_lane_reset, --lane_rst(3), + ffc_lane_rx_rst_ch0 => lane_rst_qtx(3), ffc_txpwdnb_ch0 => '1', ffc_rxpwdnb_ch0 => '1', ffs_rlos_lo_ch0 => link_error(3)(2), @@ -439,8 +488,8 @@ THE_SERDES: serdes_fot_full_quad_ctc ff_disp_err_ch1 => link_error(2)(0), ff_cv_ch1 => link_error(2)(1), ffc_rrst_ch1 => '0', - ffc_lane_tx_rst_ch1 => lane_rst(2), - ffc_lane_rx_rst_ch1 => lane_rst(2), + ffc_lane_tx_rst_ch1 => tx_lane_reset, --lane_rst(2), + ffc_lane_rx_rst_ch1 => lane_rst_qtx(2), ffc_txpwdnb_ch1 => '1', ffc_rxpwdnb_ch1 => '1', ffs_rlos_lo_ch1 => link_error(2)(2), @@ -468,8 +517,8 @@ THE_SERDES: serdes_fot_full_quad_ctc ff_disp_err_ch2 => link_error(1)(0), ff_cv_ch2 => link_error(1)(1), ffc_rrst_ch2 => '0', - ffc_lane_tx_rst_ch2 => lane_rst(1), - ffc_lane_rx_rst_ch2 => lane_rst(1), + ffc_lane_tx_rst_ch2 => tx_lane_reset, --lane_rst(1), + ffc_lane_rx_rst_ch2 => lane_rst_qtx(1), ffc_txpwdnb_ch2 => '1', ffc_rxpwdnb_ch2 => '1', ffs_rlos_lo_ch2 => link_error(1)(2), @@ -497,8 +546,8 @@ THE_SERDES: serdes_fot_full_quad_ctc ff_disp_err_ch3 => link_error(0)(0), ff_cv_ch3 => link_error(0)(1), ffc_rrst_ch3 => '0', - ffc_lane_tx_rst_ch3 => lane_rst(0), - ffc_lane_rx_rst_ch3 => lane_rst(0), + ffc_lane_tx_rst_ch3 => tx_lane_reset, -- lane_rst(0), + ffc_lane_rx_rst_ch3 => lane_rst_qtx(0), ffc_txpwdnb_ch3 => '1', ffc_rxpwdnb_ch3 => '1', ffs_rlos_lo_ch3 => link_error(0)(2), @@ -520,37 +569,16 @@ end generate; ------------------------------------------------------------------------ ---TX Reset ------------------------------------------------------------------------ - - tx_lane_reset <= ffs_plol or quad_rst_qtx(0) or not ffs_plol_low_stable ; - - process(CLK_25) - begin - ffs_plol_low_stable <= '0'; - if rising_edge(CLK_25) then - if ffs_plol = '0' then - ffs_plol_low_stable <= '0'; - ffs_plol_counter <= (others => '0'); - elsif ffs_plol_counter(18 downto 17) /= "11" then - ffs_plol_low_stable <= ffs_plol_counter(18); - ffs_plol_counter <= ffs_plol_counter + 1; - end if; - end if; - end process; - -gen_logic : for i in 0 to 3 generate - ----------------------------------------------------------------------- --TX Control ----------------------------------------------------------------------- +gen_tx: for i in 0 to 3 generate THE_TX_CONTROL : trb_net16_tx_control port map( - TXCLK_IN => CLK_25, + TXCLK_IN => ff_txfullclk, RXCLK_IN => CLK_25, SYSCLK_IN => CLK, - RESET_IN => lane_rst(i), + RESET_IN => tx_lane_reset, TX_DATA_IN => MED_DATA_IN(i*16+15 downto i*16), TX_WRITE_IN => MED_DATAREADY_IN(i), @@ -563,20 +591,51 @@ gen_logic : for i in 0 to 3 generate REQUEST_POSITION_IN => request_position_i(i*8+7 downto i*8), START_RETRANSMIT_IN => start_retransmit_i(i), START_POSITION_IN => start_position_i(i*8+7 downto i*8), - SEND_LINK_RESET_IN => send_reset_words_ext(i), + SEND_LINK_RESET_IN => CTRL_OP(i*16+15), TX_ALLOW_IN => tx_allow(i), - DEBUG_OUT => debug_txcontrol_i(i*32+31 downto i*32) - ); + DEBUG_OUT => debug_txcontrol_i(i*32+31 downto i*32), + STAT_REG_OUT => statreg_txcontrol_i(i*32+31 downto i*32) + ); +end generate; ----------------------------------------------------------------------- --RX Control ----------------------------------------------------------------------- +gen_rx: for i in 0 to 3 generate +-- THE_RX_CONTROL : trb_net16_rx_packets +-- port map( +-- -- Resets +-- RESET_IN => reset, +-- QUAD_RST_IN => quad_rst(0), +-- -- data stream from SerDes +-- CLK_IN => CLK_25, +-- RX_ALLOW_IN => rx_allow(i), +-- RX_DATA_IN => rx_data(8*i+7 downto 8*i), +-- RX_K_IN => rx_k(i), +-- -- media interface +-- SYSCLK_IN => CLK, +-- MED_DATA_OUT => MED_DATA_OUT(i*16+15 downto i*16), +-- MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT(i), +-- MED_READ_IN => MED_READ_IN(i), +-- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(i*3+2 downto i*3), +-- -- reset handling +-- SEND_RESET_WORDS_OUT => send_reset_words(i), +-- MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i), +-- -- Status signals +-- PACKET_TIMEOUT_OUT => packet_timeout(i), +-- -- Debug signals +-- BSM_OUT => rx_bsm(i*4+3 downto i*4), +-- DBG_OUT => debug_rxcontrol_i(i*16+15 downto i*16) +-- ); +-- +-- MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i); + THE_RX_CONTROL : trb_net16_rx_control port map( RESET_IN => reset_rx_control(i), - QUAD_RST_IN => quad_rst(0), + QUAD_RST_IN => lane_rst(i), -- raw data from SerDes receive path CLK_IN => CLK_25, RX_DATA_IN => rx_data(i*8+7 downto i*8), @@ -600,91 +659,52 @@ gen_logic : for i in 0 to 3 generate SEND_RESET_WORDS_OUT => send_reset_words(i), MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i), -- Status signals - PACKET_TIMEOUT_OUT => packet_timeout_i(i), - ENABLE_CORRECTION_IN => enable_correction_i(i), + PACKET_TIMEOUT_OUT => packet_timeout(i), -- Debugging + ENABLE_CORRECTION_IN => CTRL_OP(i*16+8), + STAT_REG_OUT => statreg_rxcontrol_i(i*64+63 downto i*64), DEBUG_OUT => debug_rxcontrol_i(i*32+31 downto i*32) ); -reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_q(i)(7); +reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_q(i)(7); ------------------------------------------------------------------------ ---Link State Machine ------------------------------------------------------------------------ - - THE_SFP_LSM: trb_net16_lsm_sfp - generic map( - CHECK_FOR_CV => c_NO - ) - port map( - SYSCLK => CLK, - RESET => reset, - CLEAR => clear, - SFP_MISSING_IN => '0', - SFP_LOS_IN => sfp_los(i), - SD_LINK_OK_IN => link_ok_q(i), - SD_LOS_IN => link_error_q(i)(2), - SD_TXCLK_BAD_IN => ffs_plol, -- - SD_RXCLK_BAD_IN => link_error_q(i)(7), - SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN => "10", - SD_CV_IN(0) => link_error_q(i)(1), - SD_CV_IN(1) => '0', - FULL_RESET_OUT => quad_rst(i), - LANE_RESET_OUT => lane_rst(i), - TX_ALLOW_OUT => tx_allow(i), - RX_ALLOW_OUT => rx_allow(i), - SWAP_BYTES_OUT => open, - STAT_OP => FSM_STAT_OP(i*16+15 downto i*16), - CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16), - STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32) - ); +MED_DATA_OUT(i*16+15 downto i*16) <= buf_med_data_out(i*16+15 downto i*16); +MED_DATAREADY_OUT(i) <= buf_med_dataready_out(i); +MED_PACKET_NUM_OUT(i*3+2 downto i*3) <= buf_med_packet_num_out(i*3+2 downto i*3); +end generate; ----------------------------------------------------------------------- ---Synchronizer +--Synchronization ----------------------------------------------------------------------- - - +gen_sync: for i in 0 to 3 generate CLK_TO_TX_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 6 + WIDTH => 1 ) port map( RESET => '0', - D_IN(0) => tx_allow(i), - D_IN(1) => lane_rst(i), - D_IN(2) => quad_rst(i), - D_IN(3) => CTRL_OP(i*16+15), - D_IN(4) => rx_allow(i), - D_IN(5) => CTRL_OP(i*16+8), + D_IN(0) => lane_rst(i), CLK0 => CLK, CLK1 => CLK_25, - D_OUT(0) => tx_allow_qtx(i), - D_OUT(1) => lane_rst_qtx(i), - D_OUT(2) => quad_rst_qtx(i), - D_OUT(3) => send_reset_words_ext(i), - D_OUT(4) => rx_allow_qtx(i), - D_OUT(5) => enable_correction_i(i) + D_OUT(0) => lane_rst_qtx(i) ); - RX_TO_CLK_SYNC: signal_sync + LINK_ERROR_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 10 + WIDTH => 9 ) port map( - RESET => '0', + RESET => reset, D_IN(7 downto 0) => link_error(i), - D_IN(8) => link_ok(i), - D_IN(9) => tx_lane_reset, - CLK0 => CLK_25, - CLK1 => CLK, + D_IN(8) => link_ok(i), + CLK0 => CLK_25, + CLK1 => CLK, D_OUT(7 downto 0) => link_error_q(i), - D_OUT(8) => link_ok_q(i), - D_OUT(9) => tx_lane_reset_q(i) + D_OUT(8) => link_ok_q(i) ); SYNC_INPUT_TO_CLK : signal_sync @@ -693,117 +713,370 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ WIDTH => 1 ) port map( - RESET => '0', + RESET => reset, D_IN(0) => sd(i), CLK0 => CLK, CLK1 => CLK, D_OUT(0) => sd_q(i) ); - sfp_los(i) <= not sd_q(i); - - +end generate; ----------------------------------------------------------------------- ---STAT & Debug +--LED Signals ----------------------------------------------------------------------- - - - STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0); - --STAT_OP(i*16+8) <= start_retransmit_i(i);--signal is registered! - STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); - STAT_OP(i*16+10) <= rx_led(i); - STAT_OP(i*16+11) <= tx_led(i); - --STAT_OP(i*16+12) <= --signal is registered! - STAT_OP(i*16+13) <= make_trbnet_reset(i); - STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); - STAT_OP(i*16+15) <= send_reset_words(i); - - STAT_DEBUG(i*64+15 downto i*64+0) <= FSM_STAT_DEBUG(i*32+15 downto i*32); - process(CLK) - begin - if rising_edge(CLK) then - STAT_OP(i*16+8) <= start_retransmit_i(i); - if CTRL_OP(i*16+8) = '1' then - STAT_OP(i*16+12) <= request_retransmit_i(i); - else - STAT_OP(i*16+12) <= (link_error(i)(1) and not send_reset_words(i) and tx_allow(i)); + gen_led: for i in 0 to 3 generate + THE_TX_RX_LED_PROC: process( clk ) + begin + if( rising_edge(CLK) ) then + if ( buf_MED_DATAREADY_OUT(i) = '1' ) then + rx_led(i) <= '1'; + elsif( led_counter = 0 ) then + rx_led(i) <= '0'; + end if; + if ( MED_DATAREADY_IN(i) = '1') then + tx_led(i) <= '1'; + elsif( led_counter = 0 ) then + tx_led(i) <= '0'; + end if; end if; + end process; + end generate; - STAT_DEBUG(i*64+16) <= request_retransmit_i(i); - STAT_DEBUG(i*64+17) <= start_retransmit_i(i); - STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); - STAT_DEBUG(i*64+26) <= rx_k(i); - STAT_DEBUG(i*64+31 downto i*64+27) <= (others => '0'); + proc_led_counter: process(CLK) + begin + if( rising_edge(CLK) ) then + led_counter <= led_counter + 1; end if; end process; - STAT_DEBUG(i*64+47 downto i*64+32) <= debug_txcontrol_i(i*32+15 downto i*32); - STAT_DEBUG(i*64+63 downto i*64+48) <= debug_rxcontrol_i(i*32+15 downto i*32); ------------------------------------------------------------------------ ---Statistics ------------------------------------------------------------------------ - process(clk) - begin - if rising_edge(clk) then - if request_retransmit_i(i) = '1' and CTRL_OP(i*16+15) = '0' then - request_cnt_i(i) <= request_cnt_i(i) + 1; - end if; - end if; - end process; - STAT_REG_OUT(i*32+11 downto i*32+0) <= (others => '0'); --reserved for trigger information - STAT_REG_OUT(i*32+23 downto i*32+12) <= (others => '0'); - STAT_REG_OUT(i*32+31 downto i*32+24) <= request_cnt_i(i); ----------------------------------------------------------------------- ---LED Signals +--TX Reset ----------------------------------------------------------------------- - THE_TX_LED_PROC: process( clk_25 ) - begin - if( rising_edge(CLK_25) ) then - last_tx_k(i) <= tx_k(i); - if( tx_k(i) = '0' and last_tx_k(i) = '0') then - tx_led(i) <= '1'; - elsif led_counter = 0 then - tx_led(i) <= '0'; - end if; - end if; - end process; - THE_RX_LED_PROC: process( clk_25 ) + tx_lane_reset <= not ffs_plol_low_stable or RESET; + + proc_plol_stable : process(CLEAR, CLK_25) begin - if( rising_edge(CLK_25) ) then - if ( buf_med_dataready_out(i) = '1' ) then - rx_led(i) <= '1'; - elsif( led_counter = 0 ) then - rx_led(i) <= '0'; + if CLEAR = '1' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif rising_edge(CLK_25) then + if ffs_plol = '1' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif ffs_plol_counter(18) = '1' then + ffs_plol_low_stable <= '1'; + ffs_plol_counter <= ffs_plol_counter; + else + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= ffs_plol_counter + 1; end if; end if; end process; -end generate; - - - PROC_LED_COUNTER: process(CLK_25) - begin - if( rising_edge(CLK_25) ) then - led_counter <= led_counter + 1; - end if; - end process PROC_LED_COUNTER; ----------------------------------------------------------------------- ---I/O +--Link State Machine ----------------------------------------------------------------------- - - MED_DATA_OUT <= buf_med_data_out; - MED_PACKET_NUM_OUT <= buf_med_packet_num_out; - MED_DATAREADY_OUT <= buf_med_dataready_out; - + gen_lsm : for i in 0 to 3 generate + THE_SFP_LSM: trb_net16_lsm_sfp + generic map( + CHECK_FOR_CV => c_NO + ) + port map( + SYSCLK => CLK, + RESET => reset, + CLEAR => reset, + SFP_MISSING_IN => '0', + SFP_LOS_IN => sfp_los(i), + SD_LINK_OK_IN => link_ok_q(i), + SD_LOS_IN => link_error_q(i)(2), + SD_TXCLK_BAD_IN => tx_lane_reset, --ffs_plol, + SD_RXCLK_BAD_IN => link_error_q(i)(7), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => "10", + SD_CV_IN(0) => link_error_q(i)(1), + SD_CV_IN(1) => '0', + FULL_RESET_OUT => quad_rst(i), + LANE_RESET_OUT => lane_rst(i), + TX_ALLOW_OUT => tx_allow(i), + RX_ALLOW_OUT => rx_allow(i), + SWAP_BYTES_OUT => open, + STAT_OP => FSM_STAT_OP(i*16+15 downto i*16), + CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16), + STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32) + ); + end generate; + + SFP_LOS <= not sd_q; FSM_CTRL_OP <= CTRL_OP; -end architecture; \ No newline at end of file + +----------------------------------------------------------------------- +--Status & Debug +----------------------------------------------------------------------- + gen_stat : for i in 0 to 3 generate + STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0); + STAT_OP(i*16+8) <= start_retransmit_i(i); + STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); + STAT_OP(i*16+10) <= rx_led(i); + STAT_OP(i*16+11) <= tx_led(i); + + + process(CLK) + begin + if rising_edge(CLK) then + if CTRL_OP(i*16+8) = '1' then + STAT_OP(i*16+12) <= request_retransmit_i(i); + else + STAT_OP(i*16+12) <= (link_error_q(i)(1) or packet_timeout(i)) and not send_reset_words(i) and tx_allow(i); + end if; + end if; + end process; + STAT_OP(i*16+13) <= make_trbnet_reset(i); + STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); + STAT_OP(i*16+15) <= send_reset_words(i); + + STAT_DEBUG(i*64+17 downto i*64+0) <= FSM_STAT_DEBUG(i*32+17 downto i*32); + STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); + STAT_DEBUG(i*64+26) <= rx_k(i); + STAT_DEBUG(i*64+48 downto i*64+27) <= debug_txcontrol_i(i*32+21 downto i*32); + STAT_DEBUG(i*64+63 downto i*64+49) <= debug_rxcontrol_i(i*16+14 downto i*16+0); + + STAT_REG_OUT(128*i+31 downto 128*i+0) <= statreg_txcontrol_i(32*i+31 downto 32*i); + STAT_REG_OUT(128*i+95 downto 128*i+32) <= statreg_rxcontrol_i(64*i+63 downto 64*i); + STAT_REG_OUT(128*i+127 downto 128*i+96) <= (others => '0'); + + end generate; + + + + +end architecture; + + +-- THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport +-- generic map( +-- USE_STATUS_FLAGS => c_NO +-- ) +-- port map( +-- read_clock_in => clk, +-- write_clock_in => CLK_25, +-- read_enable_in => rx_fifo_read_en(i), +-- write_enable_in => rx_fifo_write_en(i), +-- fifo_gsr_in => fifo_reset(i), +-- write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8), +-- read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8), +-- full_out => rx_fifo_full(i), +-- empty_out => rx_fifo_empty(i) +-- ); +-- +-- THE_WRITE_RX_FIFO_PROC: process( CLK_25 ) +-- begin +-- if( rising_edge(CLK_25) ) then +-- buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8); +-- buf_rx_k(i) <= rx_k(i); +-- if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then +-- rx_fifo_write_en(i) <= '0'; +-- is_idle_word(i) <= '1'; +-- rx_starting(i) <= '1'; +-- else +-- rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8); +-- if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then +-- rx_fifo_write_en(i) <= '1'; +-- else +-- rx_fifo_write_en(i) <= '0'; +-- end if; +-- if ( buf_rx_k(i) = '1' ) then +-- is_idle_word(i) <= '1'; +-- rx_starting(i) <= '0'; +-- elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then +-- is_idle_word(i) <= '0'; +-- end if; +-- end if; +-- end if; +-- end process THE_WRITE_RX_FIFO_PROC; +-- +-- THE_CNT_RESET_PROC : process( CLK_25 ) +-- begin +-- if( rising_edge(CLK_25) ) then +-- if( reset = '1' ) then +-- send_reset_words(i) <= '0'; +-- make_trbnet_reset(i) <= '0'; +-- reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); +-- else +-- send_reset_words(i) <= '0'; +-- make_trbnet_reset(i) <= '0'; +-- if( (buf_rx_data(i*8+7 downto i*8) = x"FE") and (buf_rx_k(i) = '1') ) then +-- if( reset_word_cnt(i*5+4) = '0' ) then +-- reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1; +-- else +-- send_reset_words(i) <= '1'; +-- end if; +-- else +-- reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); +-- make_trbnet_reset(i) <= reset_word_cnt(i*5+4); +-- end if; +-- end if; +-- end if; +-- end process; +-- -- RX Control (100) +-- -- ------------------- +-- THE_RX_CTRL_PROC: process( clk ) +-- begin +-- if( rising_edge(clk) ) then +-- if( reset = '1' ) then +-- buf_med_dataready_out(i) <= '0'; +-- byte_select(i) <= '0'; +-- last_rx_fifo_read_en(i) <= '0'; +-- else +-- last_rx_fifo_read_en(i) <= rx_fifo_read_en(i); +-- last_rx_fifo_empty(i) <= rx_fifo_empty(i); +-- last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i); +-- last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i); +-- last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8); +-- buf_med_dataready_out(i) <= '0'; +-- if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then +-- if( byte_select(i) = '1' ) then +-- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8) +-- & buf_MED_DATA_OUT(i*16+7 downto i*16); +-- buf_MED_DATAREADY_OUT(i) <= '1'; +-- else +-- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8); +-- end if; +-- byte_select(i) <= not byte_select(i); +-- end if; +-- end if; +-- end if; +-- end process THE_RX_CTRL_PROC; +-- +-- rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i); +-- MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16); +-- MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i); +-- MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH); +-- +-- --rx packet counter +-- --------------------- +-- THE_RX_PACKETS_PROC: process( clk ) +-- begin +-- if( rising_edge(clk) ) then +-- if( (reset = '1') or (rx_allow(i) = '0') ) then +-- rx_counter(i*3+2 downto i*3) <= c_H0; +-- else +-- if( buf_med_dataready_out(i) = '1' ) then +-- if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then +-- rx_counter(i*3+2 downto i*3) <= (others => '0'); +-- else +-- rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process THE_RX_PACKETS_PROC; + + + + + +-- +-- THE_TX_FIFO: trb_net_fifo_16bit_bram_dualport +-- generic map( +-- USE_STATUS_FLAGS => c_NO +-- ) +-- port map( +-- read_clock_in => CLK_25,--ff_txfullclk, +-- write_clock_in => CLK, +-- read_enable_in => tx_fifo_read_en(i), +-- write_enable_in => tx_fifo_write_en(i), +-- fifo_gsr_in => fifo_reset(i), +-- write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16), +-- read_data_out(15 downto 0) => tx_fifo_dout((i+1)*16-1 downto i*16), +-- full_out => tx_fifo_full(i), +-- empty_out => tx_fifo_empty(i) +-- ); +-- +-- +-- THE_READ_TX_FIFO_PROC: process( CLK_25 ) +-- begin +-- if( rising_edge(CLK_25) ) then +-- if( reset = '1' ) then +-- byte_waiting(i) <= '0'; +-- tx_fifo_read_en(i) <= '0'; +-- tx_k(i) <= '1'; +-- tx_data((i+1)*8-1 downto i*8) <= x"FE"; +-- tx_fifo_valid_read(i) <= '0'; +-- else +-- tx_fifo_read_en(i) <= tx_allow_qtx(i); +-- tx_fifo_valid_read(i) <= tx_fifo_read_en(i) and not tx_fifo_empty(i); +-- if( byte_waiting(i) = '0' ) then +-- if ( tx_fifo_valid_read(i) = '1' ) then +-- byte_buffer((i+1)*8-1 downto i*8) <= tx_fifo_dout((i)*16+15 downto i*16+8); +-- byte_waiting(i) <= '1'; +-- tx_k(i) <= '0'; +-- tx_data((i+1)*8-1 downto i*8) <= tx_fifo_dout(i*16+7 downto i*16+0); +-- tx_fifo_read_en(i) <= tx_allow_qtx(i); +-- elsif( send_reset_q(i) = '1' ) then +-- byte_buffer((i+1)*8-1 downto i*8) <= x"FE"; +-- byte_waiting(i) <= '1'; +-- tx_k(i) <= '1'; +-- tx_data((i+1)*8-1 downto i*8) <= x"FE"; +-- tx_fifo_read_en(i) <= '0'; +-- else +-- byte_buffer((i+1)*8-1 downto i*8) <= x"50"; +-- byte_waiting(i) <= '1'; +-- tx_k(i) <= '1'; +-- tx_data((i+1)*8-1 downto i*8) <= x"BC"; +-- tx_fifo_read_en(i) <= tx_allow_qtx(i); +-- end if; +-- else +-- tx_data((i+1)*8-1 downto i*8) <= byte_buffer((i+1)*8-1 downto i*8); +-- tx_k(i) <= send_reset_q(i); --second byte is always data +-- byte_waiting(i) <= '0'; +-- tx_fifo_read_en(i) <= '0'; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- fifo_reset(i) <= reset or quad_rst(0) or not rx_allow(i); --(sync with SYSCLK) + +--TX Control (100) +-- --------------------- +-- buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow_del(i); +-- tx_fifo_write_en(i) <= buf_med_read_out(i) and med_dataready_in(i); +-- tx_fifo_data_in(i*16+15 downto i*16) <= med_data_in(i*16+15 downto i*16); +-- med_read_out(i) <= buf_med_read_out(i); + + + +-- TX_TO_CLK_SYNC: signal_sync +-- generic map( +-- DEPTH => 2, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => reset, +-- D_IN(0) => tx_fifo_valid_read(i), +-- CLK0 => CLK_25, +-- CLK1 => CLK, +-- D_OUT(0) => tx_fifo_valid_read_q(i) +-- ); +-- THE_SFP_STATUS_SYNC: signal_sync +-- generic map( +-- DEPTH => 2, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => RESET, +-- D_IN(0) => rx_allow(i), +-- CLK0 => CLK, +-- CLK1 => CLK_25, +-- D_OUT(0) => rx_allow_qrx(i) +-- ); \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_checker.vhd b/media_interfaces/trb_net16_rx_checker.vhd index 44f2f3c..034411f 100644 --- a/media_interfaces/trb_net16_rx_checker.vhd +++ b/media_interfaces/trb_net16_rx_checker.vhd @@ -21,7 +21,7 @@ port( RESUME_OUT : out std_logic; -- full packet RX resume signal REQ_RETRANS_OUT : out std_logic; -- request retransmission -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); + STAT_REG_OUT : out std_logic_vector(15 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) ); end entity trb_net16_rx_checker; @@ -147,7 +147,12 @@ FIFO_RST_OUT <= fifo_rst; RESUME_OUT <= resume; REQ_RETRANS_OUT <= request; -BSM_OUT <= bsm; +STAT_REG_OUT(3 downto 0) <= bsm; +STAT_REG_OUT(4) <= fifo_rst; +STAT_REG_OUT(5) <= request; +STAT_REG_OUT(6) <= resume; +STAT_REG_OUT(15 downto 7) <= (others => '0'); + DBG_OUT <= debug; end behavioral; \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 58f7108..7e96392 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -22,9 +22,9 @@ port( FIFO_WR_OUT : out std_logic; FIFO_INHIBIT_OUT : out std_logic; -- Special comma actions - LD_RX_POSITION_OUT : out std_logic; + LD_RX_POSITION_OUT : out std_logic; --change position in rx fifo RX_POSITION_OUT : out std_logic_vector(7 downto 0); - LD_START_POSITION_OUT : out std_logic; + LD_START_POSITION_OUT : out std_logic; --restart sending from given position START_POSITION_OUT : out std_logic_vector(7 downto 0); -- Check COMMA_LOCKED_OUT : out std_logic; @@ -33,6 +33,7 @@ port( MAKE_TRBNET_RESET_OUT : out std_logic; ENABLE_CORRECTION_IN : in std_logic; -- Debugging + STAT_REG_OUT : out std_logic_vector(15 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity trb_net16_rx_comma_handler; @@ -251,6 +252,12 @@ debug(12) <= c_reset; debug(11) <= reset_word_cnt(4); debug(10 downto 0) <= (others => '0'); +STAT_REG_OUT(4 downto 0) <= reset_word_cnt; +STAT_REG_OUT(5) <= fifo_inhibit; +STAT_REG_OUT(6) <= comma_locked; +STAT_REG_OUT(7) <= '0'; +STAT_REG_OUT(15 downto 8)<= (others => '0'); + ---------------------------------------------------------------------- -- Output signals ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index e704217..6f6f042 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -37,7 +37,8 @@ port( COMMA_LOCKED_OUT : out std_logic; -- Debugging ENABLE_CORRECTION_IN : in std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(63 downto 0) ); end entity; @@ -73,6 +74,7 @@ port( MAKE_TRBNET_RESET_OUT : out std_logic; ENABLE_CORRECTION_IN : in std_logic; -- Debugging + STAT_REG_OUT : out std_logic_vector(15 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component trb_net16_rx_comma_handler; @@ -101,7 +103,7 @@ port( PACKET_TIMEOUT_OUT : out std_logic; ENABLE_CORRECTION_IN : in std_logic; -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); + STAT_REG_OUT : out std_logic_vector(15 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) ); end component trb_net16_rx_full_packets; @@ -121,7 +123,7 @@ port( RESUME_OUT : out std_logic; -- full packet RX resume signal REQ_RETRANS_OUT : out std_logic; -- request retransmission -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); + STAT_REG_OUT : out std_logic_vector(15 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) ); end component trb_net16_rx_checker; @@ -206,6 +208,12 @@ signal comma_locked : std_logic; signal debug : std_logic_vector(31 downto 0); +signal statreg_rxfullpackets : std_logic_vector(15 downto 0); +signal statreg_rxcommahandler : std_logic_vector(15 downto 0); +signal statreg_rxchecker : std_logic_vector(15 downto 0); + + + begin ---------------------------------------------------------------------- @@ -238,6 +246,7 @@ port map( MAKE_TRBNET_RESET_OUT => make_trbnet_reset, ENABLE_CORRECTION_IN => enable_correction_qrx, -- Debugging + STAT_REG_OUT => statreg_rxcommahandler, DEBUG_OUT => debug_rch ); @@ -350,7 +359,7 @@ port map( PACKET_TIMEOUT_OUT => packet_timeout, ENABLE_CORRECTION_IN => ENABLE_CORRECTION_IN, -- Debug signals - BSM_OUT => open, + STAT_REG_OUT => statreg_rxfullpackets, DBG_OUT => debug_rfp ); @@ -381,7 +390,7 @@ port map( RESUME_OUT => rx_resume, REQ_RETRANS_OUT => request_retransmit, -- Debug signals - BSM_OUT => open, + STAT_REG_OUT => statreg_rxchecker, DBG_OUT => debug_rxc ); @@ -400,6 +409,17 @@ debug(5) <= debug_rch(12); debug(15 downto 4) <= debug_rch(15 downto 4); +STAT_REG_OUT(15 downto 0) <= statreg_rxfullpackets; +STAT_REG_OUT(23 downto 16) <= statreg_rxcommahandler(7 downto 0); +STAT_REG_OUT(31 downto 24) <= rx_position; --load RX buffer position +STAT_REG_OUT(39 downto 32) <= statreg_rxchecker(7 downto 0); +STAT_REG_OUT(47 downto 40) <= start_position; --restart sending from this position +STAT_REG_OUT(48) <= packet_timeout; +STAT_REG_OUT(49) <= rx_gone_wrong; +STAT_REG_OUT(50) <= pkt_in_transit; +STAT_REG_OUT(55 downto 51) <= (others => '0'); +STAT_REG_OUT(63 downto 56) <= request_position; --make request for resending + ---------------------------------------------------------------------- -- Output signals ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_rx_full_packets.vhd b/media_interfaces/trb_net16_rx_full_packets.vhd index 3b3ba4b..81d494e 100644 --- a/media_interfaces/trb_net16_rx_full_packets.vhd +++ b/media_interfaces/trb_net16_rx_full_packets.vhd @@ -30,7 +30,7 @@ port( PACKET_TIMEOUT_OUT : out std_logic; ENABLE_CORRECTION_IN : in std_logic; -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); + STAT_REG_OUT : out std_logic_vector(15 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) ); end entity trb_net16_rx_full_packets; @@ -374,7 +374,7 @@ begin end if; end process THE_TOC_PROC; -toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" and ENABLE_CORRECTION_IN = '1') else '0'; +toc_done_x <= '1' when ( timeout_ctr(6 downto 2) = b"111_11" and ENABLE_CORRECTION_IN = '1') else '0'; ---------------------------------------------------------------------- -- Debug signals @@ -385,6 +385,15 @@ debug(10) <= ce_toc; debug(9) <= rst_toc; debug(8 downto 0) <= (others => '0'); +STAT_REG_OUT(3 downto 0) <= bsm; +STAT_REG_OUT(4) <= toc_done; +STAT_REG_OUT(5) <= transit; +STAT_REG_OUT(6) <= pkt_timeout; +STAT_REG_OUT(7) <= ce_toc; +STAT_REG_OUT(10 downto 8) <= std_logic_vector(rx_counter); +STAT_REG_OUT(15 downto 11)<= (others => '0'); + + ---------------------------------------------------------------------- -- Output signals ---------------------------------------------------------------------- @@ -398,7 +407,6 @@ PKT_IN_TRANSIT_OUT <= transit; MED_DATAREADY_OUT <= med_dataready; MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter); -BSM_OUT <= bsm; DBG_OUT <= debug; end behavioral; \ No newline at end of file diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index c95e0b3..53d904e 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -29,7 +29,8 @@ port( SEND_LINK_RESET_IN : in std_logic; TX_ALLOW_IN : in std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -84,12 +85,14 @@ architecture arch of trb_net16_tx_control is signal buf_tx_read_out : std_logic; signal tx_data_25_i : std_logic_vector(15 downto 0); signal tx_allow_qtx : std_logic; + signal tx_allow_q : std_logic; signal send_link_reset_qtx : std_logic; signal ct_fifo_empty : std_logic; signal ct_fifo_write : std_logic; signal ct_fifo_read : std_logic; signal ct_fifo_full : std_logic; signal ct_fifo_afull : std_logic; + signal ct_fifo_reset : std_logic; begin @@ -103,8 +106,8 @@ begin RdClock => TXCLK_IN, WrEn => ct_fifo_write, RdEn => ct_fifo_read, - Reset => RESET_IN, - RPReset => RESET_IN, + Reset => ct_fifo_reset, + RPReset => ct_fifo_reset, Q => tx_data_25_i, Empty => ct_fifo_empty, Full => ct_fifo_full, @@ -114,24 +117,27 @@ begin THE_RD_PROC : process(SYSCLK_IN) begin if rising_edge(SYSCLK_IN) then - buf_tx_read_out <= TX_ALLOW_IN and not ct_fifo_afull ; + buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ; end if; end process; +ct_fifo_reset <= not tx_allow_qtx; TX_READ_OUT <= buf_tx_read_out; ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN; -ct_fifo_read <= tx_allow_qtx and not ram_afull; +ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; ---------------------------------------------------------------------- -- RAM ---------------------------------------------------------------------- -THE_RAM_WR_PROC : process(TXCLK_IN) + THE_RAM_WR_PROC : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - ram_write <= ct_fifo_read and not ct_fifo_empty; + if RESET_IN = '1' then + ram_write <= '0'; + elsif rising_edge(TXCLK_IN) then + ram_write <= ct_fifo_read; end if; end process; @@ -147,10 +153,12 @@ THE_RAM_WR_PROC : process(TXCLK_IN) end process; --RAM read pointer - THE_READ_CNT : process(TXCLK_IN) + THE_READ_CNT : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then + if RESET_IN = '1' then + ram_read_addr <= (others => '0'); + elsif rising_edge(TXCLK_IN) then + if tx_allow_qtx = '0' then ram_read_addr <= (others => '0'); elsif load_read_pointer_i = '1' then ram_read_addr <= unsigned(restart_position_i); @@ -161,10 +169,12 @@ THE_RAM_WR_PROC : process(TXCLK_IN) end process; --RAM write pointer - THE_WRITE_CNT : process(TXCLK_IN) + THE_WRITE_CNT : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then + if RESET_IN = '1' then + ram_write_addr <= (others => '0'); + elsif rising_edge(TXCLK_IN) then + if tx_allow_qtx = '0' then ram_write_addr <= (others => '0'); elsif ram_write = '1' then ram_write_addr <= ram_write_addr + to_unsigned(1,1); @@ -174,10 +184,12 @@ THE_RAM_WR_PROC : process(TXCLK_IN) --RAM fill level counter - THE_FILL_CNT : process(TXCLK_IN) + THE_FILL_CNT : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then + if RESET_IN = '1' then + ram_fill_level <= (others => '0'); + elsif rising_edge(TXCLK_IN) then + if tx_allow_qtx = '0' then ram_fill_level <= (others => '0'); else ram_fill_level <= ram_write_addr - ram_read_addr; @@ -187,8 +199,9 @@ THE_RAM_WR_PROC : process(TXCLK_IN) --RAM empty - ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; - ram_afull <= '1' when ram_fill_level > 4 else '0'; +-- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; + ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; + ram_afull <= '1' when ram_fill_level >= 4 else '0'; @@ -196,94 +209,93 @@ THE_RAM_WR_PROC : process(TXCLK_IN) -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(TXCLK_IN) + THE_DATA_CONTROL_FSM : process(TXCLK_IN, RESET_IN) begin if rising_edge(TXCLK_IN) then --- if RESET_IN = '1' then --- null; --- else - ram_read <= '0'; - - case current_state is - when SLEEP => - TX_DATA_OUT <= x"BC"; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_L; - - when SEND_DATA_L => - TX_DATA_OUT <= ram_dout(7 downto 0); - TX_K_OUT <= '0'; - current_state <= SEND_DATA_H; - - when SEND_DATA_H => - TX_DATA_OUT <= ram_dout(15 downto 8); - TX_K_OUT <= '0'; - --current_state <= see below - - when SEND_IDLE_L => - TX_DATA_OUT <= x"BC"; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_H; - - when SEND_IDLE_H => - TX_DATA_OUT <= x"50"; - TX_K_OUT <= '0'; - --current_state <= see below - - when SEND_START_L => - TX_DATA_OUT <= x"FB"; - TX_K_OUT <= '1'; - current_state <= SEND_START_H; - - when SEND_START_H => - TX_DATA_OUT <= std_logic_vector(ram_read_addr); - TX_K_OUT <= '0'; - --current_state <= see below - - when SEND_REQUEST_L => - TX_DATA_OUT <= x"F7"; - TX_K_OUT <= '1'; - current_state <= SEND_REQUEST_H; - - when SEND_REQUEST_H => - TX_DATA_OUT <= request_position_i; - TX_K_OUT <= '0'; - --current_state <= see below - - when SEND_RESET => - TX_DATA_OUT <= x"FE"; - TX_K_OUT <= '1'; - if SEND_LINK_RESET_IN = '0' then - current_state <= SEND_IDLE_L; - end if; - - when others => - current_state <= SEND_IDLE_L; - end case; - - if current_state = SEND_START_H or - current_state = SEND_IDLE_H or - current_state = SEND_DATA_H or - current_state = SEND_REQUEST_H or - current_state = SLEEP then - if RESET_IN = '1' then - current_state <= SEND_IDLE_L; - elsif send_link_reset_qtx = '1' then - current_state <= SEND_RESET; - elsif make_request_i = '1' then - current_state <= SEND_REQUEST_L; - elsif make_restart_i = '1' then - current_state <= SEND_START_L; - elsif ram_empty = '0' and tx_allow_qtx = '1' then - ram_read <= '1'; - current_state <= SEND_DATA_L; - else + ram_read <= '0'; + + case current_state is + when SLEEP => + TX_DATA_OUT <= x"BC"; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_L; + + when SEND_DATA_L => + TX_DATA_OUT <= ram_dout(7 downto 0); + TX_K_OUT <= '0'; + current_state <= SEND_DATA_H; + + when SEND_DATA_H => + TX_DATA_OUT <= ram_dout(15 downto 8); + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_IDLE_L => + TX_DATA_OUT <= x"BC"; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_H; + + when SEND_IDLE_H => + TX_DATA_OUT <= x"50"; + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_START_L => + TX_DATA_OUT <= x"FB"; + TX_K_OUT <= '1'; + current_state <= SEND_START_H; + + when SEND_START_H => + TX_DATA_OUT <= std_logic_vector(ram_read_addr); + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_REQUEST_L => + TX_DATA_OUT <= x"F7"; + TX_K_OUT <= '1'; + current_state <= SEND_REQUEST_H; + + when SEND_REQUEST_H => + TX_DATA_OUT <= request_position_i; + TX_K_OUT <= '0'; + --current_state <= see below + + when SEND_RESET => + TX_DATA_OUT <= x"FE"; + TX_K_OUT <= '1'; + if send_link_reset_qtx = '0' then current_state <= SEND_IDLE_L; end if; + when others => + current_state <= SEND_IDLE_L; + end case; + + if current_state = SEND_START_H or + current_state = SEND_IDLE_H or + current_state = SEND_DATA_H or + current_state = SEND_REQUEST_H or + current_state = SLEEP then + if tx_allow_qtx = '0' then + current_state <= SEND_IDLE_L; + elsif send_link_reset_qtx = '1' then + current_state <= SEND_RESET; + elsif make_request_i = '1' then + current_state <= SEND_REQUEST_L; + elsif make_restart_i = '1' then + current_state <= SEND_START_L; + elsif ram_empty = '0' then + ram_read <= '1'; + current_state <= SEND_DATA_L; + else + current_state <= SEND_IDLE_L; end if; + end if; --- end if; + end if; + if RESET_IN = '1' then + ram_read <= '0'; + end if; end process; ---------------------------------------------------------------------- @@ -305,6 +317,18 @@ THE_RAM_WR_PROC : process(TXCLK_IN) D_OUT(1) => send_link_reset_qtx ); + THE_TX_TO_SYS_SYNC : signal_sync + generic map( + WIDTH => 1, + DEPTH => 2 + ) + port map( + RESET => '0', + CLK0 => SYSCLK_IN, + CLK1 => SYSCLK_IN, + D_IN(0) => tx_allow_qtx, + D_OUT(0) => tx_allow_q + ); THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync port map( @@ -340,10 +364,13 @@ THE_RAM_WR_PROC : process(TXCLK_IN) --Store Request Retransmit position - THE_STORE_REQUEST_PROC : process(TXCLK_IN) + THE_STORE_REQUEST_PROC : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then + if RESET_IN = '1' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif rising_edge(TXCLK_IN) then + if tx_allow_qtx = '0' then make_request_i <= '0'; request_position_i <= (others => '0'); elsif request_retransmit_i = '1' then @@ -359,10 +386,13 @@ THE_RAM_WR_PROC : process(TXCLK_IN) --Store Restart position - THE_STORE_RESTART_PROC : process(TXCLK_IN) + THE_STORE_RESTART_PROC : process(TXCLK_IN, RESET_IN) begin - if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then + if RESET_IN = '1' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif rising_edge(TXCLK_IN) then + if tx_allow_qtx = '0' then make_restart_i <= '0'; restart_position_i <= (others => '0'); elsif start_retransmit_i = '1' then @@ -382,6 +412,30 @@ THE_RAM_WR_PROC : process(TXCLK_IN) ---------------------------------------------------------------------- -- Debug ---------------------------------------------------------------------- + DEBUG_OUT(0) <= ram_read; + DEBUG_OUT(1) <= ct_fifo_write; + DEBUG_OUT(2) <= ct_fifo_read; + DEBUG_OUT(3) <= tx_allow_qtx; + DEBUG_OUT(4) <= ram_empty; + DEBUG_OUT(5) <= ram_afull; + + + process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + STAT_REG_OUT(7 downto 0) <= ram_fill_level; + STAT_REG_OUT(15 downto 8) <= ram_read_addr; + STAT_REG_OUT(16) <= ram_afull; + STAT_REG_OUT(17) <= ram_empty; + STAT_REG_OUT(18) <= tx_allow_qtx; + STAT_REG_OUT(19) <= TX_ALLOW_IN; + STAT_REG_OUT(20) <= make_restart_i; + STAT_REG_OUT(21) <= make_request_i; + STAT_REG_OUT(31 downto 22) <= (others => '0'); + end if; + end process; + + end architecture; \ No newline at end of file diff --git a/special/handler_data.vhd b/special/handler_data.vhd index e0803f2..1fb55dd 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -282,7 +282,8 @@ begin buffer_state_bits(i) <= "010"; if FEE_DATA_WRITE_IN(i) = '1' then data_counter(i) <= data_counter(i) + to_unsigned(1,1); - elsif FEE_DATA_FINISHED_IN(i) = '1' then + end if; + if FEE_DATA_FINISHED_IN(i) = '1' then current_buffer_state(i) <= WAITING; length_buffer_write(i) <= '1'; end if; diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index 0efda63..26b565f 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -27,7 +27,6 @@ port( LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release --- LVL1_INT_TRG_RESET_IN : in std_logic; -- reset internal trigger counter LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter @@ -367,8 +366,8 @@ begin NEXT_STATE <= TRGFND; next_toc_rst <= '1'; next_val_trg <= '1'; - elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and - (LVL1_TRG_TYPE_IN(3) = '1') and (LVL1_TRG_INFORMATION_IN(7) = '1')) then + elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and + (LVL1_TRG_TYPE_IN(3) = '1') and (LVL1_TRG_INFORMATION_IN(7) = '1')) then -- timingtriggerless trigger found NEXT_STATE <= LVL1FND; next_toc_rst <= '1'; diff --git a/special/spi_master.vhd b/special/spi_master.vhd index 683007c..4e011bf 100755 --- a/special/spi_master.vhd +++ b/special/spi_master.vhd @@ -53,7 +53,7 @@ architecture Behavioral of spi_master is signal reg_bus_data_out : std_logic_vector(31 downto 0); -- readback signal spi_bsm : std_logic_vector(7 downto 0); - signal spi_debug : std_logic_vector(31 downto 0); + signal spi_debug : std_logic_vector(31 downto 0); signal spi_start_x : std_logic; signal spi_start : std_logic; diff --git a/testbenches/tb_fot_interface.vhd b/testbenches/tb_fot_interface.vhd new file mode 100644 index 0000000..6343227 --- /dev/null +++ b/testbenches/tb_fot_interface.vhd @@ -0,0 +1,290 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity tbfot is +end entity; + +architecture arch of tbfot is + +component trb_net16_rx_packets is +port( + -- Resets + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- data stream from SerDes + CLK_IN : in std_logic; -- SerDes RX clock + RX_ALLOW_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component; + + + signal clk : std_logic := '1'; + signal clk25 : std_logic := '1'; + signal reset : std_logic := '1'; + signal reset_async : std_logic := '1'; + + signal toggle1 : std_logic; + signal counter1 : std_logic_vector(11 downto 0); + signal read1 : std_logic; + signal dataready1 : std_logic; + signal number1 : std_logic_vector(2 downto 0); + signal data1 : std_logic_vector(15 downto 0); + + signal toggle2 : std_logic; + signal counter2 : std_logic_vector(11 downto 0); + signal read2 : std_logic; + signal dataready2 : std_logic; + signal number2 : std_logic_vector(2 downto 0); + signal data2 : std_logic_vector(15 downto 0); + + signal tx_data_in : std_logic_vector(15 downto 0); + signal tx_write_in : std_logic; + signal tx_read_out : std_logic; + + signal tx_data_out : std_logic_vector( 7 downto 0); + signal tx_k_out : std_logic; + + signal tx_allow_in : std_logic; + signal send_link_reset_in : std_logic; + + signal dummy : std_logic_vector(31 downto 0); + +begin + + + proc_clk25 : process + begin + wait for 20 ns; + clk25 <= not clk25; + end process; + + + proc_clk : process + begin + wait for 5 ns; + clk <= not clk; + end process; + + proc_reset : process + begin + reset <= '1'; + reset_async <= '1'; + wait for 40 ns; + reset_async <= '0'; + wait for 105 ns; + reset <= '0'; + wait; + end process; + +--control from LSM + proc_lsm : process + begin + tx_allow_in <= '0'; + send_link_reset_in <= '0'; + wait for 350 ns; + wait until rising_edge(clk); wait for 1 ns; + tx_allow_in <= '1'; + send_link_reset_in <= '0'; + wait; + end process; + + + + process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + number1 <= "100"; + dataready1 <= '0'; + toggle1 <= '0'; + counter1 <= (others => '0'); + else + if ((counter1 < 19 and toggle1 = '1') or (counter1 < 14 and toggle1 = '0')) or + (((counter1 < 20 and toggle1 = '1') or (counter1 < 15 and toggle1 = '0')) and read1 = '0') then + dataready1 <= '1'; + if read1 = '1' and dataready1 = '1' then + counter1 <= counter1 + 1; + end if; + else + dataready1 <= '0'; + if counter1 = 2046 then + counter1 <= (others => '0'); + toggle1 <= not toggle1; + else + counter1 <= counter1 + 1; + end if; + end if; + if read1 = '1' and dataready1 = '1' then + if number1 = "100" then + number1 <= "000"; + else + number1 <= number1 + 1; + end if; + end if; + end if; + end if; + end process; + + data1 <= (counter1(7 downto 0)) & (counter1(7 downto 0)); + data2 <= (counter2(7 downto 0)) & (counter2(7 downto 0)); + + process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + number2 <= "100"; + dataready2 <= '0'; + toggle2 <= '0'; + counter2 <= (others => '0'); + else + if ((counter2 < 23 and toggle2 = '1') or (counter2 < 18 and toggle2 = '0')) or + (((counter2 < 24 and toggle2 = '1') or (counter2 < 19 and toggle2 = '0')) and read2 = '0') or + (counter2 = 30 and (dataready2 = '0' or read2 = '0')) then + dataready2 <= '1'; + if read2 = '1' and dataready2 = '1' then + counter2 <= counter2 + 1; + end if; + else + dataready2 <= '0'; + if counter2 = 2047 then + counter2 <= (others => '0'); + toggle2 <= not toggle2; + else + counter2 <= counter2 + 1; + end if; + end if; + if read2 = '1' and dataready2 = '1' then + if number2 = "100" then + number2 <= "000"; + else + number2 <= number2 + 1; + end if; + end if; + end if; + end if; + end process; + + the_test_mux : trb_net16_io_multiplexer + generic map ( + USE_INPUT_SBUF => (others => c_NO) + ) + port map( + -- Misc + CLK => clk, + RESET => reset, + CLK_EN => '1', + -- Media direction port + MED_DATAREADY_IN => '0', + MED_DATA_IN => (others => '0'), + MED_PACKET_NUM_IN => (others => '0'), + MED_READ_OUT => open, + MED_DATAREADY_OUT => tx_write_in, + MED_DATA_OUT => tx_data_in, + MED_PACKET_NUM_OUT => open, + MED_READ_IN => tx_read_out, + -- Internal direction port + INT_DATA_OUT => open, + INT_PACKET_NUM_OUT => open, + INT_DATAREADY_OUT => open, + INT_READ_IN => (others => '1'), + INT_DATAREADY_IN(0) => dataready1, + INT_DATAREADY_IN(1) => '0', + INT_DATAREADY_IN(2) => dataready2, + INT_DATAREADY_IN(7 downto 3) => (others => '0'), + INT_DATA_IN(15 downto 0) => data1, + INT_DATA_IN(31 downto 16) => (others => '0'), + INT_DATA_IN(47 downto 32) => data2, + INT_DATA_IN(127 downto 48) => (others => '0'), + INT_PACKET_NUM_IN(2 downto 0) => number1, + INT_PACKET_NUM_IN(5 downto 3) => "000", + INT_PACKET_NUM_IN(8 downto 6) => number2, + INT_PACKET_NUM_IN(23 downto 9)=> (others => '0'), + INT_READ_OUT(0) => read1, + INT_READ_OUT(1) => dummy(0), + INT_READ_OUT(2) => read2, + INT_READ_OUT(3) => dummy(1), + INT_READ_OUT(7 downto 4) => dummy(6 downto 3), + ctrl => (others => '0') + ); + + + the_tx_control : trb_net16_tx_control + port map( + TXCLK_IN => clk25, + RXCLK_IN => clk25, + SYSCLK_IN => clk, + RESET_IN => reset, + + TX_DATA_IN => tx_data_in, + TX_WRITE_IN => tx_write_in, + TX_READ_OUT => tx_read_out, + + TX_DATA_OUT => tx_data_out, + TX_K_OUT => tx_k_out, + + REQUEST_RETRANSMIT_IN => '0', + REQUEST_POSITION_IN => (others => '0'), + + START_RETRANSMIT_IN => '0', + START_POSITION_IN => (others => '0'), + + SEND_LINK_RESET_IN => '0', + TX_ALLOW_IN => tx_allow_in, + + DEBUG_OUT => open + ); + + + + THE_RX_CONTROL : trb_net16_rx_packets + port map( + -- Resets + RESET_IN => reset, + QUAD_RST_IN => reset_async, + -- data stream from SerDes + CLK_IN => clk25, + RX_ALLOW_IN => tx_allow_in, + RX_DATA_IN => tx_data_out(7 downto 0), + RX_K_IN => tx_k_out, + -- media interface + SYSCLK_IN => clk, + MED_DATA_OUT => open, + MED_DATAREADY_OUT => open, + MED_READ_IN => '1', + MED_PACKET_NUM_OUT => open, + -- reset handling + SEND_RESET_WORDS_OUT => open, + MAKE_TRBNET_RESET_OUT => open, + -- Status signals + PACKET_TIMEOUT_OUT => open, + -- Debug signals + BSM_OUT => open, + DBG_OUT => open + ); + + + + +end architecture; \ No newline at end of file diff --git a/testbenches/tb_trb_net16_tx_control.vhd b/testbenches/tb_trb_net16_tx_control.vhd index a4574b5..2a5a2fa 100644 --- a/testbenches/tb_trb_net16_tx_control.vhd +++ b/testbenches/tb_trb_net16_tx_control.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; ---use work.trb_net_components.all; +use work.trb_net_components.all; entity txtb is end entity; @@ -56,6 +56,16 @@ architecture arch of txtb is signal tx_allow_in : std_logic; +-- signal INT_DATA_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); +-- signal INT_PACKET_NUM_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); +-- signal INT_DATAREADY_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); +-- signal INT_READ_IN : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + signal INT_DATAREADY : STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + signal INT_DATA : STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); + signal INT_PACKET_NUM : STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); + signal INT_READ : STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + begin proc_clk25 : process @@ -105,80 +115,231 @@ begin DEBUG_OUT => open ); + + the_mux: trb_net16_io_multiplexer + generic map( + USE_INPUT_SBUF => (others => c_NO) + ) + port map( + -- Misc + CLK => clk, + RESET => reset, + CLK_EN => '1', + + -- Media direction port + MED_DATAREADY_IN => '0', + MED_DATA_IN => (others => '0'), + MED_PACKET_NUM_IN => (others => '0'), + MED_READ_OUT => open, + + MED_DATAREADY_OUT => tx_write_in, + MED_DATA_OUT => tx_data_in, + MED_PACKET_NUM_OUT => open, + MED_READ_IN => tx_read_out, + + -- Internal direction port + INT_DATA_OUT => open, + INT_PACKET_NUM_OUT => open, + INT_DATAREADY_OUT => open, + INT_READ_IN => (others => '1'), + + INT_DATAREADY_IN => int_dataready, + INT_DATA_IN => int_data, + INT_PACKET_NUM_IN => int_packet_num, + INT_READ_OUT => int_read, + + -- Status and control port + CTRL => (others => '0'), + STAT => open + ); + + --Data input process begin - tx_data_in <= (others => '0'); - tx_write_in <= '0'; + int_data(31 downto 16) <= (others => '0'); + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '0'; wait for 300 ns; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"1001"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0101"; + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"0202"; + int_packet_num(5 downto 3) <= "000"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_dataready(1) <= '0'; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"0303"; + int_packet_num(5 downto 3) <= "001"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"2002"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0404"; + int_packet_num(5 downto 3) <= "010"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_write_in <= '0'; + int_dataready(1) <= '0'; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"3003"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0505"; + int_packet_num(5 downto 3) <= "011"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"4004"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_dataready(1) <= '0'; + wait for 1 us; wait until rising_edge(clk); wait for 1 ns; - tx_write_in <= '0'; + int_data(31 downto 16) <= x"0606"; + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"5005"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0707"; + int_packet_num(5 downto 3) <= "000"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"6006"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0808"; + int_packet_num(5 downto 3) <= "001"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"7007"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0909"; + int_packet_num(5 downto 3) <= "010"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"8008"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0a0a"; + int_packet_num(5 downto 3) <= "011"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"9009"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0b0b"; + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"a00a"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0c0c"; + int_packet_num(5 downto 3) <= "000"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"b00b"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0d0d"; + int_packet_num(5 downto 3) <= "001"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"c00c"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0e0e"; + int_packet_num(5 downto 3) <= "010"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"d00d"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"0f0f"; + int_packet_num(5 downto 3) <= "011"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"e00e"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"1010"; + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= x"f00f"; - tx_write_in <= '1'; - if tx_read_out = '0' then wait until tx_read_out = '1'; end if; + int_data(31 downto 16) <= x"2020"; + int_packet_num(5 downto 3) <= "000"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; wait until rising_edge(clk); wait for 1 ns; - tx_data_in <= (others => '0'); - tx_write_in <= '0'; + int_data(31 downto 16) <= x"3030"; + int_packet_num(5 downto 3) <= "001"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"4040"; + int_packet_num(5 downto 3) <= "010"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"5050"; + int_packet_num(5 downto 3) <= "011"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"6060"; + int_packet_num(5 downto 3) <= "100"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"7070"; + int_packet_num(5 downto 3) <= "000"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"8080"; + int_packet_num(5 downto 3) <= "001"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"9090"; + int_packet_num(5 downto 3) <= "010"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= x"a0a0"; + int_packet_num(5 downto 3) <= "011"; + int_dataready(1) <= '1'; + if int_read(1) = '0' then wait until int_read(1) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(31 downto 16) <= (others => '0'); + int_dataready(1) <= '0'; + wait for 970 ns; + end process; + + +--Data input + process + begin + int_data(15 downto 0) <= (others => '0'); + int_packet_num(2 downto 0) <= "100"; + int_dataready(0) <= '0'; wait; + wait for 300 ns; + wait until rising_edge(clk); wait for 1 ns; + int_data(15 downto 0) <= x"1111"; + int_packet_num(2 downto 0) <= "100"; + int_dataready(0) <= '1'; + if int_read(0) = '0' then wait until int_read(0) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(15 downto 0) <= x"2222"; + int_packet_num(2 downto 0) <= "000"; + int_dataready(0) <= '1'; + if int_read(0) = '0' then wait until int_read(0) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_dataready(0) <= '0'; + wait until rising_edge(clk); wait for 1 ns; + int_data(15 downto 0) <= x"3333"; + int_packet_num(2 downto 0) <= "001"; + int_dataready(0) <= '1'; + if int_read(0) = '0' then wait until int_read(0) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_data(15 downto 0) <= x"4444"; + int_packet_num(2 downto 0) <= "010"; + int_dataready(0) <= '1'; + if int_read(0) = '0' then wait until int_read(0) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_dataready(0) <= '0'; + wait until rising_edge(clk); wait for 1 ns; + int_data(15 downto 0) <= x"5555"; + int_packet_num(2 downto 0) <= "011"; + int_dataready(0) <= '1'; + if int_read(0) = '0' then wait until int_read(0) = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + int_dataready(0) <= '0'; + wait for 700 ns; end process; @@ -202,14 +363,14 @@ begin start_position_in <= (others => '0'); wait for 630 ns; wait until rising_edge(clk); wait for 1 ns; - start_retransmit_in <= '1'; + start_retransmit_in <= '0'; start_position_in <= std_logic_vector(to_unsigned(5,8)); wait until rising_edge(clk); wait for 1 ns; start_retransmit_in <= '0'; start_position_in <= (others => '0'); wait for 1050 ns; wait until rising_edge(clk); wait for 1 ns; - start_retransmit_in <= '1'; + start_retransmit_in <= '0'; start_position_in <= std_logic_vector(to_unsigned(15,8)); wait until rising_edge(clk); wait for 1 ns; start_retransmit_in <= '0'; @@ -230,8 +391,6 @@ begin end process; - - end architecture; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index f740cd5..b02c11b 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -262,7 +262,12 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full signal int_trg_reset : std_logic; signal reset_trg_logic : std_logic; signal stat_lvl1_handler : std_logic_vector(63 downto 0); + signal stat_counters_lvl1_handler: std_logic_vector(63 downto 0); signal trg_invert_i : std_logic; + signal int_lvl1_timeout_detected : std_logic; + signal int_lvl1_spurious_trg : std_logic; + signal int_lvl1_missing_tmg_trg : std_logic; + signal int_spike_detected : std_logic; signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic; @@ -298,8 +303,9 @@ begin end if; end process; - MED_CTRL_OP_OUT(15 downto 0) <= (8 => buf_REGIO_COMMON_CTRL_REG_OUT(64+27), - others => '0'); + MED_CTRL_OP_OUT(7 downto 0) <= (others => '0'); + MED_CTRL_OP_OUT(8) <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27); + MED_CTRL_OP_OUT(15 downto 9) <= (others => '0'); MED_STAT_OP <= MED_STAT_OP_IN; --Connections for data channel @@ -310,6 +316,7 @@ begin IBUF_DEPTH => IBUF_DEPTH(i), IBUF_SECURE_MODE => IBUF_SECURE_MODE(i), SBUF_VERSION => 0, + SBUF_VERSION_OBUF => 6, OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH, USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i), USE_CHECKSUM => USE_CHECKSUM(i), @@ -743,6 +750,9 @@ begin MPLEX: trb_net16_io_multiplexer + generic map( + USE_INPUT_SBUF => (1,1,1,1,0,0,1,1) + ) port map ( CLK => CLK, RESET => reset_no_link, @@ -791,8 +801,9 @@ begin link_error_i, link_and_reset_status, stat_lvl1_handler) begin buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; - buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match; - buf_COMMON_STAT_REG_IN(8) <= timing_trigger_missing_stat; + buf_COMMON_STAT_REG_IN(4) <= stat_lvl1_handler(12); + buf_COMMON_STAT_REG_IN(8) <= int_lvl1_missing_tmg_trg; + buf_COMMON_STAT_REG_IN(13) <= stat_lvl1_handler(7); buf_COMMON_STAT_REG_IN(15) <= link_error_i; if REGIO_USE_1WIRE_INTERFACE = c_YES then buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature; @@ -800,6 +811,11 @@ begin buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num; buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler; buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0); + buf_COMMON_STAT_REG_IN(175 downto 160) <= buf_LVL1_TRG_INFORMATION_OUT(15 downto 0); + buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT; + buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0); + buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT; + buf_COMMON_STAT_REG_IN(255 downto 192) <= stat_counters_lvl1_handler; end process; @@ -848,131 +864,137 @@ begin -- Check LVL1 trigger number ------------------------------------------------- --- THE_LVL1_HANDLER : handler_lvl1 --- generic map ( --- TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW --- ) --- port map( --- RESET => reset_trg_logic, --- CLOCK => CLK, --- --Timing Trigger --- LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN, --- LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16), --- --LVL1_handler connection --- LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT, --- LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT, --- LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT, --- LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT, --- LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT, --- LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN, --- LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN, + THE_LVL1_HANDLER : handler_lvl1 + generic map ( + TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW + ) + port map( + RESET => reset_trg_logic, + RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5), + CLOCK => CLK, + --Timing Trigger + LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN, + LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16), + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT, + LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT, + LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT, + LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT, + LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT, + LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN, + + LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, + LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1), + LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32), + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT, + LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT, + LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT, + LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT, + LVL1_MULTIPLE_TRG_OUT => int_multiple_trg, + LVL1_DELAY_OUT => int_lvl1_delay, + LVL1_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected, + LVL1_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg, + LVL1_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg, + SPIKE_DETECTED_OUT => int_spike_detected, + + LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + + --Stat/Control + STATUS_OUT => stat_lvl1_handler, + TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95), + TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93), + COUNTERS_STATUS_OUT => stat_counters_lvl1_handler, + --Debug + DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT + ); + + + +-- THE_TRG_SYNC : signal_sync +-- generic map( +-- DEPTH => 2, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => RESET, +-- D_IN(0) => TRG_TIMING_TRG_RECEIVED_IN, +-- CLK0 => CLK, +-- CLK1 => CLK, +-- D_OUT(0) => reg_timing_trigger +-- ); -- --- LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, --- LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1), --- LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32), -- --- --FEE logic / Data Handler --- LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT, --- LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT, --- LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT, --- LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT, --- LVL1_MULTIPLE_TRG_OUT => int_multiple_trg, --- LVL1_DELAY_OUT => int_lvl1_delay, -- --- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, --- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, -- --- --Stat/Control --- STATUS_OUT => stat_lvl1_handler, --- TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95), --- TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93), --- --Debug --- DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT --- ); +-- proc_internal_trigger_number : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if reset_no_link = '1' then +-- int_trigger_num <= (others => '0'); +-- elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then +-- int_trigger_num <= int_trigger_num + 1; +-- elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then +-- int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32); +-- end if; +-- end if; +-- end process; -- - - - THE_TRG_SYNC : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => TRG_TIMING_TRG_RECEIVED_IN, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => reg_timing_trigger - ); - - - - - proc_internal_trigger_number : process(CLK) - begin - if rising_edge(CLK) then - if reset_no_link = '1' then - int_trigger_num <= (others => '0'); - elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then - int_trigger_num <= int_trigger_num + 1; - elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then - int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32); - end if; - end if; - end process; - - proc_check_trigger_number : process(CLK) - begin - if rising_edge(CLK) then - if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then - trigger_number_match <= '1'; - elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then - if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then - trigger_number_match <= '1'; - else - trigger_number_match <= '0'; - end if; - end if; - end if; - end process; - - - proc_detect_trigger_receive : process(CLK) - begin - if rising_edge(CLK) then - last_reg_timing_trigger <= reg_timing_trigger; - trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95); - - last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; - LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT; - LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT; - - if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then - got_timing_trigger <= '0'; - got_timingless_trigger <= '0'; - timing_trigger_missing <= '0'; - elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN - got_timing_trigger <= '1'; - elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then - got_timingless_trigger <= '1'; - elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then - timing_trigger_missing <= '1'; - end if; - end if; - end process; - - - proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger ) - begin - buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN; - buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16); - buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17); - end process; - - buf_LVL1_VALID_TIMING_TRG_OUT <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN; - buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger - and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7); - buf_LVL1_INVALID_TRG_OUT <= '0'; +-- proc_check_trigger_number : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then +-- trigger_number_match <= '1'; +-- elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then +-- if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then +-- trigger_number_match <= '1'; +-- else +-- trigger_number_match <= '0'; +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- +-- proc_detect_trigger_receive : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- last_reg_timing_trigger <= reg_timing_trigger; +-- trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95); +-- +-- last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; +-- LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT; +-- LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT; +-- +-- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then +-- got_timing_trigger <= '0'; +-- got_timingless_trigger <= '0'; +-- timing_trigger_missing <= '0'; +-- elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN +-- got_timing_trigger <= '1'; +-- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then +-- got_timingless_trigger <= '1'; +-- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then +-- timing_trigger_missing <= '1'; +-- end if; +-- end if; +-- end process; +-- +-- +-- proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger ) +-- begin +-- buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN; +-- buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16); +-- buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17); +-- end process; +-- +-- buf_LVL1_VALID_TIMING_TRG_OUT <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN; +-- buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger +-- and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7); +-- buf_LVL1_INVALID_TRG_OUT <= '0'; -- proc_count_timing_trg : process(CLK) -- begin @@ -993,9 +1015,9 @@ begin ------------------------------------------------- -- Connect Outputs ------------------------------------------------- - buf_LVL1_TRG_RELEASE_IN <= LVL1_TRG_RELEASE_IN; --changed back - LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; --changed back - --LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_DATA_VALID_OUT; --changed back +-- buf_LVL1_TRG_RELEASE_IN <= LVL1_TRG_RELEASE_IN; --changed back +-- LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; --changed back + LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_DATA_VALID_OUT; --changed back LVL1_TRG_VALID_TIMING_OUT <= buf_LVL1_VALID_TIMING_TRG_OUT; LVL1_TRG_VALID_NOTIMING_OUT <= buf_LVL1_VALID_NOTIMING_TRG_OUT; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index cf1c6f6..a163016 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -17,7 +17,7 @@ entity trb_net16_endpoint_hades_full_handler is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); @@ -400,7 +400,7 @@ begin BUS_ADDR_OUT(19 downto 16) => dbuf_addr, BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78), - BUS_ADDR_OUT(95 downto 48) => dummy(241 downto 194), + BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(94), BUS_TIMEOUT_OUT(2) => dummy(95), @@ -507,7 +507,7 @@ begin ); reset_ipu_i <= RESET or common_ctrl_reg_i(2); - lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i; + lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i; STAT_DEBUG_IPU_HANDLER_OUT <= debug_ipu_handler_i; STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 55dbafa..e0ee39b 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -25,7 +25,7 @@ entity trb_net16_hub_base is INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_000050FF_00000000" & + x"00000000_00000000_000090FF_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; @@ -40,6 +40,7 @@ entity trb_net16_hub_base is MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO); -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); @@ -301,28 +302,32 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal iobuf_reset_ipu_counter : std_logic; signal iobuf_reset_sctrl_counter : std_logic; + type tv_t is array (2**(c_MUX_WIDTH-1)-1 downto 0) of std_logic_vector(15 downto 0); + signal current_timeout_value : tv_t; + signal hub_level : std_logic_vector(3 downto 0); + type cnt_t is array (MII_NUMBER-1 downto 0) of unsigned(31 downto 0); - signal busy_counter_excl : cnt_t; - signal busy_counter_incl : cnt_t; - signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER-1 downto 0); - signal reg_excl_enable : std_logic_vector(MII_NUMBER-1 downto 0); + signal busy_counter_excl : cnt_t; + signal busy_counter_incl : cnt_t; + signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER-1 downto 0); + signal reg_excl_enable : std_logic_vector(MII_NUMBER-1 downto 0); - signal mii_error : std_logic_vector(31 downto 0); + signal mii_error : std_logic_vector(31 downto 0); signal iobuf_stat_init_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0); signal iobuf_stat_reply_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0); - signal led_counter : unsigned(9 downto 0); - signal hub_led_i : std_logic_vector(MII_NUMBER-1 downto 0); - signal hub_show_port : std_logic_vector(MII_NUMBER-1 downto 0); + signal led_counter : unsigned(9 downto 0); + signal hub_led_i : std_logic_vector(MII_NUMBER-1 downto 0); + signal hub_show_port : std_logic_vector(MII_NUMBER-1 downto 0); - signal lsm_addr : std_logic_vector(3 downto 0); - signal lsm_read : std_logic; - signal lsm_write : std_logic; - signal lsm_data : std_logic_vector(31 downto 0); - signal next_lsm_data : std_logic_vector(31 downto 0); - signal last_lsm_read : std_logic; - signal next_last_lsm_read : std_logic; + signal lsm_addr : std_logic_vector(3 downto 0); + signal lsm_read : std_logic; + signal lsm_write : std_logic; + signal lsm_data : std_logic_vector(31 downto 0); + signal next_lsm_data : std_logic_vector(31 downto 0); + signal last_lsm_read : std_logic; + signal next_last_lsm_read : std_logic; type counter8b_t is array (0 to 15) of unsigned(7 downto 0); signal received_retransmit_requests : counter8b_t; @@ -384,8 +389,9 @@ begin proc_SYNC_CTRL_OP : process(CLK) begin if rising_edge(CLK) then - MED_CTRL_OP(12+i*16 downto i*16) <= (others => '0'); + MED_CTRL_OP(7+i*16 downto i*16) <= (others => '0'); MED_CTRL_OP(8+i*16) <= HC_COMMON_CTRL_REGS(64+27); + MED_CTRL_OP(12+i*16 downto 9+i*16) <= (others => '0'); MED_CTRL_OP(13+i*16) <= local_reset_med(i); MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i); if MII_IS_UPLINK(i) = 0 then @@ -531,10 +537,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32), STAT_DATA_COUNTER => IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32), CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), - CTRL_OBUF_settings( 3 downto 0) => HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), - CTRL_OBUF_settings(15 downto 4) => (others => '0'), - CTRL_OBUF_settings(19 downto 16) => HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), - CTRL_OBUF_settings(31 downto 20) => (others => '0'), + CTRL_OBUF_settings(15 downto 0) => current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), + CTRL_OBUF_settings(31 downto 16) => current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16), STAT_INIT_OBUF_DEBUG => iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32), STAT_REPLY_OBUF_DEBUG => iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32), TIMER_TICKS_IN(0) => timer_us_tick, @@ -845,7 +849,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; HUBLOGIC : trb_net16_hub_logic generic map ( --media interfaces - POINT_NUMBER => point_num + POINT_NUMBER => point_num, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY ) port map( CLK => CLK, @@ -873,7 +878,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32), STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32), STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16), - CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), + CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), CTRL_TIMER_TICK(0) => timer_us_tick, CTRL_TIMER_TICK(1) => timer_ms_tick @@ -913,7 +918,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32), STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16), STAT_FSM => stat_ipu_fsm, - CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), + CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), CTRL_TIMER_TICK(0) => timer_us_tick, CTRL_TIMER_TICK(1) => timer_ms_tick @@ -1200,23 +1205,43 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --Status and Control Registers --------------------------------------------------------------------- + gen_timeout_values : for k in 0 to 3 generate + proc_get_timeout_value : process(CLK) + begin + if rising_edge(CLK) then + case to_integer(unsigned(HUB_CTRL_TIMEOUT_TIME(k*4+3 downto k*4))) is + when 0 => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16)); + when 1 => current_timeout_value(k) <= std_logic_vector(to_unsigned(64,16) - unsigned(hub_level&'0')); + when 2 => current_timeout_value(k) <= std_logic_vector(to_unsigned(128,16) - unsigned(hub_level&'0')); + when 3 => current_timeout_value(k) <= std_logic_vector(to_unsigned(256,16) - unsigned(hub_level&'0')); + when 4 => current_timeout_value(k) <= std_logic_vector(to_unsigned(1000,16) - unsigned(hub_level&'0')); + when 5 => current_timeout_value(k) <= std_logic_vector(to_unsigned(2000,16) - unsigned(hub_level&'0')); + when 6 => current_timeout_value(k) <= std_logic_vector(to_unsigned(4000,16) - unsigned(hub_level&'0')); + when 7 => current_timeout_value(k) <= std_logic_vector(to_unsigned(8000,16) - unsigned(hub_level&'0')); + when others => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16)); + end case; + end if; + end process; + end generate; + + --Usual common stat reg, trigger counters are not in use here HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0); HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT; HC_COMMON_STAT_REGS(63 downto 32) <= COMMON_STAT_REGS(63 downto 32); --Status Registers - buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked; - buf_HC_STAT_REGS(4*32+MII_NUMBER-1 downto 4*32) <= HUB_MED_CONNECTED(MII_NUMBER-1 downto 0); - buf_HC_STAT_REGS(5*32-1 downto 4*32+MII_NUMBER) <= (others => '0'); - buf_HC_STAT_REGS(6*32-1 downto 5*32+17) <= (others => '0'); - buf_HC_STAT_REGS(7*32-1 downto 6*32+17) <= (others => '0'); - buf_HC_STAT_REGS(8*32-1 downto 7*32) <= stat_ipu_fsm; - buf_HC_STAT_REGS(16*32-1 downto 12*32) <= HC_STAT_ack_waiting; - buf_HC_STAT_REGS(16*32+MII_NUMBER-1 downto 16*32) <= mii_error(MII_NUMBER-1 downto 0); - buf_HC_STAT_REGS(32*32-1 downto 16*32+MII_NUMBER) <= (others => '0'); - buf_HC_STAT_REGS(36*32-1 downto 32*32) <= HUB_STAT_ERRORBITS; - buf_HC_STAT_REGS(64*32-1 downto 36*32) <= (others => '0'); + buf_HC_STAT_REGS(3*32+31 downto 0) <= buf_STAT_POINTS_locked; + buf_HC_STAT_REGS(4*32+MII_NUMBER-1 downto 4*32) <= HUB_MED_CONNECTED(MII_NUMBER-1 downto 0); + buf_HC_STAT_REGS(4*32+31 downto 4*32+MII_NUMBER) <= (others => '0'); + buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0'); + buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0'); + buf_HC_STAT_REGS(7*32+31 downto 7*32) <= stat_ipu_fsm; + buf_HC_STAT_REGS(15*32-1 downto 8*32) <= (others => '0'); + buf_HC_STAT_REGS(16*32+MII_NUMBER-1 downto 16*32) <= mii_error(MII_NUMBER-1 downto 0); + buf_HC_STAT_REGS(31*32+31 downto 16*32+MII_NUMBER) <= (others => '0'); + buf_HC_STAT_REGS(35*32+31 downto 32*32) <= HUB_STAT_ERRORBITS; + buf_HC_STAT_REGS(63*32+31 downto 36*32) <= (others => '0'); loop_links : for i in 0 to 16 generate buf_HC_STAT_REGS(5*32+i) <= '1' when (i < MII_NUMBER or (i = MII_NUMBER and INT_NUMBER > 0)) and MII_IS_UPLINK(i) = 1 else '0'; @@ -1227,7 +1252,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); begin if rising_edge(CLK) then gen_bits : for i in 0 to MII_NUMBER-1 loop - if MED_STAT_OP(i*16+15) = '0' and MED_STAT_OP(i*16+13) = '0' and MED_STAT_OP(i*16+7 downto i*16+4) = "0111" then + if MED_STAT_OP(i*16+15 downto i*16+13) = "000" and MED_STAT_OP(i*16+12) = '1' and RESET = '0' then mii_error(i) <= '1'; elsif STAT_REG_STROBE(16) = '1' then mii_error(i) <= '0'; @@ -1241,29 +1266,51 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); begin if rising_edge(CLK) then reg_STROBES <= STAT_REG_STROBE; ---Timeouts +--Timeouts 88-8B if reg_STROBES(8) = '1' then - buf_HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0'); + HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0'); else - buf_HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or buf_HC_STAT_REGS(8*32+31 downto 8*32); + HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or HC_STAT_REGS(8*32+31 downto 8*32); end if; if reg_STROBES(9) = '1' then - buf_HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0'); + HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0'); else - buf_HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or buf_HC_STAT_REGS(9*32+31 downto 9*32); + HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or HC_STAT_REGS(9*32+31 downto 9*32); end if; if reg_STROBES(10) = '1' then - buf_HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); + HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); else - buf_HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or buf_HC_STAT_REGS(10*32+31 downto 10*32); + HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or HC_STAT_REGS(10*32+31 downto 10*32); end if; if reg_STROBES(11) = '1' then - buf_HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0'); + HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0'); else - buf_HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or buf_HC_STAT_REGS(11*32+31 downto 11*32); + HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or HC_STAT_REGS(11*32+31 downto 11*32); end if; ---Error on slowcontrol +--Waiting for ACK timeout 8C-8F + if reg_STROBES(12) = '1' then + HC_STAT_REGS(12*32+31 downto 12*32) <= (others => '0'); + else + HC_STAT_REGS(12*32+31 downto 12*32) <= HC_STAT_ack_waiting(0*32+31 downto 0*32) or HC_STAT_REGS(12*32+31 downto 12*32); + end if; + if reg_STROBES(13) = '1' then + HC_STAT_REGS(13*32+31 downto 13*32) <= (others => '0'); + else + HC_STAT_REGS(13*32+31 downto 13*32) <= HC_STAT_ack_waiting(1*32+31 downto 1*32) or HC_STAT_REGS(13*32+31 downto 13*32); + end if; + if reg_STROBES(14) = '1' then + HC_STAT_REGS(14*32+31 downto 14*32) <= (others => '0'); + else + HC_STAT_REGS(14*32+31 downto 14*32) <= HC_STAT_ack_waiting(2*32+31 downto 2*32) or HC_STAT_REGS(14*32+31 downto 14*32); + end if; + if reg_STROBES(15) = '1' then + HC_STAT_REGS(15*32+31 downto 15*32) <= (others => '0'); + else + HC_STAT_REGS(15*32+31 downto 15*32) <= HC_STAT_ack_waiting(3*32+31 downto 3*32) or HC_STAT_REGS(15*32+31 downto 15*32); + end if; + +--Error on slowcontrol A4 if reg_STROBES(36) = '1' then HC_STAT_REGS(36*32+31 downto 36*32) <= (others => '0'); else @@ -1295,15 +1342,13 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); end if; end process; - HC_STAT_REGS(11*32+31 downto 8*32) <= buf_HC_STAT_REGS(11*32+31 downto 8*32); PROC_REG_STAT_REGS : process(CLK) begin if rising_edge(CLK) then HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0); - HC_STAT_REGS(36*32-1 downto 12*32) <= buf_HC_STAT_REGS(36*32-1 downto 12*32); - HC_STAT_REGS(48*32-1 downto 39*32) <= buf_HC_STAT_REGS(48*32-1 downto 39*32); - HC_STAT_REGS(64*32-1 downto 48*32) <= buf_HC_STAT_REGS(64*32-1 downto 48*32); + HC_STAT_REGS(36*32-1 downto 16*32) <= buf_HC_STAT_REGS(36*32-1 downto 16*32); + HC_STAT_REGS(64*32-1 downto 39*32) <= buf_HC_STAT_REGS(64*32-1 downto 39*32); end if; end process; @@ -1492,11 +1537,11 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); if rising_edge(CLK) then for i in 0 to 2**(c_MUX_WIDTH-1)-1 loop if HUB_locked(i) = '0' then - HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32) and not HC_STAT_ack_waiting(i*32+31 downto i*32); + HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32); if i < 2 and INT_NUMBER = 3 then - HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HC_CTRL_REGS(i*32+MII_NUMBER) and not HC_STAT_ack_waiting(i*32+MII_NUMBER) and stream_port_connected; + HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HC_CTRL_REGS(i*32+MII_NUMBER) and stream_port_connected; else - HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HC_CTRL_REGS(i*32+MII_NUMBER+1) and not HC_STAT_ack_waiting(i*32+MII_NUMBER+1) and stream_port_connected; + HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HC_CTRL_REGS(i*32+MII_NUMBER+1) and stream_port_connected; end if; else HUB_CTRL_activepoints(i*32+31 downto i*32) <= HUB_CTRL_activepoints(i*32+31 downto i*32) and not HC_STAT_ack_waiting(i*32+31 downto i*32); @@ -1513,9 +1558,10 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); PROC_timeout_settings : process (CLK) begin if rising_edge(CLK) then - if CTRL_REG_STROBE(5) = '1' then +-- if CTRL_REG_STROBE(5) = '1' then HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32); - end if; + hub_level <= HC_CTRL_REGS(5*32+19 downto 5*32+16); +-- end if; end if; end process; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 6ae6e06..7f5573e 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -113,6 +113,7 @@ package trb_net16_hub_func is MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO); -- settings for external api connections INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); @@ -212,7 +213,8 @@ component trb_net16_hub_streaming_port is MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); - MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES) + MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) ); port( @@ -324,7 +326,7 @@ component trb_net16_hub_streaming_port is STAT_ERRORBITS : out std_logic_vector (31 downto 0); STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); STAT_FSM : out std_logic_vector (31 downto 0); - CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); + CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); @@ -335,7 +337,8 @@ component trb_net16_hub_streaming_port is component trb_net16_hub_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 32 := 2 + POINT_NUMBER : integer range 2 to 32 := 2; + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) ); port ( CLK : in std_logic; @@ -363,7 +366,7 @@ component trb_net16_hub_streaming_port is STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); - CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); + CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 348df1b..d2b9072 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -47,7 +47,7 @@ entity trb_net16_hub_ipu_logic is STAT_ERRORBITS : out std_logic_vector (31 downto 0); STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); STAT_FSM : out std_logic_vector (31 downto 0); - CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); + CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); @@ -205,7 +205,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is -- signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0); signal timeout_found : std_logic; - signal reg_CTRL_TIMEOUT_TIME : std_logic_vector(3 downto 0); + signal reg_CTRL_TIMEOUT_TIME : unsigned(15 downto 0); signal timer_us_tick : std_logic; signal timer_ms_tick : std_logic; @@ -548,18 +548,44 @@ begin --Check for Timeouts ---------------------------------- +-- gen_timeout_counters : for i in 0 to POINT_NUMBER-1 generate +-- proc_timeout_counters : process (CLK) +-- begin +-- if rising_edge(CLK) then +-- connection_timed_out(i) <= '0'; +-- reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME; +-- timeout_found <= or_all(connection_timed_out); +-- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then +-- timeout_counter(i) <= (others => '0'); +-- elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1'))) = '1' then +-- connection_timed_out(i) <= '1'; +-- elsif timer_ms_tick = '1' then +-- timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); +-- end if; +-- end if; +-- end process; +-- end generate; + + + proc_reg_setting : process (CLK) + begin + if rising_edge(CLK) then + reg_CTRL_TIMEOUT_TIME <= unsigned(CTRL_TIMEOUT_TIME); + timeout_found <= or_all(connection_timed_out); + end if; + end process; + gen_timeout_counters : for i in 0 to POINT_NUMBER-1 generate - proc_timeout_counters : process (CLK) + proc_ack_timeout_counters : process (CLK) begin if rising_edge(CLK) then connection_timed_out(i) <= '0'; - reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME; - timeout_found <= or_all(connection_timed_out); - if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then + if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' + or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then timeout_counter(i) <= (others => '0'); - elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1'))) = '1' then + elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then connection_timed_out(i) <= '1'; - elsif timer_ms_tick = '1' then + elsif timer_ms_tick = '1' and got_trm(i) = '0' then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); end if; end if; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index b717f6e..ce71f7c 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -7,12 +7,13 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; - +use work.trb_net16_hub_func.all; entity trb_net16_hub_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 32 := 17 + POINT_NUMBER : integer range 2 to 32 := 17; + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) ); port ( CLK : in std_logic; @@ -42,17 +43,13 @@ entity trb_net16_hub_logic is STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); - CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); + CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) ); end entity; architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of trb_net16_hub_logic_arch : architecture is "HUBLOGIC_group"; --signals init_pool @@ -63,26 +60,27 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); - signal buf_INIT_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); - signal buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); - signal REPLY_POOL_DATAREADY : std_logic; - signal REPLY_POOL_READ : std_logic; - signal REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0); - signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); - signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); - signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reading_trmF0 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal REPLY_combined_trm_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal REPLY_MUX_real_reading : std_logic; - signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); + signal buf_INIT_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal REPLY_POOL_DATAREADY : std_logic; + signal REPLY_POOL_READ : std_logic; + signal REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal saved_REPLY_TYPE : std_logic_vector(2 downto 0); + signal current_REPLY_TYPE : std_logic_vector(2 downto 0); + signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_trmF0 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal REPLY_combined_trm_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_combined_trm_F1 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_combined_trm_F3 : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_MUX_real_reading : std_logic; + signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); --general signals signal locked, next_locked : std_logic; @@ -95,7 +93,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal get_init_locked, release_init_locked: std_logic; signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_arbiter_result : std_logic_vector(POINT_NUMBER-1 downto 0); type state_type is (SENDING_DATA, SENDING_REPLY_TRM); signal current_state, next_state : state_type; @@ -111,27 +109,26 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal reply_point_lock, next_point_lock : std_logic; - signal comb_REPLY_muxed_DATAREADY : std_logic; - signal comb_REPLY_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal reply_arbiter_CLK_EN : std_logic; - signal init_arbiter_CLK_EN : std_logic; - signal init_arbiter_ENABLE : std_logic; - signal init_arbiter_read_out : std_logic_vector(POINT_NUMBER-1 downto 0); - signal init_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); - - signal INIT_muxed_DATAREADY : std_logic; - signal INIT_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal INIT_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal INIT_muxed_READ : std_logic; - signal comb_INIT_next_read : std_logic; - signal reply_fsm_state : std_logic; - - signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic; - signal reset_i : std_logic; - attribute syn_keep : boolean; - attribute syn_keep of reset_i : signal is true; + signal comb_REPLY_muxed_DATAREADY : std_logic; + signal comb_REPLY_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal reply_arbiter_CLK_EN : std_logic; + signal init_arbiter_CLK_EN : std_logic; + signal init_arbiter_ENABLE : std_logic; + signal init_arbiter_read_out : std_logic_vector(POINT_NUMBER-1 downto 0); + signal init_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); + + signal INIT_muxed_DATAREADY : std_logic; + signal INIT_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal INIT_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal INIT_muxed_READ : std_logic; + signal comb_INIT_next_read : std_logic; + signal reply_fsm_state : std_logic; + + signal waiting_for_init_finish : std_logic; + signal next_waiting_for_init_finish : std_logic; + signal reset_i : std_logic; signal reply_dataready_in_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); signal reply_data_in_i : std_logic_vector(c_DATA_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0'); @@ -144,12 +141,19 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0); signal timeout_found : std_logic; - signal reg_CTRL_TIMEOUT_TIME : std_logic_vector(3 downto 0); + signal reg_CTRL_TIMEOUT_TIME : unsigned(15 downto 0); signal timer_us_tick : std_logic; signal timer_ms_tick : std_logic; signal last_locked : std_logic; + attribute HGROUP : string; + attribute syn_keep : boolean; + + attribute HGROUP of trb_net16_hub_logic_arch : architecture is "HUBLOGIC_group"; + attribute syn_keep of reset_i : signal is true; + + begin @@ -281,7 +285,7 @@ begin if rising_edge(CLK) then if reset_i = '1' or INIT_POOL_READ = '1' then init_has_read_from_pool(i) <= '0'; - elsif INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then + elsif (INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1') or MII_IS_UPLINK_ONLY(i) = c_YES then init_has_read_from_pool(i) <= '1'; end if; end if; @@ -515,7 +519,13 @@ begin if reset_i = '1' or send_reply_trm = '1' or locked = '0' then got_trm <= (others => '0'); else - got_trm <= got_trm or locking_point or reading_trmF2 or not real_activepoints or connection_timed_out; + for i in 0 to POINT_NUMBER-1 loop + if MII_IS_UPLINK_ONLY(i) = c_NO then + got_trm(i) <= got_trm(i) or locking_point(i) or reading_trmF2(i) or not real_activepoints(i) or connection_timed_out(i); + else + got_trm(i) <= '1'; + end if; + end loop; end if; end if; end process; @@ -534,18 +544,41 @@ begin --Check for Timeouts ---------------------------------- + proc_reg_setting : process (CLK) + begin + if rising_edge(CLK) then + reg_CTRL_TIMEOUT_TIME <= unsigned(CTRL_TIMEOUT_TIME); + timeout_found <= or_all(connection_timed_out); + end if; + end process; + +-- proc_timeout_counters : process (CLK) +-- begin +-- if rising_edge(CLK) then +-- reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME; +-- connection_timed_out(i) <= '0'; +-- timeout_found <= or_all(connection_timed_out); +-- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then +-- timeout_counter(i) <= (others => '0'); +-- elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(3 downto 0)))+1) = '1' then +-- connection_timed_out(i) <= '1'; +-- elsif timer_ms_tick = '1' and got_trm(i) = '0' then +-- timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); +-- end if; +-- end if; +-- end process; + gen_timeout_counters : for i in 0 to POINT_NUMBER-1 generate - proc_timeout_counters : process (CLK) + proc_ack_timeout_counters : process (CLK) begin if rising_edge(CLK) then - reg_CTRL_TIMEOUT_TIME <= CTRL_TIMEOUT_TIME; connection_timed_out(i) <= '0'; - timeout_found <= or_all(connection_timed_out); - if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then + if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' + or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = 0 then timeout_counter(i) <= (others => '0'); - elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1'))) = '1' then + elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then connection_timed_out(i) <= '1'; - elsif timer_ms_tick = '1' and got_trm(i) = '0' then + elsif timer_ms_tick = '1' and REPLY_POOL_next_read = '1' and got_trm(i) = '0' then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); end if; end if; diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd index 29b43a8..5cd947e 100644 --- a/trb_net16_hub_streaming_port.vhd +++ b/trb_net16_hub_streaming_port.vhd @@ -33,7 +33,8 @@ entity trb_net16_hub_streaming_port is MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); - MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES) + MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) ); port( @@ -238,6 +239,7 @@ begin MII_IBUF_DEPTH => MII_IBUF_DEPTH, MII_IS_UPLINK => MII_IS_UPLINK, MII_IS_DOWNLINK => MII_IS_DOWNLINK, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, INIT_ENDPOINT_ID => INIT_ENDPOINT_ID, INT_NUMBER => 3, INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0) diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index e12f245..5cf6ff5 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -19,30 +19,30 @@ entity trb_net16_io_multiplexer is CLK_EN : in std_logic; -- Media direction port - MED_DATAREADY_IN : in STD_LOGIC; - MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out STD_LOGIC; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; - MED_DATAREADY_OUT : out STD_LOGIC; - MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in STD_LOGIC; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATA_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN : in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN : in std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -- Status and control port - CTRL : in STD_LOGIC_VECTOR (31 downto 0); - STAT : out STD_LOGIC_VECTOR (31 downto 0) + CTRL : in std_logic_vector (31 downto 0); + STAT : out std_logic_vector (31 downto 0) ); end trb_net16_io_multiplexer; diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index b493ef6..3bc038e 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -213,9 +213,10 @@ begin CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer, STAT_DEBUG => STAT_INIT_OBUF_DEBUG ); - INT_INIT_READ_OUT <= '0'; + INT_INIT_READ_OUT <= '1'; end generate; gen_INITOBUF4 : if USE_ACKNOWLEDGE = 0 generate + INT_INIT_READ_OUT <= '1'; MED_INIT_DATAREADY_OUT <= '0'; MED_INIT_DATA_OUT <= (others => '0'); MED_INIT_PACKET_NUM_OUT <= (others => '0'); @@ -267,9 +268,10 @@ begin --CTRL_SETTINGS => CTRL_OBUF_settings(31 downto 16), STAT_DEBUG => STAT_REPLY_OBUF_DEBUG ); - INT_REPLY_READ_OUT <= '0'; + INT_REPLY_READ_OUT <= '1'; end generate; gen_REPLYOBUF4 : if USE_ACKNOWLEDGE = 0 generate + INT_REPLY_READ_OUT <= '1'; MED_REPLY_DATAREADY_OUT <= '0'; MED_REPLY_DATA_OUT <= (others => '0'); MED_REPLY_PACKET_NUM_OUT <= (others => '0'); diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 1a45330..c504bb1 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -69,7 +69,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal CURRENT_DATA_COUNT : unsigned (DATA_COUNT_WIDTH-1 downto 0); signal max_DATA_COUNT_minus_one : unsigned (DATA_COUNT_WIDTH-1 downto 0); signal TRANSMITTED_BUFFERS : unsigned (1 downto 0); - signal inc_TRANSMITTED_BUFFERS : std_logic; + signal inc_TRANSMITTED_BUFFERS : std_logic; signal decrease_TRANSMITTED_BUFFERS : std_logic; signal SEND_BUFFER_SIZE_IN : std_logic_vector (3 downto 0); @@ -87,7 +87,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal sending_state : sending_state_t; signal reset_DATA_COUNT : std_logic; - signal inc_DATA_COUNT : std_logic; + signal inc_DATA_COUNT : std_logic; signal CRC_RESET : std_logic; signal CRC_enable : std_logic; @@ -110,6 +110,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal timer_tick : std_logic; signal reset_transmitted_buffers : std_logic; + signal current_timeout_value : unsigned(15 downto 0); attribute syn_preserve : boolean; attribute syn_keep : boolean; @@ -504,10 +505,34 @@ begin --------------------------------------------------------------------- -- measure time waiting for two ACK - if too long, set error flag --------------------------------------------------------------------- +-- proc_reg_setting : process (CLK) +-- begin +-- if rising_edge(CLK) then +-- wait_for_ack_max_bit <= CTRL_SETTINGS(2 downto 0); +-- timer_tick <= TIMER_TICKS_IN(1); +-- end if; +-- end process; + +-- proc_ack_timeout_counters : process (CLK) +-- begin +-- if rising_edge(CLK) then +-- wait_for_ack_timeout <= '0'; +-- reset_transmitted_buffers <= '0'; +-- if TRANSMITTED_BUFFERS(1) = '0' or wait_for_ack_max_bit = "000" or wait_for_ack_max_bit = "111" then +-- wait_for_ack_counter <= (0 => '1', others => '0'); +-- elsif wait_for_ack_counter(to_integer(unsigned(wait_for_ack_max_bit&'1'))) = '1' then +-- wait_for_ack_timeout <= '1'; +-- reset_transmitted_buffers <= '1'; +-- elsif timer_tick = '1' then +-- wait_for_ack_counter <= wait_for_ack_counter + to_unsigned(1,1); +-- end if; +-- end if; +-- end process; + proc_reg_setting : process (CLK) begin if rising_edge(CLK) then - wait_for_ack_max_bit <= CTRL_SETTINGS(2 downto 0); + current_timeout_value <= unsigned(CTRL_SETTINGS(15 downto 0)); timer_tick <= TIMER_TICKS_IN(1); end if; end process; @@ -517,9 +542,11 @@ begin if rising_edge(CLK) then wait_for_ack_timeout <= '0'; reset_transmitted_buffers <= '0'; - if TRANSMITTED_BUFFERS(1) = '0' or wait_for_ack_max_bit = "000" or wait_for_ack_max_bit = "111" then - wait_for_ack_counter <= (0 => '1', others => '0'); - elsif wait_for_ack_counter(to_integer(unsigned(wait_for_ack_max_bit&'1'))) = '1' then + if current_timeout_value = 0 then + wait_for_ack_counter <= (others => '0'); + elsif TRANSMITTED_BUFFERS(1) = '0' then + wait_for_ack_counter <= (1 => '1', others => '0'); + elsif wait_for_ack_counter = current_timeout_value then wait_for_ack_timeout <= '1'; reset_transmitted_buffers <= '1'; elsif timer_tick = '1' then @@ -528,6 +555,7 @@ begin end if; end process; + --------------------------------------------------------------------- -- Debug output --------------------------------------------------------------------- diff --git a/trb_net16_rx_packets.vhd b/trb_net16_rx_packets.vhd index f486659..a585c00 100755 --- a/trb_net16_rx_packets.vhd +++ b/trb_net16_rx_packets.vhd @@ -411,12 +411,12 @@ toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0'; ---------------------------------------------------------------------- -- Debug signals ---------------------------------------------------------------------- -debug(15) <= toc_done; -debug(14) <= ce_toc; -debug(13) <= rst_toc; -debug(12) <= fifo_rst; -debug(11 downto 9) <= (others => '0'); -debug(8 downto 0) <= fifo_rcnt_stdlv; +debug(15 downto 13) <= (others => '0'); +debug(12 downto 4) <= fifo_rcnt_stdlv; +debug(3) <= toc_done; +debug(2) <= ce_toc; +debug(1) <= rst_toc; +debug(0) <= fifo_rst; --debug(15 downto 8) <= fifo_rcnt_stdlv(7 downto 0); --debug(7 downto 2) <= (others => '0'); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 6d4607a..df75e12 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -977,44 +977,50 @@ end component trb_net16_med_scm_sfp_gbe; component handler_lvl1 is generic( TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES - ); - port( - RESET : in std_logic; - CLOCK : in std_logic; - --Timing Trigger - LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics - LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger - --LVL1_handler connection - LVL1_TRG_RECEIVED_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS - LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS - - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release - LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter - LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter - - --FEE logic / Data Handler - LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid - LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received - LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received - LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) - LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected - LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); - - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE - LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE - - --Stat/Control - STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers - TRG_ENABLE_IN : in std_logic; -- trigger enable flag - TRG_INVERT_IN : in std_logic; -- trigger invert flag - --Debug - DEBUG_OUT : out std_logic_vector (15 downto 0) - ); + ); + port( + RESET : in std_logic; + RESET_STATS_IN : in std_logic; + CLOCK : in std_logic; + --Timing Trigger + LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics + LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS + LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS + + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release + LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter + LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected + LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); + LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10 + LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10 + LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10 + SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10 + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE + LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE + + --Stat/Control + STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers + TRG_ENABLE_IN : in std_logic; -- trigger enable flag + TRG_INVERT_IN : in std_logic; -- trigger invert flag + COUNTERS_STATUS_OUT : out std_logic_vector (63 downto 0); + --Debug + DEBUG_OUT : out std_logic_vector (15 downto 0) + ); end component; @@ -1612,9 +1618,10 @@ end component; SD : in std_logic_vector(3 downto 0); -- Status and control port - STAT_OP : out std_logic_vector (63 downto 0); + STAT_OP : out std_logic_vector (63 downto 0); CTRL_OP : in std_logic_vector (63 downto 0); - STAT_DEBUG : out std_logic_vector (255 downto 0); + STAT_REG_OUT : out std_logic_vector (511 downto 0); + STAT_DEBUG : out std_logic_vector (255 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) ); end component; @@ -2350,7 +2357,8 @@ end component; PACKET_TIMEOUT_OUT : out std_logic; ENABLE_CORRECTION_IN : in std_logic; -- Debugging - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -2837,7 +2845,8 @@ end component; SEND_LINK_RESET_IN : in std_logic; TX_ALLOW_IN : in std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) ); end component; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index ad01ab4..b89763a 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -111,7 +111,7 @@ package trb_net_std is --common registers --maximum: 4, because of regio implementation - constant std_COMSTATREG : integer := 5; + constant std_COMSTATREG : integer := 8; constant std_COMCTRLREG : integer := 3; --needed address width for common registers constant std_COMneededwidth : integer := 3; -- 2.43.0