From fc6c597375b8f1fd7ed7f975e085e25d1101ed2d Mon Sep 17 00:00:00 2001 From: hadaq Date: Fri, 4 Nov 2011 15:10:06 +0000 Subject: [PATCH] *** empty log message *** --- tdc_test/compile_periph_synonly.pl | 155 ++++++++ tdc_test/trb3_periph.lpf | 324 ++++++++++++++++ tdc_test/trb3_periph.p2t | 20 + tdc_test/trb3_periph.prj | 155 ++++++++ tdc_test/trb3_periph.vhd | 582 +++++++++++++++++++++++++++++ 5 files changed, 1236 insertions(+) create mode 100755 tdc_test/compile_periph_synonly.pl create mode 100644 tdc_test/trb3_periph.lpf create mode 100644 tdc_test/trb3_periph.p2t create mode 100644 tdc_test/trb3_periph.prj create mode 100644 tdc_test/trb3_periph.vhd diff --git a/tdc_test/compile_periph_synonly.pl b/tdc_test/compile_periph_synonly.pl new file mode 100755 index 0000000..99c0314 --- /dev/null +++ b/tdc_test/compile_periph_synonly.pl @@ -0,0 +1,155 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $BasePath = "../base/"; #path to "base" directory +my $lattice_path = '/opt/lattice/diamond/1.3'; +my $synplify_path = '/opt/synplicity/fpga_e201103'; +my $lm_license_file_for_synplify = "27000\@localhost"; +my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; +################################################################################### + + + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +#$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +#execute($c); + +#my $tpmap = $TOPNAME . "_map" ; + +#$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +#execute($c); + + +#system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#execute($c); + +## IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +## TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/tdc_test/trb3_periph.lpf b/tdc_test/trb3_periph.lpf new file mode 100644 index 0000000..37f910c --- /dev/null +++ b/tdc_test/trb3_periph.lpf @@ -0,0 +1,324 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 2.5; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; + +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Trigger I/O +################################################################# + +#Trigger from fan-out +LOCATE COMP "TRIGGER_LEFT" SITE "V3"; +LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; +IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + +################################################################# +# To central FPGA +################################################################# + +LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; +LOCATE COMP "FPGA5_COMM_10" SITE "V10"; +LOCATE COMP "FPGA5_COMM_11" SITE "W10"; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5"; +LOCATE COMP "TEST_LINE_1" SITE "A6"; +LOCATE COMP "TEST_LINE_2" SITE "G8"; +LOCATE COMP "TEST_LINE_3" SITE "F9"; +LOCATE COMP "TEST_LINE_4" SITE "D9"; +LOCATE COMP "TEST_LINE_5" SITE "D10"; +LOCATE COMP "TEST_LINE_6" SITE "F10"; +LOCATE COMP "TEST_LINE_7" SITE "E10"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "G10"; +LOCATE COMP "TEST_LINE_11" SITE "G9"; +LOCATE COMP "TEST_LINE_12" SITE "C9"; +LOCATE COMP "TEST_LINE_13" SITE "C10"; +LOCATE COMP "TEST_LINE_14" SITE "H10"; +LOCATE COMP "TEST_LINE_15" SITE "H11"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; + +################################################################# +# Connection to AddOn +################################################################# +#All DQ groups from one bank are grouped. +#All DQS are inserted in the DQ lines at position 6 and 7 +#DQ 6-9 are shifted to 8-11 +#Order per bank is kept, i.e. adjacent numbers have adjacent pins +#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10. +#even numbers are positive LVDS line, odd numbers are negative LVDS line +#DQUL can be switched to 1.8V + +LOCATE COMP "DQLL_0" SITE "P1"; #DQLL0_0 #1 +LOCATE COMP "DQLL_1" SITE "P2"; #DQLL0_1 #3 +LOCATE COMP "DQLL_2" SITE "T2"; #DQLL0_2 #5 +LOCATE COMP "DQLL_3" SITE "U3"; #DQLL0_3 #7 +LOCATE COMP "DQLL_4" SITE "R1"; #DQLL0_4 #9 +LOCATE COMP "DQLL_5" SITE "R2"; #DQLL0_5 #11 +LOCATE COMP "DQLL_6" SITE "N3"; #DQSLL0_T #13 +LOCATE COMP "DQLL_7" SITE "P3"; #DQSLL0_C #15 +LOCATE COMP "DQLL_8" SITE "P5"; #DQLL0_6 #17 +LOCATE COMP "DQLL_9" SITE "P6"; #DQLL0_7 #19 +LOCATE COMP "DQLL_10" SITE "N5"; #DQLL0_8 #21 +LOCATE COMP "DQLL_11" SITE "N6"; #DQLL0_9 #23 + +LOCATE COMP "DQLL_12" SITE "V1"; #DQLL1_0 #26 +LOCATE COMP "DQLL_13" SITE "U2"; #DQLL1_1 #28 +LOCATE COMP "DQLL_14" SITE "T1"; #DQLL1_2 #30 +LOCATE COMP "DQLL_15" SITE "U1"; #DQLL1_3 #32 +LOCATE COMP "DQLL_16" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "DQLL_17" SITE "R3"; #DQLL1_5 #36 +LOCATE COMP "DQLL_18" SITE "T3"; #DQSLL1_T #38 +LOCATE COMP "DQLL_19" SITE "R4"; #DQSLL1_C #40 +LOCATE COMP "DQLL_20" SITE "R5"; #DQLL1_6 #42 +LOCATE COMP "DQLL_21" SITE "R6"; #DQLL1_7 #44 +LOCATE COMP "DQLL_22" SITE "T7"; #DQLL1_8 #46 +LOCATE COMP "DQLL_23" SITE "T8"; #DQLL1_9 #48 + +LOCATE COMP "DQLL_24" SITE "AC2"; #DQLL2_0 #25 +LOCATE COMP "DQLL_25" SITE "AC3"; #DQLL2_1 #27 +LOCATE COMP "DQLL_26" SITE "AB1"; #DQLL2_2 #29 +LOCATE COMP "DQLL_27" SITE "AC1"; #DQLL2_3 #31 +LOCATE COMP "DQLL_28" SITE "AA1"; #DQLL2_4 #33 +LOCATE COMP "DQLL_29" SITE "AA2"; #DQLL2_5 #35 +LOCATE COMP "DQLL_30" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "DQLL_31" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 +LOCATE COMP "DQLL_32" SITE "Y5"; #DQLL2_6 #41 +LOCATE COMP "DQLL_33" SITE "AA5"; #DQLL2_7 #43 +LOCATE COMP "DQLL_34" SITE "V6"; #DQLL2_8 #45 +LOCATE COMP "DQLL_35" SITE "V7"; #DQLL2_9 #47 + +LOCATE COMP "DQLL_36" SITE "AD1"; #DQLL3_0 #2 +LOCATE COMP "DQLL_37" SITE "AD2"; #DQLL3_1 #4 +LOCATE COMP "DQLL_38" SITE "AB5"; #DQLL3_2 #6 +LOCATE COMP "DQLL_39" SITE "AB6"; #DQLL3_3 #8 +LOCATE COMP "DQLL_40" SITE "AB3"; #DQLL3_4 #10 +LOCATE COMP "DQLL_41" SITE "AB4"; #DQLL3_5 #12 +LOCATE COMP "DQLL_42" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 +LOCATE COMP "DQLL_43" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "DQLL_44" SITE "AA3"; #DQLL3_6 #18 +LOCATE COMP "DQLL_45" SITE "AA4"; #DQLL3_7 #20 +LOCATE COMP "DQLL_46" SITE "W8"; #DQLL3_8 #22 +LOCATE COMP "DQLL_47" SITE "W9"; #DQLL3_9 #24 + +LOCATE COMP "DQLR_0" SITE "AC26"; #DQLR0_0 #129 +LOCATE COMP "DQLR_1" SITE "AC25"; #DQLR0_1 #131 +LOCATE COMP "DQLR_2" SITE "Y19"; #DQLR0_2 #133 +LOCATE COMP "DQLR_3" SITE "Y20"; #DQLR0_3 #135 +LOCATE COMP "DQLR_4" SITE "AB24"; #DQLR0_4 #137 +LOCATE COMP "DQLR_5" SITE "AC24"; #DQLR0_5 #139 +LOCATE COMP "DQLR_6" SITE "Y22"; #DQSLR0_T #141 +LOCATE COMP "DQLR_7" SITE "AA22"; #DQSLR0_C #143 +LOCATE COMP "DQLR_8" SITE "AD24"; #DQLR0_6 #145 +LOCATE COMP "DQLR_9" SITE "AE24"; #DQLR0_7 #147 +LOCATE COMP "DQLR_10" SITE "AE25"; #DQLR0_8 #149 +LOCATE COMP "DQLR_11" SITE "AF24"; #DQLR0_9 #151 + +LOCATE COMP "DQLR_12" SITE "W23"; #DQLR1_0 #169 +LOCATE COMP "DQLR_13" SITE "W22"; #DQLR1_1 #171 +LOCATE COMP "DQLR_14" SITE "AA25"; #DQLR1_2 #173 +LOCATE COMP "DQLR_15" SITE "Y24"; #DQLR1_3 #175 +LOCATE COMP "DQLR_16" SITE "AA26"; #DQLR1_4 #177 +LOCATE COMP "DQLR_17" SITE "AB26"; #DQLR1_5 #179 +LOCATE COMP "DQLR_18" SITE "W21"; #DQSLR1_T #181 +LOCATE COMP "DQLR_19" SITE "W20"; #DQSLR1_C #183 +LOCATE COMP "DQLR_20" SITE "AA24"; #DQLR1_6 #185 +LOCATE COMP "DQLR_21" SITE "AA23"; #DQLR1_7 #187 +LOCATE COMP "DQLR_22" SITE "AD26"; #DQLR1_8 #189 +LOCATE COMP "DQLR_23" SITE "AD25"; #DQLR1_9 #191 + +LOCATE COMP "DQLR_24" SITE "R25"; #DQLR2_0 #170 +LOCATE COMP "DQLR_25" SITE "R26"; #DQLR2_1 #172 +LOCATE COMP "DQLR_26" SITE "T25"; #DQLR2_2 #174 +LOCATE COMP "DQLR_27" SITE "T24"; #DQLR2_3 #176 +LOCATE COMP "DQLR_28" SITE "T26"; #DQLR2_4 #178 +LOCATE COMP "DQLR_29" SITE "U26"; #DQLR2_5 #180 +LOCATE COMP "DQLR_30" SITE "V21"; #DQSLR2_T #182 +LOCATE COMP "DQLR_31" SITE "V22"; #DQSLR2_C #184 +LOCATE COMP "DQLR_32" SITE "U24"; #DQLR2_6 #186 +LOCATE COMP "DQLR_33" SITE "V24"; #DQLR2_7 #188 +LOCATE COMP "DQLR_34" SITE "U23"; #DQLR2_8 #190 +LOCATE COMP "DQLR_35" SITE "U22"; #DQLR2_9 #192 + +LOCATE COMP "DQUL_0" SITE "B2"; #DQUL0_0 #74 +LOCATE COMP "DQUL_1" SITE "B3"; #DQUL0_1 #76 +LOCATE COMP "DQUL_2" SITE "D4"; #DQUL0_2 #78 +LOCATE COMP "DQUL_3" SITE "E4"; #DQUL0_3 #80 +LOCATE COMP "DQUL_4" SITE "C3"; #DQUL0_4 #82 +LOCATE COMP "DQUL_5" SITE "D3"; #DQUL0_5 #84 +LOCATE COMP "DQUL_6" SITE "G5"; #DQSUL0_T #86 +LOCATE COMP "DQUL_7" SITE "G6"; #DQSUL0_C #88 +LOCATE COMP "DQUL_8" SITE "E3"; #DQUL0_6 #90 +LOCATE COMP "DQUL_9" SITE "F4"; #DQUL0_7 #92 +LOCATE COMP "DQUL_10" SITE "H6"; #DQUL0_8 #94 +LOCATE COMP "DQUL_11" SITE "J6"; #DQUL0_9 #96 + +LOCATE COMP "DQUL_12" SITE "G2"; #DQUL1_0 #73 +LOCATE COMP "DQUL_13" SITE "G3"; #DQUL1_1 #75 +LOCATE COMP "DQUL_14" SITE "F2"; #DQUL1_2 #77 +LOCATE COMP "DQUL_15" SITE "F3"; #DQUL1_3 #79 +LOCATE COMP "DQUL_16" SITE "C2"; #DQUL1_4 #81 +LOCATE COMP "DQUL_17" SITE "D2"; #DQUL1_5 #83 +LOCATE COMP "DQUL_18" SITE "K7"; #DQSUL1_T #85 +LOCATE COMP "DQUL_19" SITE "K6"; #DQSUL1_C #87 +LOCATE COMP "DQUL_20" SITE "H5"; #DQUL1_6 #89 +LOCATE COMP "DQUL_21" SITE "J5"; #DQUL1_7 #91 +LOCATE COMP "DQUL_22" SITE "K8"; #DQUL1_8 #93 +LOCATE COMP "DQUL_23" SITE "J7"; #DQUL1_9 #95 + +LOCATE COMP "DQUL_24" SITE "K2"; #DQUL2_0 #50 +LOCATE COMP "DQUL_25" SITE "K1"; #DQUL2_1 #52 +LOCATE COMP "DQUL_26" SITE "J4"; #DQUL2_2 #54 +LOCATE COMP "DQUL_27" SITE "J3"; #DQUL2_3 #56 +LOCATE COMP "DQUL_28" SITE "D1"; #DQUL2_4 #58 +LOCATE COMP "DQUL_29" SITE "C1"; #DQUL2_5 #60 +LOCATE COMP "DQUL_30" SITE "K4"; #DQSUL2_T #62 +LOCATE COMP "DQUL_31" SITE "K5"; #DQSUL2_C #64 +LOCATE COMP "DQUL_32" SITE "E1"; #DQUL2_6 #66 +LOCATE COMP "DQUL_33" SITE "F1"; #DQUL2_7 #68 +LOCATE COMP "DQUL_34" SITE "L5"; #DQUL2_8 #70 +LOCATE COMP "DQUL_35" SITE "L6"; #DQUL2_9 #72 + +LOCATE COMP "DQUL_36" SITE "H2"; #DQUL3_0 #49 +LOCATE COMP "DQUL_37" SITE "G1"; #DQUL3_1 #51 +LOCATE COMP "DQUL_38" SITE "K3"; #DQUL3_2 #53 +LOCATE COMP "DQUL_39" SITE "L3"; #DQUL3_3 #55 +LOCATE COMP "DQUL_40" SITE "H1"; #DQUL3_4 #57 +LOCATE COMP "DQUL_41" SITE "J1"; #DQUL3_5 #59 +LOCATE COMP "DQUL_42" SITE "M5"; #DQSUL3_T #61 +LOCATE COMP "DQUL_43" SITE "M6"; #DQSUL3_C #63 +LOCATE COMP "DQUL_44" SITE "L2"; #DQUL3_6 #65 +LOCATE COMP "DQUL_45" SITE "L1"; #DQUL3_7 #67 + + +LOCATE COMP "DQUR_0" SITE "J23"; #DQUR0_0 #105 +LOCATE COMP "DQUR_1" SITE "H23"; #DQUR0_1 #107 +LOCATE COMP "DQUR_2" SITE "G26"; #DQUR0_2 #109 +LOCATE COMP "DQUR_3" SITE "F26"; #DQUR0_3 #111 +LOCATE COMP "DQUR_4" SITE "H26"; #DQUR0_4 #113 +LOCATE COMP "DQUR_5" SITE "H25"; #DQUR0_5 #115 +LOCATE COMP "DQUR_6" SITE "F24"; #DQSUR0_T #117 +LOCATE COMP "DQUR_7" SITE "G24"; #DQSUR0_C #119 +LOCATE COMP "DQUR_8" SITE "K23"; #DQUR0_6 #121 +LOCATE COMP "DQUR_9" SITE "K22"; #DQUR0_7 #123 +# LOCATE COMP "DQUR_10" SITE "F25"; #DQUR0_8 #125 #input only +# LOCATE COMP "DQUR_11" SITE "E26"; #DQUR0_9 #127 #input only + +LOCATE COMP "DQUR_10" SITE "H24"; #DQUR1_0 #106 +LOCATE COMP "DQUR_11" SITE "G25"; #DQUR1_1 #108 +LOCATE COMP "DQUR_12" SITE "L20"; #DQUR1_2 #110 +LOCATE COMP "DQUR_13" SITE "M21"; #DQUR1_3 #112 +LOCATE COMP "DQUR_14" SITE "K24"; #DQUR1_4 #114 +LOCATE COMP "DQUR_15" SITE "J24"; #DQUR1_5 #116 +LOCATE COMP "DQUR_16" SITE "M23"; #DQSUR1_T #118 +LOCATE COMP "DQUR_17" SITE "M24"; #DQSUR1_C #120 +LOCATE COMP "DQUR_18" SITE "L24"; #DQUR1_6 #122 +LOCATE COMP "DQUR_19" SITE "K25"; #DQUR1_7 #124 +LOCATE COMP "DQUR_20" SITE "M22"; #DQUR1_8 #126 +LOCATE COMP "DQUR_21" SITE "N21"; #DQUR1_9 #128 +LOCATE COMP "DQUR_22" SITE "J26"; #DQUR2_0 #130 +LOCATE COMP "DQUR_23" SITE "K26"; #DQUR2_1 #132 +LOCATE COMP "DQUR_24" SITE "N23"; #DQUR2_2 #134 +LOCATE COMP "DQUR_25" SITE "N22"; #DQUR2_3 #136 +LOCATE COMP "DQUR_26" SITE "K19"; #DQUR2_4 #138 +LOCATE COMP "DQUR_27" SITE "L19"; #DQUR2_5 #140 +LOCATE COMP "DQUR_28" SITE "P23"; #DQSUR2_T #142 +LOCATE COMP "DQUR_29" SITE "R22"; #DQSUR2_C #144 +LOCATE COMP "DQUR_30" SITE "L25"; #DQUR2_6 #146 +LOCATE COMP "DQUR_31" SITE "L26"; #DQUR2_7 #148 +LOCATE COMP "DQUR_32" SITE "P21"; #DQUR2_8 #150 +LOCATE COMP "DQUR_33" SITE "P22"; #DQUR2_9 #152 + +DEFINE PORT GROUP "DQ_group" "DQ*" ; +IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +################################################################# +# Additional Lines to AddOn +################################################################# + +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 + +################################################################# +# Flash ROM and Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14"; +IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; diff --git a/tdc_test/trb3_periph.p2t b/tdc_test/trb3_periph.p2t new file mode 100644 index 0000000..c037b03 --- /dev/null +++ b/tdc_test/trb3_periph.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 12 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj new file mode 100644 index 0000000..c13e4fb --- /dev/null +++ b/tdc_test/trb3_periph.prj @@ -0,0 +1,155 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "./trb3_periph.vhd" + +add_file -vhdl -lib "work" "../source/TDC.vhd" +add_file -vhdl -lib "work" "../source/Adder_320.vhd" +add_file -vhdl -lib "work" "../source/Channel_320.vhd" +add_file -vhdl -lib "work" "../source/Encoder_320_Bit.vhd" +add_file -vhdl -lib "work" "../source/FIFO_32x512_NOreg.vhd" +add_file -vhdl -lib "work" "../source/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../source/bit_sync.vhd" +add_file -vhdl -lib "work" "../source/edge_to_pulse_fast.vhd" +add_file -vhdl -lib "work" "../source/up_counter.vhd" + + + + + + diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd new file mode 100644 index 0000000..7993618 --- /dev/null +++ b/tdc_test/trb3_periph.vhd @@ -0,0 +1,582 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + + + +entity trb3_periph is + port( + --Clocks + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + + --Trigger + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + + --Serdes + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + + --Inter-FPGA Communication + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined + --Connection to AddOn + SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only + DQUL : inout std_logic_vector(45 downto 0); + DQLL : inout std_logic_vector(47 downto 0); + DQUR : inout std_logic_vector(33 downto 0); + DQLR : inout std_logic_vector(35 downto 0); + --All DQ groups from one bank are grouped. + --All DQS are inserted in the DQ lines at position 6 and 7, DQ 6-9 are shifted to 8-11 + --Order per bank is kept, i.e. adjacent numbers have adjacent pins + --all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. + --even numbers are positive LVDS line, odd numbers are negative LVDS line + --DQUL can be switched to 1.8V + --Flash ROM & Reboot + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + + --Misc + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of DQLL : signal is true; + attribute syn_useioff of DQUL : signal is true; + attribute syn_useioff of DQLR : signal is true; + attribute syn_useioff of DQUR : signal is true; + attribute syn_useioff of SPARE_LINE : signal is true; + + +end entity; + +architecture trb3_periph_arch of trb3_periph is + --Constants + constant REGIO_NUM_STAT_REGS : integer := 2; + constant REGIO_NUM_CTRL_REGS : integer := 2; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + --Clock / Reset + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --Media Interface + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + + --FPGA Test + signal time_counter : unsigned(31 downto 0); + + --TDC component + component TDC + generic ( + CHANNEL_NUMBER : integer range 0 to 64); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRIGGER_IN : in std_logic; + TRIGGER_WIN_IN : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + TRB_WR_CLK_OUT : out std_logic; + DATA_VALID_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + READY_OUT : out std_logic; + TDC_DEBUG_00 : out std_logic_vector(31 downto 0)); + end component; + +begin +--------------------------------------------------------------------------- +-- Reset Generation +--------------------------------------------------------------------------- + + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + + +--------------------------------------------------------------------------- +-- Clock Handling +--------------------------------------------------------------------------- + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_LEFT, --CLK_GPLL_RIGHT + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + + +--------------------------------------------------------------------------- +-- The TrbNet media interface (to other FPGA) +--------------------------------------------------------------------------- + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES --run on 200 MHz clock + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler + generic map( + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"45", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"91000001", + REGIO_INIT_ADDRESS => x"f300", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 125, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open + ); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- + DQLL <= (others => '0'); + DQUL <= (others => '0'); + DQLR <= (others => '0'); + DQUR <= (others => '0'); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- SPI / Flash +--------------------------------------------------------------------------- + + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + +-- data memory for SPI accesses + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + +--------------------------------------------------------------------------- +-- Reboot FPGA +--------------------------------------------------------------------------- + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not time_counter(26); + LED_YELLOW <= not med_stat_op(11); + + +--------------------------------------------------------------------------- +-- Test Connector +--------------------------------------------------------------------------- + TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); + TEST_LINE(8) <= med_dataready_in; + TEST_LINE(9) <= med_dataready_out; + TEST_LINE(10) <= stat_reg_strobe(0); + TEST_LINE(15 downto 11) <= (others => '0'); + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process + begin + wait until rising_edge(clk_100_i); + time_counter <= time_counter + 1; + end process; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 8) -- Number of TDC channels + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + HIT_IN => DQUL(7 downto 0), -- Channel start signals + TRIGGER_IN => trg_timing_valid_i, -- Readout trigger + TRIGGER_WIN_IN => x"00640000", -- Trigger window register relative to + -- the trigger (post edge & pre edge) + DATA_OUT => fee_data_i, -- Data to readout + TRB_WR_CLK_OUT => open, -- Readout clk (maybe not necessary + -- in trb3) + DATA_VALID_OUT => fee_data_write_i, -- Data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- Readout finished signal + READY_OUT => fee_trg_release_i, -- Ready for the next trigger + TDC_DEBUG_00 => open); -- Debug + +end architecture; -- 2.43.0