From fc742e07d9e774e4c06f21f996a6b23377a44bf9 Mon Sep 17 00:00:00 2001 From: hadaq Date: Fri, 28 Oct 2011 15:27:50 +0000 Subject: [PATCH] TDC source files added to the project --- base/trb3_periph.prj | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj index 7aab393..c475fce 100644 --- a/base/trb3_periph.prj +++ b/base/trb3_periph.prj @@ -138,6 +138,19 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "./trb3_periph.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/TDC.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/Adder_320.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/Channel_320.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/Encoder_320_Bit.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/FIFO_32x512_Oreg.vhd" +add_file -vhdl -lib "work" "../base/tdc_source_files/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../base/cores/bit_sync.vhd" +add_file -vhdl -lib "work" "../base/cores/edge_to_pulse_fast.vhd" +add_file -vhdl -lib "work" "../base/cores/f_divider.vhd" +add_file -vhdl -lib "work" "../base/cores/signal_sync.vhd" +add_file -vhdl -lib "work" "../base/cores/up_counter.vhd" + + -- 2.43.0