From fce18658e55467bcc54cc9c47b802d706f0cf64a Mon Sep 17 00:00:00 2001 From: Rene Hagdorn Date: Thu, 26 Apr 2018 18:10:36 +0200 Subject: [PATCH] Changed connections to/from Generator, 'declocked' DataSelector --- mupix/Mupix8/sources/DatasourceSelector.vhd | 79 +++++++++++---------- mupix/Mupix8/sources/FrameGenMux2.vhd | 55 +++++++------- mupix/Mupix8/sources/MupixBoard.vhd | 32 +++++---- 3 files changed, 88 insertions(+), 78 deletions(-) diff --git a/mupix/Mupix8/sources/DatasourceSelector.vhd b/mupix/Mupix8/sources/DatasourceSelector.vhd index f3be680..7d13510 100644 --- a/mupix/Mupix8/sources/DatasourceSelector.vhd +++ b/mupix/Mupix8/sources/DatasourceSelector.vhd @@ -22,6 +22,7 @@ entity DataSel is fg3in : in std_logic_vector(WIDTH - 1 downto 0); fg_full : in std_logic_vector(3 downto 0); fg_empty : in std_logic_vector(3 downto 0); + fg_rden : out std_logic_vector(3 downto 0); -- SerDes Data serdes0 : in std_logic_vector(WIDTH - 1 downto 0); @@ -30,6 +31,7 @@ entity DataSel is serdes3 : in std_logic_vector(WIDTH - 1 downto 0); sd_full : in std_logic_vector(3 downto 0); sd_empty : in std_logic_vector(3 downto 0); + sd_rden : out std_logic_vector(3 downto 0); sel : in std_logic; -- Selects FrameGen clk : in std_logic; @@ -39,6 +41,7 @@ entity DataSel is out_data1 : out std_logic_vector(WIDTH - 1 downto 0); out_data2 : out std_logic_vector(WIDTH - 1 downto 0); out_data3 : out std_logic_vector(WIDTH - 1 downto 0); + fifo_rdenx: in std_logic_vector(3 downto 0); fifo_full : out std_logic_vector(3 downto 0); fifo_empty: out std_logic_vector(3 downto 0) ); @@ -48,43 +51,47 @@ architecture Behavioral of DataSel is begin - Dsel: process (clk, sel) + Dsel: process (rst, sel) begin - if rising_edge(clk) then - if rst = '1' then - out_data0 <= (others => '0'); - out_data1 <= (others => '0'); - out_data2 <= (others => '0'); - out_data3 <= (others => '0'); - else - case sel is - - when '1' => -- FrameGen Data - out_data0 <= fg0in; - out_data1 <= fg1in; - out_data2 <= fg2in; - out_data3 <= fg3in; - fifo_full <= fg_full; - fifo_empty <= fg_empty; - - when '0' => -- SerDes Data - out_data0 <= serdes0; - out_data1 <= serdes1; - out_data2 <= serdes2; - out_data3 <= serdes3; - fifo_full <= sd_full; - fifo_empty <= sd_empty; - - when others => - out_data0 <= (others => '0'); - out_data1 <= (others => '0'); - out_data2 <= (others => '0'); - out_data3 <= (others => '0'); - fifo_full <= (others => '0'); - fifo_empty <= (others => '0'); - - end case; - end if; + if rst = '1' then + out_data0 <= (others => '0'); + out_data1 <= (others => '0'); + out_data2 <= (others => '0'); + out_data3 <= (others => '0'); + fifo_full <= (others => '0'); + fifo_empty <= (others => '0'); + fg_rden <= (others => '0'); + sd_rden <= (others => '0'); + else + case sel is + when '1' => -- FrameGen Data + out_data0 <= fg0in; + out_data1 <= fg1in; + out_data2 <= fg2in; + out_data3 <= fg3in; + fifo_full <= fg_full; + fifo_empty <= fg_empty; + fg_rden <= fifo_rdenx; + sd_rden <= (others => '0'); + when '0' => -- SerDes Data + out_data0 <= serdes0; + out_data1 <= serdes1; + out_data2 <= serdes2; + out_data3 <= serdes3; + fifo_full <= sd_full; + fifo_empty <= sd_empty; + fg_rden <= (others => '0'); + sd_rden <= fifo_rdenx; + when others => + out_data0 <= (others => '0'); + out_data1 <= (others => '0'); + out_data2 <= (others => '0'); + out_data3 <= (others => '0'); + fifo_full <= (others => '0'); + fifo_empty <= (others => '0'); + fg_rden <= (others => '0'); + sd_rden <= (others => '0'); + end case; end if; end process Dsel; diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGenMux2.vhd index 7d6ff39..37fcf8f 100644 --- a/mupix/Mupix8/sources/FrameGenMux2.vhd +++ b/mupix/Mupix8/sources/FrameGenMux2.vhd @@ -22,6 +22,7 @@ entity FrameGeneratorMux is serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); serdes_fifo_full : in std_logic_vector(3 downto 0); serdes_fifo_empty : in std_logic_vector(3 downto 0); + in_rden : in std_logic_vector(3 downto 0); serdes_fifo_rden : out std_logic_vector(3 downto 0); out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); out_fifo_full : out std_logic_vector(3 downto 0); @@ -86,7 +87,8 @@ component DataSel is fg3in : in std_logic_vector(WIDTH - 1 downto 0); fg_full : in std_logic_vector(3 downto 0); fg_empty : in std_logic_vector(3 downto 0); - + fg_rden : out std_logic_vector(3 downto 0); + -- SerDes Data serdes0 : in std_logic_vector(WIDTH - 1 downto 0); serdes1 : in std_logic_vector(WIDTH - 1 downto 0); @@ -94,15 +96,17 @@ component DataSel is serdes3 : in std_logic_vector(WIDTH - 1 downto 0); sd_full : in std_logic_vector(3 downto 0); sd_empty : in std_logic_vector(3 downto 0); - + sd_rden : out std_logic_vector(3 downto 0); + sel : in std_logic; -- Selects FrameGen clk : in std_logic; rst : in std_logic; - + out_data0 : out std_logic_vector(WIDTH - 1 downto 0); out_data1 : out std_logic_vector(WIDTH - 1 downto 0); out_data2 : out std_logic_vector(WIDTH - 1 downto 0); out_data3 : out std_logic_vector(WIDTH - 1 downto 0); + fifo_rdenx: in std_logic_vector(3 downto 0); fifo_full : out std_logic_vector(3 downto 0); fifo_empty: out std_logic_vector(3 downto 0) ); @@ -130,8 +134,6 @@ signal fifo_ef : std_logic_vector(3 downto 0); -- Internal signals: Datasource Selector signal mux_sel : std_logic := '0'; -signal sd_fifo_rden : std_logic_vector(3 downto 0); - begin -- Behavioral Frame_Generator: for J in 0 to 3 generate @@ -182,31 +184,30 @@ begin -- Behavioral fg3in => fifo_data(3), fg_full => fifo_ff, fg_empty => fifo_ef, + fg_rden => fifo_rden, serdes0 => serdes_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH), serdes1 => serdes_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH), serdes2 => serdes_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH), serdes3 => serdes_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH), sd_full => serdes_fifo_full, sd_empty => serdes_fifo_empty, + sd_rden => serdes_fifo_rden, out_data0 => out_data(1*DATAWIDTH - 1 downto 0*DATAWIDTH), out_data1 => out_data(2*DATAWIDTH - 1 downto 1*DATAWIDTH), out_data2 => out_data(3*DATAWIDTH - 1 downto 2*DATAWIDTH), out_data3 => out_data(4*DATAWIDTH - 1 downto 3*DATAWIDTH), fifo_full => out_fifo_full, - fifo_empty => out_fifo_empty + fifo_empty => out_fifo_empty, + fifo_rdenx => in_rden ); - serdes_fifo_rden <= sd_fifo_rden; - ---------------------------------------------------------------------------------- -- TRB Slave Bus --- 0x0140: start pseudo data generator (writes data to fifo) --- 0x0141: number of datawords per block --- 0x0142: pause between words --- 0x0143: downtime between blocks --- 0x0144: start DataGen fifo readout --- 0x0145: start SerDes fifo readout --- 0x0146: select data source (0 for MuPix data, 1 for pseudo data) +-- 0x0100: start pseudo data generator (writes data to fifo) +-- 0x0101: number of datawords per block +-- 0x0102: pause between words +-- 0x0103: downtime between blocks +-- 0x0105: select data source (0 for MuPix data, 1 for pseudo data) ---------------------------------------------------------------------------------- SLV_BUS_HANDLER: process (clk) @@ -220,16 +221,16 @@ SLV_BUS_HANDLER: process (clk) if SLV_READ_IN = '1' then case SLV_ADDR_IN is - when x"0141" => + when x"0101" => SLV_DATA_OUT <= gen_num; SLV_ACK_OUT <= '1'; - when x"0142" => + when x"0102" => SLV_DATA_OUT <= gen_pause; SLV_ACK_OUT <= '1'; - when x"0143" => + when x"0103" => SLV_DATA_OUT <= gen_down; SLV_ACK_OUT <= '1'; - when x"0146" => + when x"0105" => SLV_DATA_OUT(0) <= mux_sel; SLV_ACK_OUT <= '1'; when others => @@ -238,25 +239,19 @@ SLV_BUS_HANDLER: process (clk) elsif SLV_WRITE_IN = '1' then case SLV_ADDR_IN is - when x"0140" => + when x"0100" => gen_start <= SLV_DATA_IN(0); SLV_ACK_OUT <= '1'; - when x"0141" => + when x"0101" => gen_num <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; - when x"0142" => + when x"0102" => gen_pause <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; - when x"0143" => + when x"0103" => gen_down <= SLV_DATA_IN; SLV_ACK_OUT <= '1'; - when x"0144" => - fifo_rden <= SLV_DATA_IN(3 downto 0); - SLV_ACK_OUT <= '1'; - when x"0145" => - sd_fifo_rden <= SLV_DATA_IN(3 downto 0); - SLV_ACK_OUT <= '1'; - when x"0146" => + when x"0105" => mux_sel <= SLV_DATA_IN(0); SLV_ACK_OUT <= '1'; when others => diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 182f71f..6bce0c7 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -45,9 +45,9 @@ entity MupixBoard8 is fifo_data : in std_logic_vector(127 downto 0); -- mupix readout data from FIFOs --hit generator / source selector outputs - mux_data_out : out std_logic_vector(127 downto 0); - mux_fifo_full : out std_logic_vector(3 downto 0); - mux_fifo_empty : out std_logic_vector(3 downto 0); + -- mux_data_out : out std_logic_vector(127 downto 0); + -- mux_fifo_full : out std_logic_vector(3 downto 0); + -- mux_fifo_empty : out std_logic_vector(3 downto 0); --resets timestampreset_in : in std_logic; --time stamp reset @@ -229,6 +229,8 @@ architecture Behavioral of MupixBoard8 is SLV_UNKNOWN_ADDR_OUT : out std_logic ); end component MupixTRBReadout; + + signal in_rden : std_logic_vector(3 downto 0); component TriggerHandler port( @@ -275,6 +277,7 @@ architecture Behavioral of MupixBoard8 is serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); serdes_fifo_full : in std_logic_vector(3 downto 0); serdes_fifo_empty : in std_logic_vector(3 downto 0); + in_rden : in std_logic_vector(3 downto 0); serdes_fifo_rden : out std_logic_vector(3 downto 0); out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); out_fifo_full : out std_logic_vector(3 downto 0); @@ -291,8 +294,12 @@ architecture Behavioral of MupixBoard8 is ); end component FrameGeneratorMux; - constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos - constant DATA_WIDTH : natural := 32; --width of datawords + constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos + constant DATA_WIDTH : natural := 32; --width of datawords + + signal mux_fifo_data : std_logic_vector(127 downto 0); + signal mux_fifo_full : std_logic_vector(3 downto 0); + signal mux_fifo_empty : std_logic_vector(3 downto 0); --signal declarations -- Bus Handler @@ -493,10 +500,10 @@ begin -- Behavioral port map( clk => clk, rst => reset, - fifo_empty => fifo_empty, - fifo_full => fifo_full, - fifo_datain => fifo_data, - fifo_rden => fifo_rden, + fifo_empty => mux_fifo_empty, + fifo_full => mux_fifo_full, + fifo_datain => mux_fifo_data, + fifo_rden => in_rden, trb_trigger => trb_trigger_i, dataout => mupixdata_i, data_valid => mupixdata_valid_i, @@ -544,8 +551,8 @@ begin -- Behavioral hitgenerator_1: component FrameGeneratorMux generic map( - fpga_clk_speed => fpga_clk_speed - spi_clk_speed => spi_clk_speed + fpga_clk_speed => fpga_clk_speed, + spi_clk_speed => mupix_spi_clk_speed, FIFODEPTH => FIFO_DEPTH, DATAWIDTH => DATA_WIDTH ) @@ -556,7 +563,8 @@ begin -- Behavioral serdes_fifo_full => fifo_full, serdes_fifo_empty => fifo_empty, serdes_fifo_rden => fifo_rden, - out_data => mux_data_out, + in_rden => in_rden, + out_data => mux_fifo_data, out_fifo_full => mux_fifo_full, out_fifo_empty => mux_fifo_empty, --TRB slow control -- 2.43.0