From fd17a5c66008d7737bd37eec6e1252b24d952b8e Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Sun, 25 May 2014 14:07:07 +0200 Subject: [PATCH] nxyter timestamp histogram added --- nxyter/cores/ram_dp_512x32.ipx | 10 ++ nxyter/cores/ram_dp_512x32.lpc | 53 +++++++++ nxyter/cores/ram_dp_512x32.vhd | 162 ++++++++++++++++++++++++++ nxyter/source/nx_data_delay.vhd | 11 -- nxyter/source/nx_data_receiver.vhd | 17 ++- nxyter/source/nx_data_validate.vhd | 4 +- nxyter/source/nx_histogram.vhd | 120 ++++++++++++------- nxyter/source/nx_histograms.vhd | 45 +++++-- nxyter/source/nx_trigger_validate.vhd | 69 +++++++---- nxyter/source/nxyter_components.vhd | 43 ++++++- nxyter/source/nxyter_fee_board.vhd | 19 +-- nxyter/source/registers.txt | 20 +++- nxyter/trb3_periph.prj | 2 + nxyter/trb3_periph_multi.p2t | 2 +- 14 files changed, 467 insertions(+), 110 deletions(-) create mode 100644 nxyter/cores/ram_dp_512x32.ipx create mode 100644 nxyter/cores/ram_dp_512x32.lpc create mode 100644 nxyter/cores/ram_dp_512x32.vhd diff --git a/nxyter/cores/ram_dp_512x32.ipx b/nxyter/cores/ram_dp_512x32.ipx new file mode 100644 index 0000000..cdcadd5 --- /dev/null +++ b/nxyter/cores/ram_dp_512x32.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/nxyter/cores/ram_dp_512x32.lpc b/nxyter/cores/ram_dp_512x32.lpc new file mode 100644 index 0000000..0008a06 --- /dev/null +++ b/nxyter/cores/ram_dp_512x32.lpc @@ -0,0 +1,53 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP +CoreRevision=6.1 +ModuleName=ram_dp_512x32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/20/2014 +Time=16:10:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=512 +RData=32 +WAddress=512 +WData=32 +enByte=0 +ByteSize=9 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +Pad=0 +EnECC=0 +Optimization=Speed +EnSleep=ENABLED +Pipeline=0 + +[FilesGenerated] +=mem diff --git a/nxyter/cores/ram_dp_512x32.vhd b/nxyter/cores/ram_dp_512x32.vhd new file mode 100644 index 0000000..d05dd20 --- /dev/null +++ b/nxyter/cores/ram_dp_512x32.vhd @@ -0,0 +1,162 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 6.1 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -outdata REGISTERED -cascade -1 -e + +-- Tue May 20 16:10:10 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ram_dp_512x32 is + port ( + WrAddress: in std_logic_vector(8 downto 0); + RdAddress: in std_logic_vector(8 downto 0); + Data: in std_logic_vector(31 downto 0); + WE: in std_logic; + RdClock: in std_logic; + RdClockEn: in std_logic; + Reset: in std_logic; + WrClock: in std_logic; + WrClockEn: in std_logic; + Q: out std_logic_vector(31 downto 0)); +end ram_dp_512x32; + +architecture Structure of ram_dp_512x32 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of ram_dp_512x32_0_0_0 : label is "ram_dp_512x32.lpc"; + attribute MEM_INIT_FILE of ram_dp_512x32_0_0_0 : label is ""; + attribute RESETMODE of ram_dp_512x32_0_0_0 : label is "SYNC"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ram_dp_512x32_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), + ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), + ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8), + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1), + ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4), + ADR10=>RdAddress(5), ADR11=>RdAddress(6), + ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ram_dp_512x32 is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/source/nx_data_delay.vhd b/nxyter/source/nx_data_delay.vhd index 637924e..039d613 100644 --- a/nxyter/source/nx_data_delay.vhd +++ b/nxyter/source/nx_data_delay.vhd @@ -73,7 +73,6 @@ architecture Behavioral of nx_data_delay is signal debug_r : std_logic; -- Misc - signal fifo_select : std_logic; signal debug_fifo : std_logic_vector(15 downto 0); begin @@ -196,7 +195,6 @@ begin slv_no_more_data_o <= '0'; fifo_reset_r <= '0'; debug_r <= '0'; - fifo_select <= '0'; else slv_data_o <= (others => '0'); slv_unknown_addr_o <= '0'; @@ -215,11 +213,6 @@ begin slv_data_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - when x"0002" => - slv_data_o(0) <= fifo_select; - slv_data_o(31 downto 1) <= (others => '0'); - slv_ack_o <= '1'; - when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -235,10 +228,6 @@ begin debug_r <= SLV_DATA_IN(0); slv_ack_o <= '1'; - when x"0002" => - fifo_select <= SLV_DATA_IN(0); - slv_ack_o <= '1'; - when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 89542f6..0878262 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -47,6 +47,7 @@ entity nx_data_receiver is SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + DISABLE_ADC_OUT : out std_logic; ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -1073,7 +1074,7 @@ begin if (disable_adc = '0') then data_frame(43 downto 32) <= adc_data_s; else - data_frame(43 downto 32) <= x"dea"; + data_frame(43 downto 32) <= x"000"; end if; data_frame_clk <= '1'; merge_timeout_ctr <= (others => '0'); @@ -1645,6 +1646,7 @@ begin PROC_ERROR_STATUS: process(CLK_IN) + variable error_mask : std_logic_vector(15 downto 0); begin if (rising_edge(CLK_IN)) then adc_sclk_ok_f <= adc_sclk_ok; @@ -1656,7 +1658,7 @@ begin adc_error_counter <= (others => '0'); else adc_sclk_ok_c100 <= adc_sclk_ok_f; - + error_status_bits(0) <= nx_frame_rate_offline; error_status_bits(1) <= frame_rate_error; error_status_bits(2) <= nx_frame_rate_error; @@ -1671,8 +1673,14 @@ begin error_status_bits(11) <= adc_dt_error; error_status_bits(12) <= reset_handler_busy; error_status_bits(15 downto 13) <= (others => '0'); - - if (error_status_bits = x"0000") then + + if (disable_adc_r = '1') then + error_mask := x"f437"; + else + error_mask := x"0000"; + end if; + + if ((error_status_bits and error_mask) = x"0000") then error_o <= '0'; else error_o <= '1'; @@ -1985,6 +1993,7 @@ begin DATA_OUT <= data_o; DATA_CLK_OUT <= data_clk_o; ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock; + DISABLE_ADC_OUT <= disable_adc_r; ERROR_OUT <= error_o; SLV_DATA_OUT <= slv_data_out_o; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 63f20e1..787877c 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -35,6 +35,7 @@ entity nx_data_validate is SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + DISABLE_ADC_IN : in std_logic; ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -518,13 +519,12 @@ begin if (RESET_IN = '1') then error_o <= '0'; else - if (adc_tr_error_rate > x"0000020") then + if (adc_tr_error_rate > x"0000020" and DISABLE_ADC_IN = '0') then error_o <= '1'; else error_o <= '0'; end if; end if; - end if; end process PROC_ADC_TOKEN_RETURN_ERROR; diff --git a/nxyter/source/nx_histogram.vhd b/nxyter/source/nx_histogram.vhd index ed7983c..2757c38 100644 --- a/nxyter/source/nx_histogram.vhd +++ b/nxyter/source/nx_histogram.vhd @@ -7,8 +7,7 @@ use work.nxyter_components.all; entity nx_histogram is generic ( - BUS_WIDTH : integer := 7; - DATA_WIDTH : integer := 32 + BUS_WIDTH : integer := 7 ); port ( CLK_IN : in std_logic; @@ -17,14 +16,14 @@ entity nx_histogram is NUM_AVERAGES_IN : in unsigned(2 downto 0); AVERAGE_ENABLE_IN : in std_logic; CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); - CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); + CHANNEL_DATA_IN : in std_logic_vector(31 downto 0); CHANNEL_ADD_IN : in std_logic; CHANNEL_WRITE_IN : in std_logic; CHANNEL_WRITE_BUSY_OUT : out std_logic; CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); CHANNEL_READ_IN : in std_logic; - CHANNEL_DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); + CHANNEL_DATA_OUT : out std_logic_vector(31 downto 0); CHANNEL_DATA_VALID_OUT : out std_logic; CHANNEL_READ_BUSY_OUT : out std_logic; @@ -44,23 +43,23 @@ architecture Behavioral of nx_histogram is ); signal H_STATE, H_NEXT_STATE : H_STATES; - signal address_hist_m : std_logic_vector(6 downto 0); - signal address_hist_m_x : std_logic_vector(6 downto 0); - signal data_hist_m : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal data_hist_m_x : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal address_hist_m : std_logic_vector(BUS_WIDTH - 1 downto 0); + signal address_hist_m_x : std_logic_vector(BUS_WIDTH - 1 downto 0); + signal data_hist_m : std_logic_vector(31 downto 0); + signal data_hist_m_x : std_logic_vector(31 downto 0); - signal read_data_hist : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal read_data_hist : std_logic_vector(31 downto 0); signal read_data_ctr_hist : unsigned(7 downto 0); signal read_address_hist : std_logic_vector(BUS_WIDTH - 1 downto 0); signal read_enable_hist : std_logic; - signal write_data_hist : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal write_data_hist : std_logic_vector(31 downto 0); signal write_data_ctr_hist : unsigned(7 downto 0); signal write_address_hist : std_logic_vector(BUS_WIDTH - 1 downto 0); signal write_enable_hist : std_logic; signal write_address : std_logic_vector(BUS_WIDTH - 1 downto 0); - signal write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal write_data : std_logic_vector(31 downto 0); signal write_enable : std_logic; signal channel_write_busy_o : std_logic; @@ -70,10 +69,10 @@ architecture Behavioral of nx_histogram is -- Hist Read Handler signal read_address : std_logic_vector(BUS_WIDTH - 1 downto 0); - signal read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal read_data : std_logic_vector(31 downto 0); signal read_enable_p : std_logic; signal read_enable : std_logic; - signal channel_data_o : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal channel_data_o : std_logic_vector(31 downto 0); signal channel_data_valid_o : std_logic; signal channel_data_valid_o_f : std_logic_vector(2 downto 0); signal channel_read_busy_o : std_logic; @@ -99,36 +98,73 @@ begin ----------------------------------------------------------------------------- - ram_dp_128x40_hist: ram_dp_128x40 - port map ( - WrAddress => write_address_hist, - RdAddress => read_address_hist, - Data(31 downto 0) => write_data_hist, - Data(39 downto 32) => write_data_ctr_hist, - WE => not RESET_IN, - RdClock => CLK_IN, - RdClockEn => read_enable_hist, - Reset => RESET_IN, - WrClock => CLK_IN, - WrClockEn => write_enable_hist, - Q(31 downto 0) => read_data_hist, - Q(39 downto 32) => read_data_ctr_hist - ); - - ram_dp_128x32_result: ram_dp_128x32 - port map ( - WrAddress => write_address, - RdAddress => read_address, - Data => write_data, - WE => not RESET_IN, - RdClock => CLK_IN, - RdClockEn => read_enable, - Reset => RESET_IN, - WrClock => CLK_IN, - WrClockEn => write_enable, - Q => read_data - ); + SMALL: if (BUS_WIDTH = 7) generate + + ram_dp_COUNTER_HIST: ram_dp_128x40 + port map ( + WrAddress => write_address_hist, + RdAddress => read_address_hist, + Data(31 downto 0) => write_data_hist, + Data(39 downto 32) => write_data_ctr_hist, + WE => not RESET_IN, + RdClock => CLK_IN, + RdClockEn => read_enable_hist, + Reset => RESET_IN, + WrClock => CLK_IN, + WrClockEn => write_enable_hist, + Q(31 downto 0) => read_data_hist, + Q(39 downto 32) => read_data_ctr_hist + ); + + ram_dp_RESULT_HIST: ram_dp_128x32 + port map ( + WrAddress => write_address, + RdAddress => read_address, + Data => write_data, + WE => not RESET_IN, + RdClock => CLK_IN, + RdClockEn => read_enable, + Reset => RESET_IN, + WrClock => CLK_IN, + WrClockEn => write_enable, + Q => read_data + ); + end generate SMALL; + + LARGE: if (BUS_WIDTH = 9) generate + + ram_dp_COUNTER_HIST: ram_dp_512x40 + port map ( + WrAddress => write_address_hist, + RdAddress => read_address_hist, + Data(31 downto 0) => write_data_hist, + Data(39 downto 32) => write_data_ctr_hist, + WE => not RESET_IN, + RdClock => CLK_IN, + RdClockEn => read_enable_hist, + Reset => RESET_IN, + WrClock => CLK_IN, + WrClockEn => write_enable_hist, + Q(31 downto 0) => read_data_hist, + Q(39 downto 32) => read_data_ctr_hist + ); + + ram_dp_RESULT_HIST: ram_dp_512x32 + port map ( + WrAddress => write_address, + RdAddress => read_address, + Data => write_data, + WE => not RESET_IN, + RdClock => CLK_IN, + RdClockEn => read_enable, + Reset => RESET_IN, + WrClock => CLK_IN, + WrClockEn => write_enable, + Q => read_data + ); + end generate LARGE; + ----------------------------------------------------------------------------- -- Memory Handler ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index 979c3c7..1f86376 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -15,7 +15,7 @@ entity nx_histograms is CHANNEL_FILL_IN : in std_logic; CHANNEL_ID_IN : in std_logic_vector(6 downto 0); CHANNEL_ADC_IN : in std_logic_vector(11 downto 0); - CHANNEL_TS_IN : in std_logic_vector(6 downto 0); + CHANNEL_TS_IN : in std_logic_vector(8 downto 0); CHANNEL_PILEUP_IN : in std_logic; CHANNEL_OVERFLOW_IN : in std_logic; @@ -106,12 +106,12 @@ architecture Behavioral of nx_histograms is signal ts_write_busy : std_logic; signal ts_read_busy : std_logic; - signal ts_write_id : std_logic_vector(6 downto 0); + signal ts_write_id : std_logic_vector(8 downto 0); signal ts_write_data : std_logic_vector(31 downto 0); signal ts_write : std_logic; signal ts_add : std_logic; - signal ts_read_id : std_logic_vector(6 downto 0); + signal ts_read_id : std_logic_vector(8 downto 0); signal ts_read : std_logic; signal ts_read_data : std_logic_vector(31 downto 0); signal ts_read_data_valid : std_logic; @@ -151,6 +151,9 @@ begin RESET_HISTS <= RESET_IN or RESET_HISTS_IN; nx_histogram_hits: nx_histogram + generic map ( + BUS_WIDTH => 7 + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_HISTS, @@ -169,10 +172,13 @@ begin CHANNEL_DATA_VALID_OUT => hit_read_data_valid, CHANNEL_READ_BUSY_OUT => hit_read_busy, - DEBUG_OUT => DEBUG_OUT --open + DEBUG_OUT => open ); nx_histogram_adc: nx_histogram + generic map ( + BUS_WIDTH => 7 + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_HISTS, @@ -195,6 +201,9 @@ begin ); nx_histogram_pileup: nx_histogram + generic map ( + BUS_WIDTH => 7 + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_HISTS, @@ -217,6 +226,9 @@ begin ); nx_histogram_ovfl: nx_histogram + generic map ( + BUS_WIDTH => 7 + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_HISTS, @@ -237,8 +249,11 @@ begin DEBUG_OUT => open ); - + nx_histogram_ts: nx_histogram + generic map ( + BUS_WIDTH => 9 + ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_HISTS, @@ -257,7 +272,7 @@ begin CHANNEL_DATA_VALID_OUT => ts_read_data_valid, CHANNEL_READ_BUSY_OUT => ts_read_busy, - DEBUG_OUT => open + DEBUG_OUT => DEBUG_OUT ); ----------------------------------------------------------------------------- @@ -455,8 +470,8 @@ begin adc_read <= '1'; slv_ack_o <= '0'; elsif (unsigned(SLV_ADDR_IN) >= x"0400" and - unsigned(SLV_ADDR_IN) <= x"047f") then - ts_read_id <= SLV_ADDR_IN(6 downto 0); + unsigned(SLV_ADDR_IN) <= x"05ff") then + ts_read_id <= SLV_ADDR_IN(8 downto 0); ts_read <= '1'; slv_ack_o <= '0'; else @@ -505,7 +520,13 @@ begin slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - when x"0481" => + when x"0600" => + slv_data_out_o(2 downto 0) <= + std_logic_vector(ts_num_averages); + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0601" => slv_data_out_o(0) <= ts_average_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; @@ -552,7 +573,11 @@ begin adc_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; - when x"0481" => + when x"0600" => + ts_num_averages <= SLV_DATA_IN(2 downto 0); + slv_ack_o <= '1'; + + when x"0601" => ts_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 86941ba..fd4dc1c 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -42,7 +42,7 @@ entity nx_trigger_validate is HISTOGRAM_FILL_OUT : out std_logic; HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0); - HISTOGRAM_TS_OUT : out std_logic_vector(6 downto 0); + HISTOGRAM_TS_OUT : out std_logic_vector(8 downto 0); HISTOGRAM_PILEUP_OUT : out std_logic; HISTOGRAM_OVERFLOW_OUT : out std_logic; @@ -172,10 +172,12 @@ architecture Behavioral of nx_trigger_validate is signal histogram_fill_o : std_logic; signal histogram_bin_o : std_logic_vector(6 downto 0); signal histogram_adc_o : std_logic_vector(11 downto 0); - signal histogram_ts_o : std_logic_vector(6 downto 0); + signal histogram_ts_o : std_logic_vector(8 downto 0); signal histogram_pileup_o : std_logic; signal histogram_ovfl_o : std_logic; - + + signal histogram_ts_range : std_logic_vector(2 downto 0); + -- Data FIFO Delay signal data_fifo_delay_o : unsigned(7 downto 0); @@ -276,6 +278,7 @@ begin variable window_upper_thr : unsigned(11 downto 0); variable ts_window_check_value : unsigned(11 downto 0); variable deltaTStore : unsigned(13 downto 0); + variable histTStore : unsigned(8 downto 0); variable store_data : std_logic; begin if( rising_edge(CLK_IN) ) then @@ -439,21 +442,38 @@ begin -- Fill Histogram if (histogram_trig_filter = '1') then + case histogram_ts_range is + when "000" => + histTStore := deltaTStore( 8 downto 0); + when "001" => + histTStore := deltaTStore( 9 downto 1); + when "010" => + histTStore := deltaTStore(10 downto 2); + when "011" => + histTStore := deltaTStore(11 downto 3); + when "100" => + histTStore := deltaTStore(12 downto 4); + when "101" => + histTStore := deltaTStore(13 downto 5); + when others => + histTStore := deltaTStore(12 downto 4); + end case; + if (histogram_limits = '1') then if (deltaTStore >= histogram_lower_limit and deltaTStore <= histogram_upper_limit) then - histogram_fill_o <= '1'; - histogram_bin_o <= CHANNEL_IN; - histogram_adc_o <= ADC_DATA_IN; - histogram_ts_o <= deltaTStore(10 downto 4); - histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); - histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); + histogram_fill_o <= '1'; + histogram_bin_o <= CHANNEL_IN; + histogram_adc_o <= ADC_DATA_IN; + histogram_ts_o <= histTStore; + histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); + histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); end if; else histogram_fill_o <= '1'; histogram_bin_o <= CHANNEL_IN; histogram_adc_o <= ADC_DATA_IN; - histogram_ts_o <= deltaTStore(10 downto 4); + histogram_ts_o <= histTStore; histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); end if; @@ -926,6 +946,7 @@ begin reset_hists <= '0'; histogram_limits <= '0'; histogram_trig_filter <= '0'; + histogram_ts_range <= "100"; else slv_data_out_o <= (others => '0'); slv_unknown_addr_o <= '0'; @@ -1104,24 +1125,24 @@ begin slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; - --when x"001d" => - -- slv_data_out_o(15 downto 0) <= - -- std_logic_vector(window_hit_ctr_r); - -- slv_data_out_o(31 downto 16) <= (others => '0'); - -- slv_ack_o <= '1'; - when x"001d" => slv_data_out_o(15 downto 0) <= - std_logic_vector(out_of_window_h_ctr_r); + std_logic_vector(window_hit_ctr_r); slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; when x"001e" => - slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate); - slv_data_out_o(31 downto 28) <= (others => '0'); + slv_data_out_o(15 downto 0) <= + std_logic_vector(out_of_window_h_ctr_r); + slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; when x"001f" => + slv_data_out_o(27 downto 0) <= std_logic_vector(data_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0020" => slv_data_out_o(13 downto 0) <= std_logic_vector(histogram_lower_limit); slv_data_out_o(28 downto 15) <= @@ -1131,6 +1152,11 @@ begin slv_data_out_o(31) <= histogram_trig_filter; slv_ack_o <= '1'; + when x"0021" => + slv_data_out_o(2 downto 0) <= histogram_ts_range; + slv_data_out_o(31 downto 3) <= (others => '0'); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -1186,7 +1212,7 @@ begin unsigned(SLV_DATA_IN(11 downto 0)); slv_ack_o <= '1'; - when x"001f" => + when x"0020" => histogram_lower_limit <= SLV_DATA_IN(13 downto 0); histogram_upper_limit <= SLV_DATA_IN(28 downto 15); reset_hists <= SLV_DATA_IN(29); @@ -1194,6 +1220,9 @@ begin histogram_trig_filter <= SLV_DATA_IN(31); slv_ack_o <= '1'; + when x"0021" => + histogram_ts_range <= SLV_DATA_IN(2 downto 0); + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index aa97146..234ddb0 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -474,6 +474,7 @@ component nx_data_receiver SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + DISABLE_ADC_OUT : out std_logic; ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -521,6 +522,7 @@ component nx_data_validate SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + DISABLE_ADC_IN : in std_logic; ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -556,7 +558,7 @@ component nx_trigger_validate HISTOGRAM_FILL_OUT : out std_logic; HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0); - HISTOGRAM_TS_OUT : out std_logic_vector(6 downto 0); + HISTOGRAM_TS_OUT : out std_logic_vector(8 downto 0); HISTOGRAM_PILEUP_OUT : out std_logic; HISTOGRAM_OVERFLOW_OUT : out std_logic; SLV_READ_IN : in std_logic; @@ -629,8 +631,7 @@ end component; component nx_histogram generic ( - BUS_WIDTH : integer; - DATA_WIDTH : integer + BUS_WIDTH : integer ); port ( CLK_IN : in std_logic; @@ -638,13 +639,13 @@ component nx_histogram NUM_AVERAGES_IN : in unsigned(2 downto 0); AVERAGE_ENABLE_IN : in std_logic; CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); - CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); + CHANNEL_DATA_IN : in std_logic_vector(31 downto 0); CHANNEL_ADD_IN : in std_logic; CHANNEL_WRITE_IN : in std_logic; CHANNEL_WRITE_BUSY_OUT : out std_logic; CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); CHANNEL_READ_IN : in std_logic; - CHANNEL_DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); + CHANNEL_DATA_OUT : out std_logic_vector(31 downto 0); CHANNEL_DATA_VALID_OUT : out std_logic; CHANNEL_READ_BUSY_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0)); @@ -658,7 +659,7 @@ component nx_histograms CHANNEL_FILL_IN : in std_logic; CHANNEL_ID_IN : in std_logic_vector(6 downto 0); CHANNEL_ADC_IN : in std_logic_vector(11 downto 0); - CHANNEL_TS_IN : in std_logic_vector(6 downto 0); + CHANNEL_TS_IN : in std_logic_vector(8 downto 0); CHANNEL_PILEUP_IN : in std_logic; CHANNEL_OVERFLOW_IN : in std_logic; SLV_READ_IN : in std_logic; @@ -703,6 +704,36 @@ component ram_dp_128x32 ); end component; +component ram_dp_512x40 + port ( + WrAddress : in std_logic_vector(8 downto 0); + RdAddress : in std_logic_vector(8 downto 0); + Data : in std_logic_vector(39 downto 0); + WE : in std_logic; + RdClock : in std_logic; + RdClockEn : in std_logic; + Reset : in std_logic; + WrClock : in std_logic; + WrClockEn : in std_logic; + Q : out std_logic_vector(39 downto 0) + ); +end component; + +component ram_dp_512x32 + port ( + WrAddress : in std_logic_vector(8 downto 0); + RdAddress : in std_logic_vector(8 downto 0); + Data : in std_logic_vector(31 downto 0); + WE : in std_logic; + RdClock : in std_logic; + RdClockEn : in std_logic; + Reset : in std_logic; + WrClock : in std_logic; + WrClockEn : in std_logic; + Q : out std_logic_vector(31 downto 0) + ); +end component; + ------------------------------------------------------------------------------- component level_to_pulse diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 1a190c1..bf2ab83 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -139,6 +139,7 @@ architecture Behavioral of nXyter_FEE_board is signal data_recv : std_logic_vector(43 downto 0); signal data_clk_recv : std_logic; signal pll_sadc_clk_lock : std_logic; + signal disable_adc_receiver : std_logic; -- Data Delay signal data_delayed : std_logic_vector(43 downto 0); @@ -165,7 +166,7 @@ architecture Behavioral of nXyter_FEE_board is signal trigger_validate_fill : std_logic; signal trigger_validate_bin : std_logic_vector(6 downto 0); signal trigger_validate_adc : std_logic_vector(11 downto 0); - signal trigger_validate_ts : std_logic_vector(6 downto 0); + signal trigger_validate_ts : std_logic_vector(8 downto 0); signal trigger_validate_pileup : std_logic; signal trigger_validate_ovfl : std_logic; signal reset_hists : std_logic; @@ -245,7 +246,7 @@ begin PORT_ADDRESSES => ( 0 => x"0100", -- NX Status Handler 1 => x"0040", -- I2C Master 2 => x"0500", -- Data Receiver - 3 => x"0600", -- Data Buffer + 3 => x"0080", -- Event Buffer 4 => x"0060", -- SPI Master 5 => x"0140", -- Trigger Generator 6 => x"0120", -- Data Validate @@ -254,23 +255,23 @@ begin 9 => x"0200", -- NX Register Setup 10 => x"0800", -- NX Histograms 11 => x"0020", -- Debug Handler - 12 => x"0180", -- Data Delay + 12 => x"0000", -- Data Delay others => x"0000" ), PORT_ADDR_MASK => ( 0 => 4, -- NX Status Handler 1 => 1, -- I2C master 2 => 5, -- Data Receiver - 3 => 3, -- Data Buffer + 3 => 3, -- Event Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator 6 => 5, -- Data Validate 7 => 4, -- Trigger Handler - 8 => 5, -- Trigger Validate + 8 => 6, -- Trigger Validate 9 => 9, -- NX Register Setup - 10 => 10, -- NX Histograms + 10 => 11, -- NX Histograms 11 => 0, -- Debug Handler - 12 => 2, -- Data Delay + 12 => 1, -- Data Delay others => 0 ), @@ -579,7 +580,8 @@ begin SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), SLV_ACK_OUT => slv_ack(2), SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), + DISABLE_ADC_OUT => disable_adc_receiver, ERROR_OUT => error_data_receiver, DEBUG_OUT => debug_line(7) ); @@ -642,6 +644,7 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6), + DISABLE_ADC_IN => disable_adc_receiver, ERROR_OUT => error_data_validate, DEBUG_OUT => debug_line(9) ); diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 81c153f..2ac959b 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -36,6 +36,13 @@ 0x8270 : r Token register, 14 in a row -- Trigger Generator +0x8140 : r/w 3Bit: #0 Self Trigger On + #1 Pulser Trigger On + #2 Trigger Output Select (0: extern, 1: Intern) +0x8141 : r/w Pulser Trigger Period (28 Bit) +0x8142 : r Self Trigger Rate (1/s) +0x8143 : r Pulser Trigger Rate (1/s) +0x8144 : r Trigger Rate (1/s) -- Trigger Handler 0x8160 : r/w Enable Testpulse Signal (default: off) @@ -94,10 +101,10 @@ 0x8125 : r Frame Rate (in Hz) -- NX Data Delay -0x8180 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns). +0x8000 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns). Calculation is based on CTS Trigger Delay (see NX Trigger Validate) -0x8181 : r/w Debug Multiplexer (0=Data Delay, 1=FIFO) +0x8001 : r/w Debug Multiplexer (0=Data Delay, 1=FIFO) -- NX Trigger Validate 0x8400 : r/w Readout Mode: 4 Bits @@ -173,10 +180,11 @@ 0x8060 : Access to SPI Interface -- Histogram Handler -0x8800 : r Read Channel Hit Statistic (128 channel in a row) -0x8900 : r Read Channel Pileup Rate (128 channel in a row, 1/s) -0x8a00 : r Read Channel Overflow Rate (128 channel in a row, 1/s) -0x8b00 : r Read Channel averaged ADC Value (128 channel in a row) +0x8800 : r Read Channel Hit Statistic (128 channels in a row) +0x8900 : r Read Channel Pileup Rate (128 channels in a row, 1/s) +0x8a00 : r Read Channel Overflow Rate (128 channels in a row, 1/s) +0x8b00 : r Read Channel averaged ADC Value (128 channels in a row) +0x8c00 : r Read Channel Timestamp Statistic (512 channels in a row) 0x8880 : r/w Hit Rate num averages (3 Bit) 0x8881 : r/w Hit Rate average enable diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 42306ef..74e1ab3 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -148,6 +148,8 @@ add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd" add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd" +add_file -vhdl -lib "work" "cores/ram_dp_512x40.vhd" +add_file -vhdl -lib "work" "cores/ram_dp_512x32.vhd" add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd" add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd" add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index d55c38c..9b397c2 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -1,7 +1,7 @@ -w -i 2 -l 5 --n 28 +-n 8 -t 50 -s 1 -c 1 -- 2.43.0