From fd45c649d9487193192667d36c9d3e8f9544d049 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 15 Jun 2009 23:17:58 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/trb_net16_med_ecp_sfp_4.vhd | 176 +++++++++++++------ trb_net16_hub_ipu_logic.vhd | 19 +- trb_net16_ibuf.vhd | 6 - trb_net16_iobuf.vhd | 111 +----------- trb_net16_obuf.vhd | 26 ++- trb_net16_term_buf.vhd | 5 + trb_net_std.vhd | 4 + 7 files changed, 164 insertions(+), 183 deletions(-) diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd index 6df49cd..353bca6 100644 --- a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd @@ -15,8 +15,8 @@ entity trb_net16_med_ecp_sfp_4 is -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" ); port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -39,6 +39,7 @@ entity trb_net16_med_ecp_sfp_4 is SD_REFCLK_N_IN : in std_logic; SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable -- Status and control port STAT_OP : out std_logic_vector (4*16-1 downto 0); CTRL_OP : in std_logic_vector (4*16-1 downto 0); @@ -276,7 +277,8 @@ component serdes_sfp_full_quad is signal rx_data : std_logic_vector(4*16-1 downto 0); signal rx_k : std_logic_vector(7 downto 0); signal link_ok : std_logic_vector(3 downto 0); - + signal comb_rx_data : std_logic_vector(4*16 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(7 downto 0); -- original signals from SFP signal ff_rxhalfclk : std_logic_vector(3 downto 0); signal ff_txhalfclk : std_logic; --rx fifo signals @@ -306,12 +308,15 @@ component serdes_sfp_full_quad is signal last_fifo_tx_empty : std_logic_vector(3 downto 0); --link status signal rx_k_q : std_logic_vector(4*2-1 downto 0); + signal tx_k_q : std_logic_vector(4*2-1 downto 0); signal ffs_plol : std_logic; signal quad_rst : std_logic_vector(3 downto 0); signal lane_rst : std_logic_vector(3 downto 0); signal tx_allow : std_logic_vector(3 downto 0); signal rx_allow : std_logic_vector(3 downto 0); + signal rx_allow_qrx : std_logic_vector(3 downto 0); + signal tx_allow_qtx : std_logic_vector(3 downto 0); signal rx_allow_q : std_logic_vector(3 downto 0); -- clock domain changed signal signal tx_allow_q : std_logic_vector(3 downto 0); @@ -364,12 +369,95 @@ begin ) port map( RESET => RESET, - D_IN => rx_k(i*2+1 downto i*2), + D_IN => comb_rx_k(i*2+1 downto i*2), CLK0 => ff_rxhalfclk(i), CLK1 => SYSCLK, D_OUT => rx_k_q(i*2+1 downto i*2) ); + THE_TX_K_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN => tx_k(i*2+1 downto i*2), + CLK0 => ff_txhalfclk, + CLK1 => SYSCLK, + D_OUT => tx_k_q(i*2+1 downto i*2) + ); + + + -- delay line for RX_K and RX_DATA (directly from SFP to fabric logic) + THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset, + D_IN => comb_rx_data(i*16+15 downto i*16), + CLK0 => ff_rxhalfclk(i), + CLK1 => ff_rxhalfclk(i), + D_OUT => rx_data(i*16+15 downto i*16) + ); + + THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset, + D_IN => comb_rx_k(i*2+1 downto i*2), + CLK0 => ff_rxhalfclk(i), + CLK1 => ff_rxhalfclk(i), + D_OUT => rx_k(i*2+1 downto i*2) + ); + + THE_RX_ALLOW_SYNC: signal_sync -- really needed?!? + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN(0) => rx_allow(i), + D_IN(1) => tx_allow(i), + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => rx_allow_q(i), + D_OUT(1) => tx_allow_q(i) + ); + + THE_RX_ALLOW_SYNC_RX: signal_sync -- really needed?!? + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => RESET, + D_IN(0) => rx_allow(i), + CLK0 => ff_rxhalfclk(i), + CLK1 => ff_rxhalfclk(i), + D_OUT(0) => rx_allow_qrx(i) + ); + + THE_TX_ALLOW_SYNC_TX: signal_sync -- really needed?!? + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => RESET, + D_IN(0) => tx_allow(i), + CLK0 => ff_txhalfclk, + CLK1 => ff_txhalfclk, + D_OUT(0) => tx_allow_qtx(i) + ); + + ---------------------------------------------------------------------------------------------------------- -- NEW STATEMACHINE START ---------------------------------------------------------------------------------------------------------- @@ -396,6 +484,9 @@ begin CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16), STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32) ); + + + sd_txdis_out <= quad_rst(0); ---------------------------------------------------------------------------------------------------------- -- NEW STATEMACHINE STOP ---------------------------------------------------------------------------------------------------------- @@ -419,9 +510,9 @@ begin ff_txiclk_ch0 => ff_txhalfclk, ff_ebrd_clk_0 => ff_rxhalfclk(0), ff_txdata_ch0 => tx_data(15 downto 0), - ff_rxdata_ch0 => rx_data(15 downto 0), + ff_rxdata_ch0 => comb_rx_data(15 downto 0), ff_tx_k_cntrl_ch0 => tx_k(1 downto 0), - ff_rx_k_cntrl_ch0 => rx_k(1 downto 0), + ff_rx_k_cntrl_ch0 => comb_rx_k(1 downto 0), ff_rxhalfclk_ch0 => ff_rxhalfclk(0), ff_force_disp_ch0 => "00", ff_disp_sel_ch0 => "00", @@ -450,9 +541,9 @@ begin ff_txiclk_ch1 => ff_txhalfclk, ff_ebrd_clk_1 => ff_rxhalfclk(1), ff_txdata_ch1 => tx_data(31 downto 16), - ff_rxdata_ch1 => rx_data(31 downto 16), + ff_rxdata_ch1 => comb_rx_data(31 downto 16), ff_tx_k_cntrl_ch1 => tx_k(3 downto 2), - ff_rx_k_cntrl_ch1 => rx_k(3 downto 2), + ff_rx_k_cntrl_ch1 => comb_rx_k(3 downto 2), ff_rxhalfclk_ch1 => ff_rxhalfclk(1), ff_force_disp_ch1 => "00", ff_disp_sel_ch1 => "00", @@ -481,9 +572,9 @@ begin ff_txiclk_ch2 => ff_txhalfclk, ff_ebrd_clk_2 => ff_rxhalfclk(2), ff_txdata_ch2 => tx_data(47 downto 32), - ff_rxdata_ch2 => rx_data(47 downto 32), + ff_rxdata_ch2 => comb_rx_data(47 downto 32), ff_tx_k_cntrl_ch2 => tx_k(5 downto 4), - ff_rx_k_cntrl_ch2 => rx_k(5 downto 4), + ff_rx_k_cntrl_ch2 => comb_rx_k(5 downto 4), ff_rxhalfclk_ch2 => ff_rxhalfclk(2), ff_force_disp_ch2 => "00", ff_disp_sel_ch2 => "00", @@ -512,9 +603,9 @@ begin ff_txiclk_ch3 => ff_txhalfclk, ff_ebrd_clk_3 => ff_rxhalfclk(3), ff_txdata_ch3 => tx_data(63 downto 48), - ff_rxdata_ch3 => rx_data(63 downto 48), + ff_rxdata_ch3 => comb_rx_data(63 downto 48), ff_tx_k_cntrl_ch3 => tx_k(7 downto 6), - ff_rx_k_cntrl_ch3 => rx_k(7 downto 6), + ff_rx_k_cntrl_ch3 => comb_rx_k(7 downto 6), ff_rxhalfclk_ch3 => ff_rxhalfclk(3), ff_force_disp_ch3 => "00", ff_disp_sel_ch3 => "00", @@ -557,9 +648,9 @@ begin ff_txiclk_ch0 => ff_txhalfclk, ff_ebrd_clk_0 => ff_rxhalfclk(3), ff_txdata_ch0 => tx_data(63 downto 48), - ff_rxdata_ch0 => rx_data(63 downto 48), + ff_rxdata_ch0 => comb_rx_data(63 downto 48), ff_tx_k_cntrl_ch0 => tx_k(7 downto 6), - ff_rx_k_cntrl_ch0 => rx_k(7 downto 6), + ff_rx_k_cntrl_ch0 => comb_rx_k(7 downto 6), ff_rxhalfclk_ch0 => ff_rxhalfclk(3), ff_force_disp_ch0 => "00", ff_disp_sel_ch0 => "00", @@ -588,9 +679,9 @@ begin ff_txiclk_ch1 => ff_txhalfclk, ff_ebrd_clk_1 => ff_rxhalfclk(2), ff_txdata_ch1 => tx_data(47 downto 32), - ff_rxdata_ch1 => rx_data(47 downto 32), + ff_rxdata_ch1 => comb_rx_data(47 downto 32), ff_tx_k_cntrl_ch1 => tx_k(5 downto 4), - ff_rx_k_cntrl_ch1 => rx_k(5 downto 4), + ff_rx_k_cntrl_ch1 => comb_rx_k(5 downto 4), ff_rxhalfclk_ch1 => ff_rxhalfclk(2), ff_force_disp_ch1 => "00", ff_disp_sel_ch1 => "00", @@ -619,9 +710,9 @@ begin ff_txiclk_ch2 => ff_txhalfclk, ff_ebrd_clk_2 => ff_rxhalfclk(1), ff_txdata_ch2 => tx_data(31 downto 16), - ff_rxdata_ch2 => rx_data(31 downto 16), + ff_rxdata_ch2 => comb_rx_data(31 downto 16), ff_tx_k_cntrl_ch2 => tx_k(3 downto 2), - ff_rx_k_cntrl_ch2 => rx_k(3 downto 2), + ff_rx_k_cntrl_ch2 => comb_rx_k(3 downto 2), ff_rxhalfclk_ch2 => ff_rxhalfclk(1), ff_force_disp_ch2 => "00", ff_disp_sel_ch2 => "00", @@ -650,9 +741,9 @@ begin ff_txiclk_ch3 => ff_txhalfclk, ff_ebrd_clk_3 => ff_rxhalfclk(0), ff_txdata_ch3 => tx_data(15 downto 0), - ff_rxdata_ch3 => rx_data(15 downto 0), + ff_rxdata_ch3 => comb_rx_data(15 downto 0), ff_tx_k_cntrl_ch3 => tx_k(1 downto 0), - ff_rx_k_cntrl_ch3 => rx_k(1 downto 0), + ff_rx_k_cntrl_ch3 => comb_rx_k(1 downto 0), ff_rxhalfclk_ch3 => ff_rxhalfclk(0), ff_force_disp_ch3 => "00", ff_disp_sel_ch3 => "00", @@ -713,20 +804,20 @@ begin if( swap_bytes(i) = '0' ) then fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2) & rx_data(i*16+15 downto i*16+8) & rx_data(i*16+7 downto i*16); - fifo_rx_wr_en(i) <= not rx_k(i*2) and rx_allow_q(i) and link_ok(i); + fifo_rx_wr_en(i) <= not rx_k(i*2) and rx_allow_qrx(i) and link_ok(i); else fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+0) & last_rx(i*9+8) & rx_data(i*16+7 downto i*16+0) & last_rx(i*9+7 downto i*9+0); - fifo_rx_wr_en(i) <= not last_rx(i*9+8) and rx_allow_q(i) and link_ok(i); + fifo_rx_wr_en(i) <= not last_rx(i*9+8) and rx_allow_qrx(i) and link_ok(i); end if; end if; end process; - buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18); - buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16) - and not last_fifo_rx_empty(i) and rx_allow(i); + buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18); + buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16) + and not last_fifo_rx_empty(i) and rx_allow_q(i); buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3); - med_read_out(i) <= tx_allow_q(i); + med_read_out(i) <= tx_allow_q(i); THE_SYNC_PROC: process( SYSCLK ) begin @@ -747,7 +838,7 @@ begin begin if( rising_edge(SYSCLK) ) then last_fifo_rx_empty(i) <= fifo_rx_empty(i); - if RESET = '1' or rx_allow(i) = '0' then + if RESET = '1' or rx_allow_q(i) = '0' then rx_counter(i*3+2 downto i*3) <= c_H0; else if( buf_med_dataready_out(i) = '1' ) then @@ -782,40 +873,15 @@ begin fifo_tx_reset(i) <= reset or not tx_allow_q(i); fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0)& med_data_in(i*16+15 downto i*16); fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow(i); - fifo_tx_rd_en(i) <= tx_allow_q(i); + fifo_tx_rd_en(i) <= tx_allow_qtx(i); - THE_tx_allow_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => tx_allow(i), - CLK0 => SYSCLK, - CLK1 => ff_txhalfclk, - D_OUT(0) => tx_allow_q(i) - ); - - THE_rx_allow_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => rx_allow(i), - CLK0 => SYSCLK, - CLK1 => ff_rxhalfclk(i), - D_OUT(0) => rx_allow_q(i) - ); THE_SERDES_INPUT_PROC: process( ff_txhalfclk ) begin if( rising_edge(ff_txhalfclk) ) then last_fifo_tx_empty(i) <= fifo_tx_empty(i); - if( (last_fifo_tx_empty(i) = '1') or (tx_allow(i) = '0') ) then + if( (last_fifo_tx_empty(i) = '1') or (tx_allow_qtx(i) = '0') ) then tx_data(i*16+15 downto i*16) <= x"c5bc"; tx_k(i*2+1 downto i*2) <= "01"; else @@ -839,7 +905,7 @@ begin elsif( led_counter = 0 ) then rx_led(i) <= '0'; end if; - if( last_fifo_tx_empty(i) = '0') then + if( tx_k_q(i*2) = '0') then tx_led(i) <= '1'; elsif led_counter = 0 then tx_led(i) <= '0'; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index b4cd7ac..0551459 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -462,7 +462,7 @@ begin --saving (D)HDR ------------------------- gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate - hdrram_write_enable(i) <= (current_reply_reading_HDR(i) or current_reply_reading_DHDR(i)) and not reply_reading_H0(i); + hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or current_reply_reading_DHDR(i)) and not reply_reading_H0(i); -- (current_reply_reading_HDR(i) and -- (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or @@ -564,9 +564,9 @@ begin tmpF2 := '0'; tmpF3 := '0'; for i in 0 to POINT_NUMBER-1 loop - tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F1(i) and current_reply_reading_TRM(i)); - tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and current_reply_reading_TRM(i)); - tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and current_reply_reading_TRM(i)); + tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F1(i) and reg_current_reply_reading_TRM(i)); + tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and reg_current_reply_reading_TRM(i)); + tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and reg_current_reply_reading_TRM(i)); end loop; reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1; reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2; @@ -632,7 +632,7 @@ begin if RESET = '1' or send_reply_trm = '1' or locked = '0' then got_trm <= (others => '0'); else - got_trm <= got_trm or locking_point or (reply_reading_F3 and current_reply_reading_TRM) or not real_activepoints; + got_trm <= got_trm or locking_point or (reply_reading_F3 and reg_current_reply_reading_TRM) or not real_activepoints; end if; end if; end process; @@ -769,9 +769,9 @@ reply_compare_finished <= reply_compare_start; comb_REPLY_POOL_PACKET_NUM <= packet_counter; comb_REPLY_POOL_DATA <= (others => '0'); next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints - and not (current_reply_reading_DHDR and reply_reading_F1); + and not (reg_current_reply_reading_DHDR and reply_reading_F1); last_dhdr_addr <= "000"; - next_current_waiting_for_reply <= current_waiting_for_reply and not current_reply_reading_HDR and real_activepoints; + next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints; next_reply_adder_start <= '0'; reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints); reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); @@ -884,9 +884,10 @@ reply_compare_finished <= reply_compare_start; when SENDING_DATA => reply_arbiter_enable <= '1'; last_dhdr_addr <= "110"; --length - if packet_counter = c_H0 + if packet_counter = c_H0 then -- and not (comb_REPLY_muxed_PACKET_NUM = c_H0 and comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM) - and current_muxed_reading_DAT = '1' then +-- and current_muxed_reading_DAT = '1' then + --sending new H0 without checking for reading_DAT seems to be fine comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_DAT; comb_REPLY_POOL_DATA(15 downto 3) <= (others => '0'); diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 3afa129..6d74b49 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -142,7 +142,6 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal current_error_state, next_error_state : ERROR_STATE; signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0); signal fifo_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal saved_fifo_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal CRC_RESET, CRC_enable : std_logic; signal CRC_match : std_logic; @@ -269,17 +268,12 @@ counter_match <= '1'; fifo_packet_num_in <= reg_med_packet_num_in(2) & reg_med_packet_num_in(0); --regenerate long packet numbers --- fifo_long_packet_num_out(2) <= fifo_packet_num_out(1); --- fifo_long_packet_num_out(0) <= fifo_packet_num_out(0); --- fifo_long_packet_num_out(1) <= not saved_fifo_long_packet_num_out(1) when last_fifo_read = '1' and not saved_fifo_long_packet_num_out(2) = '1' and saved_fifo_long_packet_num_out(0) = '1' else saved_fifo_long_packet_num_out(1); - process(CLK) begin if rising_edge(CLK) then if RESET = '1' then fifo_long_packet_num_out <= (others => '0'); elsif next_last_fifo_read = '1' then --- saved_fifo_long_packet_num_out <= fifo_long_packet_num_out; fifo_long_packet_num_out(2) <= next_fifo_packet_num_out(1); fifo_long_packet_num_out(0) <= next_fifo_packet_num_out(0); if fifo_long_packet_num_out(2) = '0' and fifo_long_packet_num_out(0) = '1' then diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index e6bd60a..23fe23e 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -5,6 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_iobuf is @@ -81,117 +82,7 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group"; - component trb_net16_obuf is - generic ( - DATA_COUNT_WIDTH : integer := 5; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; - component trb_net16_obuf_nodata is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - --STAT - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_ibuf is - generic ( - DEPTH : integer range 0 to 7 := c_FIFO_BRAM; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE : integer range 0 to 1 := c_YES; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_READ_IN : in std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_READ_IN : in std_logic; - INT_ERROR_OUT : out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_BUFFER : out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_term_ibuf is - generic( - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - -- Internal direction port - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - INT_ERROR_OUT: out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0) - ); - end component; -- internal signals for the INITIBUF signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 9b258f0..4afe5c9 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -121,6 +121,8 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal int_dataready_in_i : std_logic; signal int_data_in_i : std_logic_vector(15 downto 0); signal int_packet_num_in_i: std_logic_vector(2 downto 0); + signal last_buf_INT_READ_OUT : std_logic; + begin @@ -140,6 +142,17 @@ begin end if; end process; + proc_SAVE_INT_READ_OUT : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_buf_INT_READ_OUT <= '0'; + else + last_buf_INT_READ_OUT <= buf_INT_READ_OUT; + end if; + end if; + end process; + -- gen_sbuf : if SECURE_MODE = 1 generate SBUF:trb_net16_sbuf generic map ( @@ -299,17 +312,24 @@ begin next_INT_READ_OUT <= '1'; increase_TRANSMITTED_BUFFERS <= '0'; increase_DATA_COUNT <= '0'; - reset_DATA_COUNT <= '0'; + reset_DATA_COUNT <= '0'; next_SEND_ACK_IN <= send_ACK; comb_dataready <= '0'; next_sending_state <= sending_state; - CRC_enable <= reg_INT_READ_OUT and int_dataready_in_i and not int_packet_num_in_i(2); - CRC_RESET <= RESET; + CRC_enable <= '0'; + CRC_RESET <= RESET; --only data words are CRC'ed if (reg_INT_READ_OUT = '1' and int_dataready_in_i = '1') then --can only happen if idle or sending_data current_output_data_buffer <= current_DATA_word; + + if int_packet_num_in_i(2) = '0' and saved_packet_type /= TYPE_TRM then + CRC_enable <= '1'; + else + CRC_enable <= '0'; + end if; + comb_dataready <= '1'; if transfer_counter = c_F3_next then increase_DATA_COUNT <= '1'; --transfer_counter(1) and not transfer_counter(0); diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index 25c3a52..106e851 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -35,6 +35,11 @@ end entity; architecture trb_net16_term_buf_arch of trb_net16_term_buf is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_term_buf_arch : architecture is "IOBUF_group"; + signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); signal INIT_transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 0bddca8..50810f5 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -116,6 +116,10 @@ package trb_net_std is constant c_read_multiple_type : std_logic_vector(3 downto 0) := x"A"; constant c_write_multiple_type : std_logic_vector(3 downto 0) := x"B"; + constant c_BUS_HANDLER_MAX_PORTS : integer := 32; + type c_BUS_HANDLER_ADDR_t is array(0 to c_BUS_HANDLER_MAX_PORTS) of std_logic_vector(15 downto 0); + type c_BUS_HANDLER_WIDTH_t is array(0 to c_BUS_HANDLER_MAX_PORTS) of integer range 0 to 16; + --Names of 16bit words constant c_H0 : std_logic_vector(2 downto 0) := "100"; -- 2.43.0