From ff86fe2ee06b6c31e719530bee3331f1900046c9 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 4 Jul 2018 15:55:17 +0200 Subject: [PATCH] remove Latches on epoch counter register --- releases/tdc_v2.3/Channel_200.vhd | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 6d4662d..091aff6 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -154,7 +154,7 @@ architecture Channel_200 of Channel_200 is type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C); signal FSM_RD_STATE : FSM_RD; - signal trg_win_end_rdo_flag : std_logic := '0'; + signal trg_win_end_rdo_flag, trg_win_end_rdo_flag_f : std_logic := '0'; signal fsm_rd_debug : std_logic_vector(3 downto 0); attribute syn_keep : boolean; @@ -743,6 +743,9 @@ begin -- Channel_200 else FSM_RD_STATE <= FLUSH_D; end if; + if ringBuffer_data_out(31 downto 29) = "011" then + epoch_value <= ringBuffer_data_out; + end if; -- when READOUT_EPOCH => -- first epoch word should be readout @@ -773,9 +776,6 @@ begin -- Channel_200 -- edge). FSM_DATA_OUTPUT : process (FSM_RD_STATE, TRG_WIN_END_RDO_IN, ringBuffer_data_out, epoch_value) begin - trg_win_end_rdo_flag <= trg_win_end_rdo_flag; - epoch_value <= epoch_value; - case FSM_RD_STATE is when IDLE => fifo_data <= (others => '0'); @@ -787,7 +787,7 @@ begin -- Channel_200 fifo_data_valid <= '0'; ringBuffer_rd_data <= '0'; if TRG_WIN_END_RDO_IN = '1' then - trg_win_end_rdo_flag <= '1'; + trg_win_end_rdo_flag_f <= '1'; end if; fsm_rd_debug <= x"2"; when FLUSH_B => @@ -795,7 +795,7 @@ begin -- Channel_200 fifo_data_valid <= '0'; ringBuffer_rd_data <= '0'; if TRG_WIN_END_RDO_IN = '1' then - trg_win_end_rdo_flag <= '1'; + trg_win_end_rdo_flag_f <= '1'; end if; fsm_rd_debug <= x"3"; when FLUSH_C => @@ -803,16 +803,13 @@ begin -- Channel_200 fifo_data_valid <= '0'; ringBuffer_rd_data <= '0'; if TRG_WIN_END_RDO_IN = '1' then - trg_win_end_rdo_flag <= '1'; + trg_win_end_rdo_flag_f <= '1'; end if; fsm_rd_debug <= x"4"; when FLUSH_D => fifo_data <= (others => '0'); fifo_data_valid <= '0'; ringBuffer_rd_data <= '0'; - if ringBuffer_data_out(31 downto 29) = "011" then - epoch_value <= ringBuffer_data_out; - end if; fsm_rd_debug <= x"5"; when READOUT_EPOCH => fifo_data <= epoch_value; @@ -820,11 +817,11 @@ begin -- Channel_200 ringBuffer_rd_data <= '1'; fsm_rd_debug <= x"6"; when READOUT_DATA_A => - fifo_data <= (others => '0'); - fifo_data_valid <= '0'; - ringBuffer_rd_data <= '1'; - trg_win_end_rdo_flag <= '0'; - fsm_rd_debug <= x"7"; + fifo_data <= (others => '0'); + fifo_data_valid <= '0'; + ringBuffer_rd_data <= '1'; + trg_win_end_rdo_flag_f <= '0'; + fsm_rd_debug <= x"7"; when READOUT_DATA_B => fifo_data <= (others => '0'); fifo_data_valid <= '0'; @@ -847,6 +844,8 @@ begin -- Channel_200 end case; end process FSM_DATA_OUTPUT; + trg_win_end_rdo_flag <= trg_win_end_rdo_flag_f when rising_edge(CLK_100); + FIFO_DATA_OUT <= fifo_data; FIFO_DATA_VALID_OUT <= fifo_data_valid; -- 2.43.0