From ffc94e7882c9252c0747664c09eea82d34f8a2ba Mon Sep 17 00:00:00 2001 From: Hadaq in Frankfurt Date: Wed, 27 Mar 2013 10:39:50 +0100 Subject: [PATCH] tried to reproduce error in simulation. failed up to now. bn --- vhdl/code/jtag_cmd_m26c.vhd | 47 ++++++++---- .../jtag_tdo_compare_counttotal_noram_m10.vhd | 25 +++--- ...jtag_cmd_m26c_test_regvaluesfrominput2.vhd | 52 +++++++++---- vhdl/code/tb/jtag_tap_mi26_hard.vhd | 14 +++- vhdl/sim/sim_jtag_cmd_m26c.prj.mpf | 76 +++++++++---------- 5 files changed, 136 insertions(+), 78 deletions(-) diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd index 46bf572..5cbaa1b 100644 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ b/vhdl/code/jtag_cmd_m26c.vhd @@ -1270,6 +1270,12 @@ signal begin_count_data_changed :std_logic; signal end_count_read_errors :std_logic; signal end_count_write_errors :std_logic; signal end_count_data_changed :std_logic; +signal begin_count_read_errors_next :std_logic; +signal begin_count_write_errors_next :std_logic; +signal begin_count_data_changed_next :std_logic; +signal end_count_read_errors_next :std_logic; +signal end_count_write_errors_next :std_logic; +signal end_count_data_changed_next :std_logic; signal last_read_error : std_logic; signal last_write_error : std_logic; signal last_data_changed : std_logic; @@ -2459,6 +2465,12 @@ begin run_requested <= '0'; write_once_requested <= '0'; write_once_count <= (others =>'0'); + begin_count_read_errors <= '0'; + begin_count_write_errors <= '0'; + begin_count_data_changed <= '0'; + end_count_read_errors <= '0'; + end_count_write_errors <= '0'; + end_count_data_changed <= '0'; -- INSERTLABEL: SYNCHRONOUS reset else m26cs_state <= m26cs_state_next; @@ -2487,6 +2499,13 @@ begin run_requested <= run_requested_next; write_once_requested <= write_once_requested_next; write_once_count <= write_once_count_next; + begin_count_read_errors <= begin_count_read_errors_next; + begin_count_write_errors <= begin_count_write_errors_next; + begin_count_data_changed <= begin_count_data_changed_next; + end_count_read_errors <= end_count_read_errors_next; + end_count_write_errors <= end_count_write_errors_next; + end_count_data_changed <= end_count_data_changed_next; + -- INSERTLABEL: SYNCHRONOUS update end if; end if; @@ -2526,12 +2545,12 @@ begin crc_error_on_last_check_next <= crc_error_on_last_check; last_run_successful_next <= last_run_successful; last_run_successful_tmp_next <= last_run_successful_tmp; - begin_count_read_errors <= '0'; -- added 201210 - begin_count_write_errors <= '0'; -- added 201210 - begin_count_data_changed <= '0'; -- added 201210 - end_count_read_errors <= '0'; -- added 201210 - end_count_write_errors <= '0'; -- added 201210 - end_count_data_changed <= '0'; -- added 201210 + begin_count_read_errors_next <= '0'; -- added 201210 + begin_count_write_errors_next <= '0'; -- added 201210 + begin_count_data_changed_next <= '0'; -- added 201210 + end_count_read_errors_next <= '0'; -- added 201210 + end_count_write_errors_next <= '0'; -- added 201210 + end_count_data_changed_next <= '0'; -- added 201210 request_reset_next <= request_reset; reset_wait_next <= reset_wait; run_requested_next <= run_requested; @@ -2626,7 +2645,7 @@ begin ram1a_select_next <= "01"; -- select jtag_write_ram1a_a ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b ram2_select_next <= '0'; -- tdo_compare_count - begin_count_data_changed <= '1';-- added 201210 + begin_count_data_changed_next <= '1';-- added 201210 m26cs_state_next <= M26CSS_DATA_CHANGED_BEGIN; end if; end if; @@ -2634,7 +2653,7 @@ begin m26cs_state_next <= M26CSS_DATA_CHANGED_WAIT; when M26CSS_DATA_CHANGED_WAIT => if(jtag_write_last_tck_cycle = '1' or jtag_write_idle = '1') then - end_count_data_changed <= '1'; -- added 201210 + end_count_data_changed_next <= '1'; -- added 201210 m26cs_state_next <= M26CSS_BLANK_RAM3A_WAIT; end if; when M26CSS_BLANK_RAM3A_WAIT => @@ -2680,7 +2699,7 @@ begin ram1a_select_next <= "00"; -- select jtag_read_ram1a_a ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator) - begin_count_read_errors <= '1'; -- added 201210 + begin_count_read_errors_next <= '1'; -- added 201210 m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator) -- else -- trigger_begin_bypassreg_next <= '1'; @@ -2710,14 +2729,14 @@ begin ram1a_select_next <= "00"; -- select jtag_read_ram1a_a ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator) - begin_count_read_errors <= '1'; -- added 201210 + begin_count_read_errors_next <= '1'; -- added 201210 m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator) else ram2_select_next <= '0'; -- tdo_compare_count ram1a_select_next <= "00"; -- select jtag_read_ram1a_a ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b trigger_jtag_read_next <= '1'; - begin_count_read_errors <= '1'; -- added 201210 + begin_count_read_errors_next <= '1'; -- added 201210 m26cs_state_next <= M26CSS_READ1_BEGIN; end if; end if; @@ -2726,7 +2745,7 @@ begin m26cs_state_next <= M26CSS_READ1_WAIT; when M26CSS_READ1_WAIT => if(jtag_read_idle = '1') then -- removed (jtag_read_last_tck_cycle = '1' or ) because writing to RAM needs time - end_count_read_errors <= '1'; -- added 201210 + end_count_read_errors_next <= '1'; -- added 201210 if(breakpoint_active(4) = '1') then --stay in state --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; @@ -2790,7 +2809,7 @@ begin --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; else trigger_jtag_write_next <= '1'; - begin_count_write_errors <= '1'; -- added 201210 + begin_count_write_errors_next <= '1'; -- added 201210 m26cs_state_next <= M26CSS_WRITE2_BEGIN; end if; end if; @@ -2798,7 +2817,7 @@ begin m26cs_state_next <= M26CSS_WRITE2_WAIT; when M26CSS_WRITE2_WAIT => if(jtag_write_idle = '1') then - end_count_write_errors <= '1'; -- added 201210 + end_count_write_errors_next <= '1'; -- added 201210 if(breakpoint_active(7) = '1') then --stay in state --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; diff --git a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd b/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd index 9a89cad..9e0fbf1 100644 --- a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd +++ b/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd @@ -63,19 +63,22 @@ architecture jtag_tdo_compare_counttotal_noram_m10_arch of jtag_tdo_compare_coun signal count_i_lookingforerrors : std_logic_vector(numcounts-1 downto 0); signal sampling_error_count : unsigned(se_counter_width-1 downto 0); - - signal counts : unsigned(numcounts*diff_counter_width-1 downto 0); + type counts_array_t is array (numcounts-1 downto 0) of unsigned(diff_counter_width-1 downto 0); + signal counts : counts_array_t; signal SAMPLE_PULSE3_D2 : std_logic; begin -COUNTS_OUT <= std_logic_vector(counts); +COUNTS_OUT_ALL: for i in 0 to numcounts-1 generate + COUNTS_OUT(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= std_logic_vector(counts(i)); +end generate; + SAMPLING_ERRORS_COUNT_OUT <= std_logic_vector(sampling_error_count); LAST_VALUES_OUT <= count_i_errors_occured; -ALL_PROC : process (CLK_IN) +ONE_PROC: process (CLK_IN) variable i : integer; begin if (rising_edge(CLK_IN)) then - for i in 0 to numcounts-1 loop + ALL_PROC: for i in 0 to numcounts-1 loop if(ENABLE_COUNTERS_IN = '1') then if(SAMPLE_PULSE3_D2 = '1') then -- when this pulse arrives, the tdo-input from the last chip has been sampled if(not(TDO_SAMPLED_IN = TDO_EXPECTED_IN)) then @@ -97,15 +100,15 @@ begin count_i_lookingforerrors(i) <= '0'; -- stop looking for errors if(count_i_errors_occured(i) = '1') then -- increment count - counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= counts(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) + 1; + counts(i) <= counts(i) + 1; end if; end if; + if(RESET_IN = '1') then + count_i_errors_occured(i) <= '0'; + count_i_lookingforerrors(i) <= '0'; + counts(i) <= (others => '0'); + end if; end loop; - if(RESET_IN = '1') then - count_i_errors_occured <= (others => '0'); - count_i_lookingforerrors <= (others => '0'); - counts <= (others => '0'); - end if; end if; end process; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd index fd4ba37..974316a 100644 --- a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd +++ b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd @@ -58,9 +58,8 @@ end component; component jtag_cmd_m26c is generic( MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.) - MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. - MAX_REGLEN : integer := 4095; -- naximum register length. - + MAX_REGISTERS : integer := 14; -- maximum number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. + MAX_REGLEN : integer := 4095; -- maximum number of bits for one register. Should be chosen as 2^n-1 WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED. READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set @@ -72,7 +71,8 @@ component jtag_cmd_m26c is RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit. -- GLOBAL_JTAG_COUNTER_BITS : integer := 10; -- JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width - JTAG_TDO_EXPECTED_MAXDELAY : integer := 3 -- set range to 0..value for delay of expected TDO value + JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value + RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz ); port( CLK_IN : in std_logic; @@ -94,11 +94,13 @@ component jtag_cmd_m26c is BUS_WRITE_ACK_OUT : out std_logic; BUS_UNKNOWN_ADDR_OUT : out std_logic; + --OFF_SPILL_IN : in std_logic; RUN_REQUEST_IN : in std_logic; WRITE_ONCE_REQUEST_IN : in std_logic; MY_STATUS_OUT : out std_logic_vector(8 downto 0); --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); + REQUEST_RESET_OUT : out std_logic; IDLE_OUT : out std_logic; PROG_JTAG_FINISHED_OUT:out std_logic; READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); @@ -202,6 +204,8 @@ signal tap_registers : TAP_REGISTERS_ARRAY; signal registers_match : std_logic; -- contains result of asynchronous check, if registers input to the JTAG-Chain-Controller match -- the output registers of the simulated MIMOSA-26 sensors signal crc32_match_out : std_logic; +signal reset_request : std_logic; +signal taps_reset : std_logic; --signal data_in, ready_for_cmd_out, data_out, data_arrived_out : std_logic; begin crc32_1: CRC_32 port map( @@ -229,6 +233,7 @@ jtag_test1 : jtag_cmd_m26c port map( CLK_IN => clk_in, BUS_UNKNOWN_ADDR_OUT => bus_unknown_addr_out, RUN_REQUEST_IN => trigger_jtag_write, WRITE_ONCE_REQUEST_IN => '0', + REQUEST_RESET_OUT => reset_request, IDLE_OUT => idle_out, PROG_JTAG_FINISHED_OUT => prog_jtag_finished_out ); @@ -238,7 +243,7 @@ port map (TCK_EMU => jtag_tck_out, TMS_EMU => jtag_tms_out, TDI_EMU => jtag_tdi_out, TDO_EMU => jtag1_out, - TRSTB_EMU => trstb, + TRSTB_EMU => taps_reset, REGISTERS_OUT => tap_registers(2) ); tap2: jtag_tap_mi26_hard @@ -246,7 +251,7 @@ port map (TCK_EMU => jtag_tck_out, TMS_EMU => jtag_tms_out, TDI_EMU => jtag1_out, TDO_EMU => jtag2_out, - TRSTB_EMU => trstb, + TRSTB_EMU => taps_reset, REGISTERS_OUT => tap_registers(1) ); tap3: jtag_tap_mi26_hard @@ -254,7 +259,7 @@ port map (TCK_EMU => jtag_tck_out, TMS_EMU => jtag_tms_out, TDI_EMU => jtag2_out, TDO_EMU => jtag_tdo_in, - TRSTB_EMU => trstb, + TRSTB_EMU => taps_reset, REGISTERS_OUT => tap_registers(0) ); --top1 : top port map( TCK_EMU => jtag_tck_out, @@ -313,6 +318,7 @@ stimulus_statemachine : process (CLK_IN) begin if(rising_edge(CLK_IN)) then phase <= phase + 1; + taps_reset <= '0'; case phase is when x"000" => if( not(TRIGGER_IN = '1')) then @@ -320,11 +326,12 @@ begin end if; when x"001" => - trstb <= '1'; + --trstb <= '1'; + taps_reset <= '1'; when x"002" => - trstb <= '0'; - + --trstb <= '0'; + taps_reset <= '0'; when x"003" => chip <= (others => '0'); when x"004" => @@ -804,17 +811,33 @@ begin -- --jtag_tdo_in <= '0'; when x"066" => if not (idle_out = '1') then + if(reset_request = '1') then + taps_reset <= '1'; + end if; phase <= phase; -- wait end if; when x"067" => trigger_jtag_write <= '1'; + taps_reset <= '0'; when x"068" => - if not (idle_out = '0') then - phase <= phase; -- wait - end if; + when x"069" => trigger_jtag_write <= '0'; when x"06A" => + if (idle_out = '1') then + trigger_jtag_write <= '1'; + else + phase <= phase; + end if; + when x"06B" => + if not (idle_out = '0') then + phase <= phase; -- wait + end if; + when x"06C" => + trigger_jtag_write <= '0'; + if(reset_request = '1') then + taps_reset <= '1'; + end if; phase <= phase; -- end when others => phase <= x"000"; @@ -831,7 +854,8 @@ begin statuscounter <= (others => '0'); crc32_1_data_in <= x"00000000"; crc32_1_clk_en <= '0'; - trstb <= '1'; + --trstb <= '1'; + taps_reset <= '1'; crc32_reset_in <= '1'; phase <= x"000"; chip <= (others => '0'); diff --git a/vhdl/code/tb/jtag_tap_mi26_hard.vhd b/vhdl/code/tb/jtag_tap_mi26_hard.vhd index fc514da..5c5dd07 100644 --- a/vhdl/code/tb/jtag_tap_mi26_hard.vhd +++ b/vhdl/code/tb/jtag_tap_mi26_hard.vhd @@ -359,7 +359,19 @@ begin end loop; end case; end if; - + if(TRSTB_EMU = '1') then + register0 <= (others => '0'); + register1 <= (others => '0'); + register2 <= (others => '0'); + register3 <= (others => '0'); + register4 <= (others => '0'); + register5 <= (others => '0'); + register6 <= (others => '0'); + register7 <= (others => '0'); + register8 <= (others => '0'); + register9 <= (others => '0'); + register10 <= (others => '0'); + end if; end process; tap_output: process (TCK_EMU, TRSTB_EMU) diff --git a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf b/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf index a8477a2..c2547d0 100644 --- a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf +++ b/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf @@ -626,7 +626,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 2 ms +RunLength = 5 ms ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1652,9 +1652,9 @@ Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_2 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_components.vhd Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_3 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363802534 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1364208502 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_4 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363807206 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363972805 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_5 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_count_m10.vhd Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_6 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tck_out_component.vhd @@ -1662,55 +1662,55 @@ Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v Project_File_7 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_pulses.vhd Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_tap_mi26_hard.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363806490 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 31 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1364208958 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = /local/bneumann/vhdl/jtag_proj/NEW/trb3/mvdjtag/version.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363372374 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363972809 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 29 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_10 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_constants.vhd Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_11 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_dp.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_12 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_data_to_ram_m10.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_13 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_std.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_11 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_data_to_ram_m10.vhd +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_12 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_dp.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_13 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_bypassreg_testchain_m10.vhd +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_14 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_delay_expected_values.vhd Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_bypassreg_testchain_m10.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_15 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_std.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_16 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_write_m10.vhd Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363371102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801035 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_18 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_writeport.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_19 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_read_m26devid_m10.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363798313 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_21 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_readport.vhd -Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363798313 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_18 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_read_m26devid_m10.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_19 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_writeport.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_20 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801035 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_21 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/blank_ram.vhd +Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_22 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_update_error_counts_ram3a.vhd Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_23 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/blank_ram.vhd -Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_23 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_readport.vhd +Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_24 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_cmd_m26c.vhd -Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363808130 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_25 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux4to1_readport.vhd -Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_26 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_misc.vhd -Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363970246 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_25 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_misc.vhd +Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_26 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux4to1_readport.vhd +Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_27 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/copy_ram.vhd Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_28 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_simulation_constants.vhd -Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801664 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_28 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_check_crc_ram1a.vhd +Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_29 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_init_ram1b.vhd Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_30 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_check_crc_ram1a.vhd -Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_31 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net16_regio_bus_handler.vhd -Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_32 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/crc_32.vhd -Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_30 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_simulation_constants.vhd +Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801664 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_31 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/crc_32.vhd +Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_32 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net16_regio_bus_handler.vhd +Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 -- 2.43.0