From 05ae9e1e1739daaa76b1c1faa5f334fdd39af380 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 27 Nov 2025 22:56:24 +0100 Subject: [PATCH] Add receiver for LUPO trigger to CTS --- cts/config_8SFP_RJAdapter.vhd | 2 +- cts/config_8SFP_RJAdapter_lupo.vhd | 215 ++++++++++++++++ cts/config_8TDC_R3B.vhd | 8 +- cts/config_compile_frankfurt.pl | 8 +- cts/config_simple.vhd | 4 +- cts/trb3sc_cts.prj | 5 +- cts/trb3sc_cts.vhd | 63 ++++- pinout/trb3sc_hub_ctsrj_lupo.lpf | 386 +++++++++++++++++++++++++++++ 8 files changed, 670 insertions(+), 21 deletions(-) create mode 100644 cts/config_8SFP_RJAdapter_lupo.vhd create mode 100644 pinout/trb3sc_hub_ctsrj_lupo.lpf diff --git a/cts/config_8SFP_RJAdapter.vhd b/cts/config_8SFP_RJAdapter.vhd index d03a374..ee5ea88 100644 --- a/cts/config_8SFP_RJAdapter.vhd +++ b/cts/config_8SFP_RJAdapter.vhd @@ -35,7 +35,7 @@ package config is constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_I2C : integer := c_YES; - constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic constant INCLUDE_TDC : integer := c_NO; diff --git a/cts/config_8SFP_RJAdapter_lupo.vhd b/cts/config_8SFP_RJAdapter_lupo.vhd new file mode 100644 index 0000000..7b6fe7c --- /dev/null +++ b/cts/config_8SFP_RJAdapter_lupo.vhd @@ -0,0 +1,215 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--design options: backplane or front SFP, with or without GBE + constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work + constant USE_ADDON : integer := c_YES; + constant USE_RJADAPT : integer := c_YES; --!!! Change pin-out file! + constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3C0"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62"; --62 for SFP, 63 for backplane + + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + + constant INCLUDE_LUPO_RECEIVER : integer := c_YES; --requires INCLUDE_TIMESTAMP_GENERATOR + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_YES; --c_NO,c_YES + + --input monitor and trigger generation logic + constant INCLUDE_TDC : integer := c_NO; + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 36 - USE_RJADAPT*12 - INCLUDE_LUPO_RECEIVER*2; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 36 - USE_RJADAPT*12 - INCLUDE_LUPO_RECEIVER*2; + + + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + + + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + + constant TRIGGER_COIN_COUNT : integer := 4; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 1; + constant TRIGGER_ADDON_COUNT : integer := 9; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 36 - USE_RJADAPT*12 - INCLUDE_LUPO_RECEIVER*2; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 2; +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + + type hub_mii_t is array(0 to 3) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 3) of hub_ct; + type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); + type intlist_t is array(0 to 7) of integer; +-- 0 opt. link opt. link +-- 0-7 SFP 1-8 +-- 1(8) CTS read-out internal 0 1 - X X O --downlink only +-- 2(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only + + --Order: + -- no backplane, no AddOn, 1x SFP, 1x GBE +-- -- -- -- no backplane, 4x AddOn, 1x SFP, 1x GBE + -- no backplane, 8x AddOn, 0x SFP, 1x GBE +-- -- -- -- backplane, 9x backplane, 1x GBE + constant SFP_NUM_ARR : hub_mii_t := (1,0,8,0); + constant INTERFACE_NUM_ARR : hub_mii_t := (1,5,8,10); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), +-- (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); + + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + constant CFG_MODE : integer := USE_ADDON*2;--*2 + USE_BACKPLANE; + + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(3 downto 0) := std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4)); + t(7 downto 7) := std_logic_vector(to_unsigned(USE_RJADAPT,1)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC + t(16 downto 16) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --data via GbE + t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE + t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); + t(26 downto 24) := std_logic_vector(to_unsigned(SFP_NUM_ARR(CFG_MODE),3)); --num SFPs with TrbNet + t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); + t(39 downto 39) := std_logic_vector(to_unsigned(1,1)); --contains CTS + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/cts/config_8TDC_R3B.vhd b/cts/config_8TDC_R3B.vhd index 5cfa7b0..726d381 100644 --- a/cts/config_8TDC_R3B.vhd +++ b/cts/config_8TDC_R3B.vhd @@ -12,9 +12,9 @@ package config is ------------------------------------------------------------------------------ --design options: backplane or front SFP, with or without GBE - constant USE_BACKPLANE : integer := c_NO; --c_YES doesn't work - constant USE_ADDON : integer := c_NO; - constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file! + constant USE_BACKPLANE : integer := c_NO; + constant USE_ADDON : integer := c_YES; + constant USE_RJADAPT : integer := c_YES; --!!! Change pin-out file! constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work --Runs with 120 MHz instead of 100 MHz @@ -35,7 +35,7 @@ package config is constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_I2C : integer := c_NO; - constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic constant INCLUDE_TDC : integer := c_YES; diff --git a/cts/config_compile_frankfurt.pl b/cts/config_compile_frankfurt.pl index 7714c11..40418d4 100644 --- a/cts/config_compile_frankfurt.pl +++ b/cts/config_compile_frankfurt.pl @@ -1,8 +1,9 @@ TOPNAME => "trb3sc_cts", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', -synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2', +lattice_path => '/d/jspc29/lattice/diamond/3.12', + synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2', +#synplify_path => '/d/jspc29/lattice/synplify/W-2024.09', #synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", @@ -10,7 +11,8 @@ nodelist_file => 'nodelist_frankfurt.txt', # pinout_file => 'trb3sc_hub_ctsrj', #with RJ adapter for I/O -pinout_file => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors + pinout_file => 'trb3sc_hub_ctsrj_lupo', #with RJ adapter for I/O and LUPO receiver +# pinout_file => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors # pinout_file => 'trb3sc_master', #with backplane diff --git a/cts/config_simple.vhd b/cts/config_simple.vhd index 05867f0..a60213b 100644 --- a/cts/config_simple.vhd +++ b/cts/config_simple.vhd @@ -69,9 +69,9 @@ package config is constant GEN_BUSY_OUTPUT : integer := c_NO; constant TRIGGER_COIN_COUNT : integer := 2; - constant TRIGGER_PULSER_COUNT : integer := 3; + constant TRIGGER_PULSER_COUNT : integer := 1; constant TRIGGER_RAND_PULSER : integer := 1; - constant TRIGGER_ADDON_COUNT : integer := 9; + constant TRIGGER_ADDON_COUNT : integer := 2; constant PERIPH_TRIGGER_COUNT : integer := 0; constant ADDON_LINE_COUNT : integer := 36 - USE_RJADAPT*12; --36 with Padiwa, 22 with RJ-adapter constant CTS_OUTPUT_MULTIPLEXERS : integer := 2; diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index 5728558..2e24e28 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -17,7 +17,7 @@ set_option -resource_sharing false # map options set_option -frequency 100 -set_option -fanout_limit 100 +set_option -fanout_limit 40 #100 set_option -disable_io_insertion 0 set_option -retiming 1 set_option -pipe 1 @@ -281,7 +281,8 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" add_file -vhdl -lib work "../../trb3/base/code/mbs_vulom_recv.vhd" add_file -vhdl -lib work "../../trb3/cts/source/r3b_timestamp_recv.vhd" add_file -vhdl -lib work "../../trb3sc/code/hadesspillmon.vhd" - +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_lupo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/clock_sense.vhd" #TDC add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 09d0f30..2d51357 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -26,10 +26,12 @@ entity trb3sc_cts is BACK_GPIO : inout std_logic_vector( 3 downto 0); SPARE_IN : in std_logic_vector( 1 downto 0); - INP : in std_logic_vector(31-12*USE_RJADAPT+64*USE_BACKPLANE downto 64*USE_BACKPLANE); + INP : in std_logic_vector(31-12*USE_RJADAPT+64*USE_BACKPLANE - 4*INCLUDE_LUPO_RECEIVER downto 64*USE_BACKPLANE); RJ_IO : out std_logic_vector( 3 downto 0); --0, inner RJ trigger output RJ_IO_IN : in std_logic_vector( 1 downto 0); REFOUT : out std_logic_vector( 8*USE_RJADAPT-1 downto 0); + X_IN : in std_logic_vector( 4*INCLUDE_LUPO_RECEIVER downto 3); + X_OUT : out std_logic_vector( 2*INCLUDE_LUPO_RECEIVER downto 1); --LED LED_GREEN : out std_logic; @@ -231,8 +233,9 @@ architecture trb3sc_arch of trb3sc_cts is signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; - signal hit_in_i : std_logic_vector(64 downto 1); - signal mbs_async_out : std_logic; + signal hit_in_i : std_logic_vector(64 downto 1); + signal mbs_async_out : std_logic; + signal timestamp_lupo_status : std_logic_vector(32*INCLUDE_LUPO_RECEIVER-1 downto 0); attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -868,10 +871,10 @@ end generate; THE_CTS : CTS generic map ( EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic - PLATTFORM => 1+USE_RJADAPT+2*USE_BACKPLANE, --TRB3sc+KEL+RJ45 + PLATTFORM => 1+USE_RJADAPT+2*USE_BACKPLANE+2*INCLUDE_LUPO_RECEIVER, --TRB3sc+KEL+RJ45 OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, ADDON_GROUPS => 1, - ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3+USE_BACKPLANE*18, others => 0) + ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3+USE_BACKPLANE*18-INCLUDE_LUPO_RECEIVER*2, others => 0) ) port map ( CLK => clk_sys, @@ -935,11 +938,17 @@ gen_inputs_kel : if USE_BACKPLANE = 0 and USE_RJADAPT = 0 generate cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0); cts_addon_triggers_in(34 + TRIG_GEN_OUTPUT_NUM - 1 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); end generate; -gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate +gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 and INCLUDE_LUPO_RECEIVER = c_NO generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0); cts_addon_triggers_in(22 + TRIG_GEN_OUTPUT_NUM - 1 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys); end generate; +gen_inputs_rj_lupo : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 and INCLUDE_LUPO_RECEIVER = c_YES generate + cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); + cts_addon_triggers_in(17 downto 2) <= INP(15 downto 0); + cts_addon_triggers_in(19 downto 18) <= X_IN(4) & X_IN(3); + cts_addon_triggers_in(20 + TRIG_GEN_OUTPUT_NUM - 1 downto 20) <= trigger_gen_outputs_i when rising_edge(clk_sys); +end generate; gen_inputs_bkpl : if USE_BACKPLANE = 1 generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(33 downto 2) <= INP(95 downto 64); @@ -956,7 +965,7 @@ end generate; --------------------------------------------------------------------------- -- Add timestamp generator --------------------------------------------------------------------------- - GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES generate + GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES and INCLUDE_LUPO_RECEIVER = c_NO generate THE_TIMESTAMP : entity work.timestamp_generator port map( CLK => clk_sys, @@ -970,8 +979,35 @@ end generate; BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM) ); end generate; + + GEN_TIMESTAMP : if INCLUDE_LUPO_RECEIVER = c_YES generate + THE_TIMESTAMP : entity work.timestamp_lupo + port map( + CLK => clk_sys, + CLEAR => reset_i, + + TIMER_CLOCK_IN => X_IN(3), + TIMER_RESET_IN => X_IN(4), + + TRIGGER_IN => cts_trigger_out, + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM), + STATUS_OUT => timestamp_lupo_status + ); + end generate; + + +gen_lupo_status : if INCLUDE_ETM = c_NO and INCLUDE_LUPO_RECEIVER = c_YES generate + cts_ext_status <= timestamp_lupo_status; +end generate; -- assert not(INCLUDE_ETM = c_YES and INCLUDE_TIMESTAMP_GENERATOR = c_YES) report "Timestamp generator and ETM can not be implemented at the same time (TODO: fix this)" severity failure; + + + assert not(INCLUDE_LUPO_RECEIVER = c_YES and INCLUDE_TIMESTAMP_GENERATOR = c_NO) report "Timestamp generator must be included for LUPO receiver)" severity failure; + assert not(INCLUDE_LUPO_RECEIVER = c_YES and USE_RJADAPT = c_NO) report "RJ adapter needed for LUPO receiver)" severity failure; + assert not(INCLUDE_LUPO_RECEIVER = c_YES and USE_BACKPLANE = c_YES) report "Backplane not compatible with LUPO receiver)" severity failure; + -- --------------------------------------------------------------------------- -- MBS receiver @@ -1024,8 +1060,8 @@ end generate; CLK_SENDER => CLK_SUPPL_PCLK, --125 Mhz RESET_IN => reset_i, - SERIAL_IN => RJ_IO_IN(1), - SERIAL_OUT => RJ_IO(2), + SERIAL_IN => INP(16), --RJ_IO_IN(1), + SERIAL_OUT => open, --INP(18), --RJ_IO(2), TRG_SYNC_OUT => cts_ext_trigger, BUS_RX => busr3b_rx, @@ -1188,10 +1224,19 @@ else generate RJ_IO(3) <= cts_monitor_out(1); end generate; +gen_busy_r3b : if GEN_BUSY_OUTPUT = c_YES and ETM_CHOICE = ETM_CHOICE_R3B and USE_RJADAPT = c_YES generate + RJ_IO(1) <= trigger_busy_i; +end generate; + gen_muxout_0 : if ETM_CHOICE /= ETM_CHOICE_R3B or INCLUDE_ETM = c_NO generate RJ_IO(2) <= cts_monitor_out(0); end generate; +gen_muxout_1 : if INCLUDE_LUPO_RECEIVER = c_YES generate + X_OUT(1) <= cts_monitor_out(0); + X_OUT(2) <= cts_monitor_out(1); +end generate; + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/pinout/trb3sc_hub_ctsrj_lupo.lpf b/pinout/trb3sc_hub_ctsrj_lupo.lpf new file mode 100644 index 0000000..0912766 --- /dev/null +++ b/pinout/trb3sc_hub_ctsrj_lupo.lpf @@ -0,0 +1,386 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# AddOn Connector +################################################################# + + LOCATE COMP "LED_HUB_LINKOK_1" SITE "AA2"; #was "DQLL0_0_P" 1 + LOCATE COMP "LED_HUB_RX_1" SITE "AA1"; + LOCATE COMP "LED_HUB_TX_1" SITE "AB2"; #was "DQLL0_1_P" 5 + LOCATE COMP "HUB_MOD0_1" SITE "AB1"; + LOCATE COMP "HUB_MOD1_1" SITE "AA4"; #was "DQLL0_2_P" 9 + LOCATE COMP "HUB_MOD2_1" SITE "AA3"; +# LOCATE COMP "HUB_RATESEL_1" SITE "AA10"; #was "DQSLL0_T" 13 + LOCATE COMP "HUB_TXDIS_1" SITE "AB9"; + LOCATE COMP "HUB_LOS_1" SITE "AA5"; #was "DQLL0_3_P" 17 +# LOCATE COMP "HUB_TXFAULT_1" SITE "AB5"; + + LOCATE COMP "LED_HUB_LINKOK_2" SITE "Y7"; #was "DQLL0_4_P" 21 + LOCATE COMP "LED_HUB_RX_2" SITE "AA7"; + LOCATE COMP "LED_HUB_TX_2" SITE "AC5"; #was "DQLL2_0_P" 25 + LOCATE COMP "HUB_MOD0_2" SITE "AC4"; + LOCATE COMP "HUB_MOD1_2" SITE "AC2"; #was "DQLL2_1_P" 29 + LOCATE COMP "HUB_MOD2_2" SITE "AC1"; +# LOCATE COMP "HUB_RATESEL_2" SITE "AB4"; #was "DQLL2_2_P" 33 + LOCATE COMP "HUB_TXDIS_2" SITE "AB3"; + LOCATE COMP "HUB_LOS_2" SITE "AD5"; #was "DQSLL2_T" 37 +# LOCATE COMP "HUB_TXFAULT_2" SITE "AE5"; + + LOCATE COMP "LED_HUB_LINKOK_3" SITE "AE4"; #was "DQLL3_0_P" 2 + LOCATE COMP "LED_HUB_RX_3" SITE "AE3"; + LOCATE COMP "LED_HUB_TX_3" SITE "AB10"; #was "DQLL3_1_P" 6 + LOCATE COMP "HUB_MOD0_3" SITE "AC10"; + LOCATE COMP "HUB_MOD1_3" SITE "AE2"; #was "DQLL3_2_P" 10 + LOCATE COMP "HUB_MOD2_3" SITE "AE1"; +# LOCATE COMP "HUB_RATESEL_3" SITE "AJ1"; #was "DQSLL3_T" 14 + LOCATE COMP "HUB_TXDIS_3" SITE "AK1"; + LOCATE COMP "HUB_LOS_3" SITE "AD4"; #was "DQLL3_3_P" 18 +# LOCATE COMP "HUB_TXFAULT_3" SITE "AD3"; + + LOCATE COMP "LED_HUB_LINKOK_4" SITE "AC9"; #was "DQLL3_4_P" 22 + LOCATE COMP "LED_HUB_RX_4" SITE "AC8"; + LOCATE COMP "LED_HUB_TX_4" SITE "Y2"; #was "DQLL1_0_P" 26 + LOCATE COMP "HUB_MOD0_4" SITE "Y1"; + LOCATE COMP "HUB_MOD1_4" SITE "W4"; #was "DQLL1_1_P" 30 + LOCATE COMP "HUB_MOD2_4" SITE "W3"; +# LOCATE COMP "HUB_RATESEL_4" SITE "W2"; #was "DQLL1_2_P" 34 + LOCATE COMP "HUB_TXDIS_4" SITE "W1"; + LOCATE COMP "HUB_LOS_4" SITE "W6"; #was "DQSLL1_T" 38 +# LOCATE COMP "HUB_TXFAULT_4" SITE "Y6"; + + LOCATE COMP "LED_HUB_LINKOK_5" SITE "AD31"; #was "DQLR1_0_P" 169 + LOCATE COMP "LED_HUB_RX_5" SITE "AD30"; + LOCATE COMP "LED_HUB_TX_5" SITE "AB32"; #was "DQLR1_1_P" 173 + LOCATE COMP "HUB_MOD0_5" SITE "AB31"; + LOCATE COMP "HUB_MOD1_5" SITE "AE34"; #was "DQLR1_2_P" 177 + LOCATE COMP "HUB_MOD2_5" SITE "AE33"; +# LOCATE COMP "HUB_RATESEL_5" SITE "AB26"; #was "DQSLR1_T" 181 + LOCATE COMP "HUB_TXDIS_5" SITE "AB25"; + LOCATE COMP "HUB_LOS_5" SITE "AD33"; #was "DQLR1_3_P" 185 +# LOCATE COMP "HUB_TXFAULT_5" SITE "AD34" + + LOCATE COMP "LED_HUB_LINKOK_6" SITE "W30"; #was "DQLR2_0_P" 170 + LOCATE COMP "LED_HUB_RX_6" SITE "W29"; + LOCATE COMP "LED_HUB_TX_6" SITE "W27"; #was "DQLR2_1_P" 174 + LOCATE COMP "HUB_MOD0_6" SITE "W26"; + LOCATE COMP "HUB_MOD1_6" SITE "W34"; #was "DQLR2_2_P" 178 + LOCATE COMP "HUB_MOD2_6" SITE "W33"; +# LOCATE COMP "HUB_RATESEL_6" SITE "Y30"; #was "DQSLR2_T" 182 + LOCATE COMP "HUB_TXDIS_6" SITE "AA29"; + LOCATE COMP "HUB_LOS_6" SITE "Y34"; #was "DQLR2_3_P" 186 +# LOCATE COMP "HUB_TXFAULT_6" SITE "Y33"; + + LOCATE COMP "LED_HUB_LINKOK_7" SITE "AB34"; #was "DQLR0_0_P" 129 + LOCATE COMP "LED_HUB_RX_7" SITE "AB33"; + LOCATE COMP "LED_HUB_TX_7" SITE "AA25"; #was "DQLR0_1_P" 133 + LOCATE COMP "HUB_MOD0_7" SITE "AA26"; + LOCATE COMP "HUB_MOD1_7" SITE "AC34"; #was "DQLR0_2_P" 137 + LOCATE COMP "HUB_MOD2_7" SITE "AC33"; +# LOCATE COMP "HUB_RATESEL_7" SITE "AB30"; #was "DQSLR0_T" 141 + LOCATE COMP "HUB_TXDIS_7" SITE "AC30"; + LOCATE COMP "HUB_LOS_7" SITE "L26"; #was "DQUR0_0_P" 105 #SITE "AA31"; #was "DQLR0_3_P" 145 +# LOCATE COMP "HUB_TXFAULT_7" SITE "AA30" + + LOCATE COMP "LED_HUB_LINKOK_8" SITE "T32"; #was "DQUR2_0_P" 130 + LOCATE COMP "LED_HUB_RX_8" SITE "T31"; + LOCATE COMP "LED_HUB_TX_8" SITE "T26"; #was "DQUR2_1_P" 134 + LOCATE COMP "HUB_MOD0_8" SITE "T27"; + LOCATE COMP "HUB_MOD1_8" SITE "U32"; #was "DQUR2_2_P" 138 + LOCATE COMP "HUB_MOD2_8" SITE "U31"; +# LOCATE COMP "HUB_RATESEL_8" SITE "T30"; #was "DQSUR2_T" 142 + LOCATE COMP "HUB_TXDIS_8" SITE "U30"; + LOCATE COMP "HUB_LOS_8" SITE "T34"; #was "DQUR2_3_P" 146 +# LOCATE COMP "HUB_TXFAULT_8" SITE "T33"; + +DEFINE PORT GROUP "HUB_group" "HUB*" ; +IOBUF GROUP "HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; +DEFINE PORT GROUP "LED_HUB_group" "LED_HUB*" ; +IOBUF GROUP "LED_HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Pin-header IO +################################################################# + + +# LOCATE COMP "DAC_IN_SDI_5" SITE "P7"; +# LOCATE COMP "DAC_IN_SDI_6" SITE "M29"; +# DEFINE PORT GROUP "IN_group" "DAC_IN*" ; +# IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +# +# +# LOCATE COMP "DAC_OUT_SDO_5" SITE "R8"; +# LOCATE COMP "DAC_OUT_SCK_5" SITE "R2"; +# LOCATE COMP "DAC_OUT_CS_5" SITE "P9"; +# LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28"; +# LOCATE COMP "DAC_OUT_SCK_6" SITE "M34"; +# LOCATE COMP "DAC_OUT_CS_6" SITE "L28"; +# DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ; +# IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF; + +LOCATE COMP "INP_0" SITE "AL34"; #57 A3_P +LOCATE COMP "INP_1" SITE "AL31"; #53 A4_P +LOCATE COMP "INP_2" SITE "AP29"; #41 B3_P +LOCATE COMP "INP_3" SITE "P7"; #33 B4_P +LOCATE COMP "INP_4" SITE "T2"; #31 C3_P +LOCATE COMP "INP_5" SITE "T9"; #29 C4_P +LOCATE COMP "INP_6" SITE "AM6"; #11 D3_P +LOCATE COMP "INP_7" SITE "AN1"; #5 D4_P +LOCATE COMP "INP_8" SITE "AL32"; #63 G3_P +LOCATE COMP "INP_9" SITE "AE32"; #67 G4_P +LOCATE COMP "INP_10" SITE "AN34"; #45 H3_P +LOCATE COMP "INP_11" SITE "AN32"; #49 H4_P +LOCATE COMP "INP_12" SITE "V4"; #25 I3_P +LOCATE COMP "INP_13" SITE "V5"; #27 I4_P +LOCATE COMP "INP_14" SITE "AL4"; #13 J3_P +LOCATE COMP "INP_15" SITE "AJ2"; #17 J4_P +LOCATE COMP "INP_16" SITE "AH33"; #61 X1_P +# LOCATE COMP "INP_17" SITE "AE30"; #69 X2_P ##comment for R3B w/ AddOn +LOCATE COMP "INP_18" SITE "AD26"; #71 X3_P +LOCATE COMP "INP_19" SITE "M29"; #73 X4_P + +# LOCATE COMP "KEL_10" SITE "AL3"; #19 D2_P +# LOCATE COMP "KEL_11" SITE "AD9"; #21 I2_P +# LOCATE COMP "KEL_19" SITE "R2"; #37 H2_P +# LOCATE COMP "KEL_20" SITE "P9"; #39 B2_P +# LOCATE COMP "KEL_26" SITE "AM29"; #51 G2_P +# LOCATE COMP "KEL_28" SITE "AL30"; #55 A2_P +# LOCATE COMP "KEL_33" SITE "AF32"; #65 GND +# LOCATE COMP "KEL_38" SITE "AC28"; #75 +# LOCATE COMP "KEL_39" SITE "M34"; #77 +# LOCATE COMP "KEL_40" SITE "L28"; #79 +# LOCATE COMP "KEL_4" SITE "AN3"; #7 J2_P +# LOCATE COMP "KEL_8" SITE "AJ5"; #15 C2_P + +LOCATE COMP "REFOUT_0" SITE "AJ31"; #59 A1_P +LOCATE COMP "REFOUT_1" SITE "AP33"; #43 B1_P +LOCATE COMP "REFOUT_2" SITE "AJ4"; #23 C1_P +LOCATE COMP "REFOUT_3" SITE "AP2"; #3 D1_P +LOCATE COMP "REFOUT_4" SITE "AP31"; #47 G1_P +LOCATE COMP "REFOUT_5" SITE "R8"; #35 H1_P +LOCATE COMP "REFOUT_6" SITE "AL5"; #9 I1_P +LOCATE COMP "REFOUT_7" SITE "AP5"; #1 J1_P + +DEFINE PORT GROUP "REFOUT_group" "REFOUT*" ; +IOBUF GROUP "REFOUT_group" IO_TYPE=LVDS25 ; + +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_0" SITE "R28"; +#LOCATE COMP "RJ_IO_1" SITE "R31"; #normal RJ on board +LOCATE COMP "RJ_IO_1" SITE "AE30"; #X_1 for R3B with AddOn +LOCATE COMP "RJ_IO_2" SITE "R26"; +LOCATE COMP "RJ_IO_3" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; + +LOCATE COMP "RJ_IO_IN_0" SITE "R28"; +LOCATE COMP "RJ_IO_IN_1" SITE "R31"; +IOBUF PORT "RJ_IO_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "RJ_IO_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + +################################################################# +# Backplane I/O +################################################################# +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +LOCATE COMP "BACK_GPIO_4" SITE "D27"; +LOCATE COMP "BACK_GPIO_5" SITE "E27"; +LOCATE COMP "BACK_GPIO_6" SITE "B28"; +LOCATE COMP "BACK_GPIO_7" SITE "A28"; +LOCATE COMP "BACK_GPIO_8" SITE "A26"; +LOCATE COMP "BACK_GPIO_9" SITE "A27"; +LOCATE COMP "BACK_GPIO_10" SITE "A29"; +LOCATE COMP "BACK_GPIO_11" SITE "A30"; +LOCATE COMP "BACK_GPIO_12" SITE "H26"; +LOCATE COMP "BACK_GPIO_13" SITE "H25"; +LOCATE COMP "BACK_GPIO_14" SITE "A31"; +LOCATE COMP "BACK_GPIO_15" SITE "B31"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "BACK_LVDS_0" SITE "V2"; +LOCATE COMP "BACK_LVDS_1" SITE "T4"; +# LOCATE COMP "BACK_LVDS_0_N" SITE "V1"; +# LOCATE COMP "BACK_LVDS_1_N" SITE "T3"; +DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ; +IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25; + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Test I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; -- 2.51.0