From fa4c9078c75328d3ebdd5cf1fa7a7331b11dd206 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 31 Mar 2026 13:09:09 +0200 Subject: [PATCH] add Mimosis readout for FEB --- mimosis/code/InputStageMulti.vhd | 246 ++++++++++++++++++++ mimosis/code/MimosisInputMulti.vhd | 356 +++++++++++++++++++++++++++++ mimosis_feb/par.p2t | 2 +- mimosis_feb/trb5sc_mimosis.prj | 20 +- mimosis_feb/trb5sc_mimosis.vhd | 312 +++++++++++++------------ pinout/trb5sc_mimosisfeb.lpf | 112 ++++----- vldb/code/gbt_core.vhd | 37 ++- 7 files changed, 873 insertions(+), 212 deletions(-) create mode 100644 mimosis/code/InputStageMulti.vhd create mode 100644 mimosis/code/MimosisInputMulti.vhd diff --git a/mimosis/code/InputStageMulti.vhd b/mimosis/code/InputStageMulti.vhd new file mode 100644 index 0000000..f3a5123 --- /dev/null +++ b/mimosis/code/InputStageMulti.vhd @@ -0,0 +1,246 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity InputStageMulti is + generic( + INPUT_NUMBER : integer := 8 + ); + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + DIN : in std_logic_vector_array_8(0 to 7); + DOUT : out std_logic_vector(15 downto 0); + + ACTIVE : out std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of InputStageMulti is + + signal clk_rx : std_logic; + signal reset_i : std_logic; + signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0'); + + signal data_i : std_logic_vector(15 downto 0); + signal add_reg : std_logic_vector(31 downto 0); + + type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT); + type state_arrt is array (0 to 7) of state_t; + + type unsigned_arr is array(0 to 7) of unsigned(6 downto 0); + signal sample_good, sample_bad : unsigned_arr := (others => (others => '0')); + signal first_good, first_bad : unsigned_arr := (others => (others => '1')); + signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0')); + signal active_i : std_logic_vector(7 downto 0); + signal data_i_mult : std_logic_vector_array_16(0 to 7); + signal s_cflag_mult : std_logic_vector_array_8(0 to 7); + signal input_select : integer range 0 to 31; + +begin + +reset_i <= RESET when rising_edge(CLK); + +gen_inputs : for i in 0 to INPUT_NUMBER-1 generate + THE_IN : entity work.mimosis_inp + port map ( + clkin=>CLK, + reset=>reset_i, + sclk=>open, + data_cflag(7 downto 0)=>s_cflag_mult(i), + data_direction(7 downto 0)=>(others => '0'), + data_loadn(7 downto 0)=>s_loadn, + data_move(7 downto 0)=>s_move, + datain(7 downto 0)=>DIN(i), + q(15 downto 0)=>data_i_mult(i) + ); +end generate; + +data_i <= data_i_mult(input_select) when rising_edge(CLK); +s_cflag <= s_cflag_mult(input_select) when rising_edge(CLK); + +DOUT <= data_i; +ACTIVE <= and(active_i); + +gen_finders : for i in 0 to 7 generate + signal timer : unsigned(14 downto 0); + signal state : state_t; + signal count : unsigned(11 downto 0); + signal pos : unsigned(6 downto 0); + signal lastsample : std_logic; + signal train : unsigned(3 downto 0); + signal last : std_logic_vector(1 downto 0); + +begin + PROC_FIND : process begin + wait until rising_edge(CLK); + s_loadn(i) <= not add_reg(i+16); + active_i(i) <= '0'; + + case state is + when START => + timer <= 0; + count <= 0; + s_move(i) <= '0'; + state <= LISTEN; + + when LISTEN => + if timer(timer'left) = '1' then + state <= STEP; + if count >= 2047 and count <= 2049 then + sample_good(i) <= sample_good(i) + 1; + lastsample <= '1'; + if first_good(i) > pos then + first_good(i) <= pos; + end if; + if last_bad(i) < pos and lastsample = '0' then + last_bad(i) <= pos; + end if; + + else + lastsample <= '0'; + sample_bad(i) <= sample_bad(i) + 1; + if first_bad(i) > pos then + first_bad(i) <= pos; + end if; + if last_good(i) < pos and lastsample = '1' then + last_good(i) <= pos; + end if; + end if; + else + timer <= timer + 1; + end if; + + last <= data_i(i*2+1 downto i*2); + + if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and + data_i(i*2+1 downto i*2) = last then + train <= train + 1; + else + train <= x"0"; + end if; + + if train = x"3" then + count <= count + 1; + end if; + + + when STEP => + if s_cflag(i) = '0' then + s_move(i) <= '1'; + pos <= pos + 1; + state <= START; + else + state <= CALC; + s_loadn(i) <= '0'; + end if; + + when CALC => + if first_good(i) = "0000000" then + pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; + else + pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1); + end if; + state <= SET0; + + when SET0 => + posi(i) <= pos; + state <= SET1; + + when SET1 => + state <= SET2; + s_move(i) <= '1'; + + when SET2 => + s_move(i) <= '0'; + if pos = 0 then + state <= ENDWAIT; + else + state <= SET3; + pos <= pos - 1; + end if; + + when SET3 => + state <= SET1; + + when ENDWAIT => + active_i(i) <= '1'; + state <= ENDWAIT; + + end case; + + if reset_i = '1' or add_reg(0) = '1' then + state <= START; + pos <= 0; + s_loadn(i) <= '0'; + active_i(i) <= '0'; + sample_good(i) <= 0; + sample_bad(i) <= 0; + last_good(i) <= 0; + last_bad(i) <= 0; + first_good(i) <= (others => '1'); + first_bad(i) <= (others => '1'); + end if; + end process; +end generate; + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + addr := to_integer(unsigned(BUS_RX.addr(2 downto 0))); + if BUS_RX.write = '1' then + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.ack <= '1'; + add_reg <= BUS_RX.data; + elsif BUS_RX.addr(15 downto 0) = x"0011" then + BUS_TX.ack <= '1'; + input_select <= to_integer(unsigned(BUS_RX.data(4 downto 0))); + else + BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.data <= add_reg; + elsif BUS_RX.addr(15 downto 0) = x"0011" then + BUS_TX.data(4 downto 0) <= std_logic_vector(to_unsigned(input_select,5)); + elsif BUS_RX.addr(15 downto 4) = x"000" then + if BUS_RX.addr(3) = '0' then + BUS_TX.data(6 downto 0) <= std_logic_vector(sample_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(sample_bad(addr)); + BUS_TX.data(16) <= s_cflag(addr); + BUS_TX.data(20) <= active_i(addr); + BUS_TX.data(30 downto 24)<= std_logic_vector(posi(addr)); + else + BUS_TX.data(6 downto 0) <= std_logic_vector(first_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(last_good(addr)); + BUS_TX.data(22 downto 16) <= std_logic_vector(first_bad(addr)); + BUS_TX.data(30 downto 24) <= std_logic_vector(last_bad(addr)); + end if; + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + + end if; + end if; +end process; + + + + +end architecture; diff --git a/mimosis/code/MimosisInputMulti.vhd b/mimosis/code/MimosisInputMulti.vhd new file mode 100644 index 0000000..ba1a579 --- /dev/null +++ b/mimosis/code/MimosisInputMulti.vhd @@ -0,0 +1,356 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity MimosisInputMulti is + generic( + INPUT_NUMBER : integer := 8 + ); + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector_array_8(0 to 7); + + BUSRDO_RX : in READOUT_RX; + BUSRDO_TX : out READOUT_TX; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of MimosisInputMulti is + constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; + constant WORD_LIMIT : integer := 4000; + signal input_active_i : std_logic; + signal data_i : std_logic_vector(15 downto 0); + signal inp_i : std_logic_vector(7 downto 0); + signal word_i : std_logic_vector(31 downto 0); + signal word_valid : std_logic; + + signal businp_rx, busword_rx, busmimosis_rx : CTRLBUS_RX; + signal businp_tx, busword_tx, busmimosis_tx : CTRLBUS_TX; + + signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic; + signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic; + signal ct_fifo_data_out : std_logic_vector(31 downto 0); + + signal buffer_empty, buffer_full : std_logic; + signal buffer_write, buffer_read : std_logic; + signal buffer_valid, buffer_nextvalid : std_logic; + signal buffer_din, buffer_dout : std_logic_vector(31 downto 0); + signal buffer_fill : std_logic_vector(13 downto 0); + + type state_t is (IDLE,START_COPY, START_COPY2, COPY,FINISH,DONE); + signal state : state_t; + signal word_count : integer range 0 to 8191; + + signal frame_number : std_logic_vector(31 downto 0); + signal frame_length : std_logic_vector(15 downto 0); + signal count_words : unsigned(15 downto 0); + signal count_header : unsigned(31 downto 0); + signal count_trailer : unsigned(31 downto 0); + signal count_fe : unsigned(31 downto 0); + signal count_ff : unsigned(31 downto 0); + signal count_oof : unsigned(31 downto 0); + signal pulse_stats : std_logic_vector(31 downto 0); + signal buffer_blocked : std_logic; + type frame_state_t is (IDLE,HDR1,HDR2,HDR3,WRITING); + signal frame_state : frame_state_t; + + +begin + + THE_IN : entity work.InputStageMulti + port map ( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => INPUT, + DOUT => data_i, + ACTIVE => input_active_i, + + BUS_RX => businp_rx, + BUS_TX => businp_tx + ); + + + THE_WORDS: entity work.WordAlign + port map( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => data_i, + DOUT => word_i, + VALID => word_valid, + + ACTIVE => input_active_i, + + BUS_RX => busword_rx, + BUS_TX => busword_tx + ); + + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg + port map( + Data(31 downto 0) => word_i(31 downto 0), + Data(35 downto 32) => "0000", + WrClock => CLK, + RdClock => CLK_SYS, + WrEn => word_valid, + RdEn => ct_fifo_read, + Reset => RESET, + RPReset => RESET, + Q(31 downto 0) => ct_fifo_data_out(31 downto 0), + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + ct_fifo_read <= '1'; + ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS); + ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS); + +---------------------------------------------------------------------- +-- Frame Copy +---------------------------------------------------------------------- + +PROC_FRAMES : process begin + wait until rising_edge(CLK_SYS); + buffer_write <= '0'; + buffer_din <= ct_fifo_data_out; + + if ct_fifo_valid = '1' then + count_words <= count_words + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + count_fe <= count_fe + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + count_ff <= count_ff + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then + count_oof <= count_oof + 1; + end if; + + case frame_state is + when IDLE => + count_words <= (others => '0'); + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + frame_state <= HDR1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= '1' when buffer_full = '0' and state = IDLE else '0'; + buffer_blocked <= '0' when buffer_full = '0' and state = IDLE else '1'; + count_header <= count_header + 1; + end if; + when HDR1 => + if ct_fifo_valid = '1' then + frame_state <= HDR2; + frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_blocked; + end if; + when HDR2 => + if ct_fifo_valid = '1' then + frame_state <= HDR3; + buffer_din(23 downto 16) <= pulse_stats(7 downto 0); + buffer_din(7 downto 0) <= pulse_stats(15 downto 8); + buffer_write <= not buffer_blocked; + end if; + when HDR3 => + if ct_fifo_valid = '1' then + frame_state <= WRITING; + buffer_din(23 downto 16) <= pulse_stats(23 downto 16); + buffer_din(7 downto 0) <= pulse_stats(31 downto 24); + buffer_write <= not buffer_blocked; + end if; + when WRITING => + buffer_write <= ct_fifo_valid and not buffer_blocked; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + frame_state <= IDLE; + frame_length <= std_logic_vector(count_words); + count_trailer <= count_trailer + 1; + end if; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" and count_words >= x"0004" then + frame_state <= HDR1; + count_header <= count_header + 1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_full; + buffer_blocked <= buffer_full; + end if; + end case; + + end process; + + + +---------------------------------------------------------------------- +-- Main Fifo +---------------------------------------------------------------------- +THE_FIFO : entity work.fifo_36x8k_oreg + port map( + Data(31 downto 0) => buffer_din, + Clock => CLK_SYS, + WrEn => buffer_write, + RdEn => buffer_read, + Reset => RESET, + AmFullThresh => "0010000000000", + Q(31 downto 0) => buffer_dout, + WCNT => buffer_fill, + Empty => buffer_empty, + Full => open, + AlmostFull => buffer_full + ); + + buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS); + buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS); + +--------------------------------------------------------------------------- +-- Buffer Handler +--------------------------------------------------------------------------- +PROC_RDO : process begin + wait until rising_edge(CLK_SYS); +-- if state = IDLE and buffer_full = '1' then +-- buffer_read <= '1'; +-- else + buffer_read <= '0'; +-- end if; + + + BUSRDO_TX.busy_release <= '0'; + BUSRDO_TX.data_write <= '0'; + BUSRDO_TX.data_finished <= '0'; + + case state is + when IDLE => + if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then + state <= START_COPY; + buffer_read <= '1'; + word_count <= 0; + end if; + if BUSRDO_RX.invalid_trg = '1' then + state <= FINISH; + end if; + + when START_COPY => + state <= START_COPY2; + buffer_read <= '1'; + word_count <= word_count + 1; + + when START_COPY2 => + state <= COPY; + buffer_read <= '1'; + word_count <= word_count + 1; + + when COPY => + + if word_count = WORD_LIMIT or buffer_valid = '0' then + state <= FINISH; + else + buffer_read <= '1'; + word_count <= word_count + 1; + BUSRDO_TX.data <= buffer_dout; + BUSRDO_TX.data_write <= '1'; + end if; + + when FINISH => + BUSRDO_TX.data_finished <= '1'; + state <= DONE; + + when DONE => + BUSRDO_TX.busy_release <= '1'; + state <= IDLE; + end case; + +end process; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"), + PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 4, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => CLK_SYS, + RESET => RESET, + + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + + BUS_RX(0) => businp_rx, + BUS_RX(1) => busword_rx, + BUS_RX(2) => busmimosis_rx, + + BUS_TX(0) => businp_tx, + BUS_TX(1) => busword_tx, + BUS_TX(2) => busmimosis_tx, + STAT_DEBUG => open + ); + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '0'; + busmimosis_tx.nack <= '0'; + busmimosis_tx.data <= (others => '0'); + + if busmimosis_rx.write = '1' then + if busmimosis_rx.addr = x"0009" then + pulse_stats <= busmimosis_rx.data; + busmimosis_tx.ack <= '1'; + else + busmimosis_tx.unknown <= '1'; + end if; + elsif busmimosis_rx.read = '1' then + busmimosis_tx.ack <= '1'; + if busmimosis_rx.addr = x"0000" then + busmimosis_tx.data <= std_logic_vector(count_header); + elsif busmimosis_rx.addr = x"0001" then + busmimosis_tx.data <= std_logic_vector(count_trailer); + elsif busmimosis_rx.addr = x"0002" then + busmimosis_tx.data <= x"0000" & frame_length; + elsif busmimosis_rx.addr = x"0003" then + busmimosis_tx.data <= frame_number; + elsif busmimosis_rx.addr = x"0004" then + busmimosis_tx.data <= x"0000" & std_logic_vector(count_words); + elsif busmimosis_rx.addr = x"0005" then + busmimosis_tx.data <= x"0000" & "00" & buffer_fill; + elsif busmimosis_rx.addr = x"0006" then + busmimosis_tx.data <= std_logic_vector(count_fe); + elsif busmimosis_rx.addr = x"0007" then + busmimosis_tx.data <= std_logic_vector(count_ff); + elsif busmimosis_rx.addr = x"0008" then + busmimosis_tx.data <= std_logic_vector(count_oof); + elsif busmimosis_rx.addr = x"0009" then + busmimosis_tx.data <= pulse_stats; + else + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '1'; + + end if; + end if; +end process; + +end architecture; diff --git a/mimosis_feb/par.p2t b/mimosis_feb/par.p2t index acca99b..cf04f8e 100644 --- a/mimosis_feb/par.p2t +++ b/mimosis_feb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 20 +-t 1 -c 2 -e 2 -i 10 diff --git a/mimosis_feb/trb5sc_mimosis.prj b/mimosis_feb/trb5sc_mimosis.prj index 34ed411..9444a25 100644 --- a/mimosis_feb/trb5sc_mimosis.prj +++ b/mimosis_feb/trb5sc_mimosis.prj @@ -288,12 +288,28 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd" add_file -vhdl -lib work "../mimosis/cores/testout.vhd" -add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd" -add_file -vhdl -lib work "../mimosis/code/InputStage.vhd" +add_file -vhdl -lib work "../mimosis/code/MimosisInputMulti.vhd" +add_file -vhdl -lib work "../mimosis/code/InputStageMulti.vhd" add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd" add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd" +#GBT Core +add_file -vhdl -lib work "../vldb/code/gbt_core.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/gbtsc_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_deserializer.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_pkg.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_rx_fifo.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_rx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_tx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_deserializer.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_rx_fifo.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_rx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_tx.vhd" + + add_file -vhdl -lib work "./trb5sc_mimosis.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/mimosis_feb/trb5sc_mimosis.vhd b/mimosis_feb/trb5sc_mimosis.vhd index 84c7ef7..0305bfd 100644 --- a/mimosis_feb/trb5sc_mimosis.vhd +++ b/mimosis_feb/trb5sc_mimosis.vhd @@ -28,25 +28,25 @@ entity trb5sc_mimosis is SFP_MOD_0 : in std_logic; --HDMI AddOn - LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); - LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_ADDON_RJ : out std_logic_vector(1 downto 0); - SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); - SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - - RJ : inout std_logic_vector(3 downto 0); - H1 : inout std_logic_vector(4 downto 0); - H2 : inout std_logic_vector(4 downto 0); - H3 : inout std_logic_vector(3 downto 0); - H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(3 downto 0); - H6 : inout std_logic_vector(4 downto 0); - H7 : inout std_logic_vector(4 downto 0); - - PIN : out std_logic_vector(8 downto 1); - - MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + H00 : in std_logic_vector(7 downto 0); + H01 : in std_logic_vector(7 downto 0); + H10 : in std_logic_vector(7 downto 0); + H11 : in std_logic_vector(7 downto 0); + V00 : in std_logic_vector(7 downto 0); + V01 : in std_logic_vector(7 downto 0); + V10 : in std_logic_vector(7 downto 0); + V11 : in std_logic_vector(7 downto 0); + + FE_CLK : out std_logic_vector(3 downto 1); --1: 320, 2: 40, 3: all on second connector + SCA_CLK : out std_logic; + SCA_RX : out std_logic; + SCA_TX : in std_logic; + SCA_RST_B : out std_logic; + SCA2_CLK : out std_logic; + SCA2_RX : out std_logic; + SCA2_TX : in std_logic; + SCA2_RST_B : out std_logic; --ADC ADC_SCLK : out std_logic; @@ -118,8 +118,8 @@ architecture arch of trb5sc_mimosis is - signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx,busgbtcore_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx,busgbtcore_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -255,13 +255,9 @@ begin CLKOS3=> clk_80 ); - H3(3) <= clk_320; - - -- For IPHC Proxy - -- RJ(0) <= clk_40; - -- For IKF Proxy - H1(4) <= clk_40; - + FE_CLK(1) <= clk_320; + FE_CLK(2) <= clk_40; + FE_CLK(3) <= '0'; proc_make_reset : process begin wait until rising_edge(clk_sys); @@ -609,9 +605,10 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0), + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", 7 => x"d600", + others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, 7 => 4, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -629,6 +626,7 @@ begin BUS_RX(4) => busgbeip_rx, BUS_RX(5) => busgbereg_rx, BUS_RX(6) => busi2c_rx, + BUS_RX(7) => busgbtcore_rx, BUS_TX(0) => bustools_tx, -- BUS_TX(1) => bussci_tx, @@ -638,6 +636,8 @@ begin BUS_TX(4) => busgbeip_tx, BUS_TX(5) => busgbereg_tx, BUS_TX(6) => busi2c_tx, + BUS_TX(7) => busgbtcore_tx, + STAT_DEBUG => open ); @@ -700,8 +700,10 @@ begin DEBUG_OUT => debug_tools ); - PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + -- PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + SCA_RST_B <= not add_reg(16); + SCA2_RST_B <= not add_reg(17); FLASH_HOLD <= '1'; FLASH_WP <= '1'; @@ -710,132 +712,142 @@ begin --------------------------------------------------------------------------- -- I2C --------------------------------------------------------------------------- - THE_I2C : entity work.i2c_slim2 - port map( - CLOCK => clk_40, - RESET => reset_i, - -- I2C command / setup - I2C_GO_IN => i2c_go, - ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read - WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word - DIRECT_IN => i2c_reg_1(4), -- don't send command - I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) - I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) - I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command - I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command - STATUS_OUT => i2c_reg_4(23 downto 16), - VALID_OUT => i2c_reg_4(31), - I2C_BUSY_OUT => i2c_reg_4(30), - I2C_DONE_OUT => i2c_reg_4(29), - -- I2C connections - SDA_IN => PIN(4), - SDA_OUT => mimosis_sda_drv, - SCL_IN => PIN(3), - SCL_OUT => mimosis_scl_drv, - -- Debug - BSM_OUT => i2c_reg_4(27 downto 24) - ); - --- I2C signal open collector driver --- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; --- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; - - PIN(4) <= MIMOSIS_SDA; - PIN(3) <= MIMOSIS_SCL; - MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; - MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; - --- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; --- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; - - - H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC - PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START - PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET +-- THE_I2C : entity work.i2c_slim2 +-- port map( +-- CLOCK => clk_40, +-- RESET => reset_i, +-- -- I2C command / setup +-- I2C_GO_IN => i2c_go, +-- ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read +-- WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word +-- DIRECT_IN => i2c_reg_1(4), -- don't send command +-- I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) +-- I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) +-- I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) +-- I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command +-- I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command +-- STATUS_OUT => i2c_reg_4(23 downto 16), +-- VALID_OUT => i2c_reg_4(31), +-- I2C_BUSY_OUT => i2c_reg_4(30), +-- I2C_DONE_OUT => i2c_reg_4(29), +-- -- I2C connections +-- SDA_IN => PIN(4), +-- SDA_OUT => mimosis_sda_drv, +-- SCL_IN => PIN(3), +-- SCL_OUT => mimosis_scl_drv, +-- -- Debug +-- BSM_OUT => i2c_reg_4(27 downto 24) +-- ); +-- +-- -- I2C signal open collector driver +-- -- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- -- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; +-- +-- PIN(4) <= MIMOSIS_SDA; +-- PIN(3) <= MIMOSIS_SCL; +-- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +-- +-- -- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- -- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +-- +-- +-- H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC +-- PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START +-- PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET PROC_I2C_REGS : process begin wait until rising_edge(CLK_SYS); busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '0'; + busi2c_tx.unknown <= busi2c_rx.write or busi2c_rx.read; busi2c_tx.nack <= '0'; busi2c_tx.data <= (others => '0'); - i2c_go_100 <= '0'; - - if busi2c_rx.write = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - i2c_reg_0 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - i2c_reg_1 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - i2c_reg_2 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - i2c_go_100 <= busi2c_rx.data(0); - elsif busi2c_rx.addr(3 downto 0) = x"5" then - i2c_reg_5 <= busi2c_rx.data; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - end if; - elsif busi2c_rx.read = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - busi2c_tx.data <= i2c_reg_0; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - busi2c_tx.data <= i2c_reg_1; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - busi2c_tx.data <= i2c_reg_2; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - busi2c_tx.data <= (others => '0'); - elsif busi2c_rx.addr(3 downto 0) = x"4" then - busi2c_tx.data <= i2c_reg_4; - elsif busi2c_rx.addr(3 downto 0) = x"5" then - busi2c_tx.data <= i2c_reg_5; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - - end if; - end if; + -- i2c_go_100 <= '0'; + -- + -- if busi2c_rx.write = '1' then + -- busi2c_tx.ack <= '1'; + -- if busi2c_rx.addr(3 downto 0) = x"0" then + -- i2c_reg_0 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"1" then + -- i2c_reg_1 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"2" then + -- i2c_reg_2 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"3" then + -- i2c_go_100 <= busi2c_rx.data(0); + -- elsif busi2c_rx.addr(3 downto 0) = x"5" then + -- i2c_reg_5 <= busi2c_rx.data; + -- else + -- busi2c_tx.ack <= '0'; + -- busi2c_tx.unknown <= '1'; + -- end if; + -- elsif busi2c_rx.read = '1' then + -- busi2c_tx.ack <= '1'; + -- if busi2c_rx.addr(3 downto 0) = x"0" then + -- busi2c_tx.data <= i2c_reg_0; + -- elsif busi2c_rx.addr(3 downto 0) = x"1" then + -- busi2c_tx.data <= i2c_reg_1; + -- elsif busi2c_rx.addr(3 downto 0) = x"2" then + -- busi2c_tx.data <= i2c_reg_2; + -- elsif busi2c_rx.addr(3 downto 0) = x"3" then + -- busi2c_tx.data <= (others => '0'); + -- elsif busi2c_rx.addr(3 downto 0) = x"4" then + -- busi2c_tx.data <= i2c_reg_4; + -- elsif busi2c_rx.addr(3 downto 0) = x"5" then + -- busi2c_tx.data <= i2c_reg_5; + -- else + -- busi2c_tx.ack <= '0'; + -- busi2c_tx.unknown <= '1'; + -- + -- end if; + -- end if; end process; - THE_I2C_GO_SYNC : pulse_sync - port map( - CLK_A_IN => clk_sys, - RESET_A_IN => reset_i, - PULSE_A_IN => i2c_go_100, - CLK_B_IN => clk_40, - RESET_B_IN => reset_i, - PULSE_B_OUT => i2c_go - ); - - THE_MIMOSIS_SIGNAL_SYNC : signal_sync - generic map( - WIDTH => 32, - DEPTH => 2 - ) - port map( - RESET => reset_i, - CLK0 => clk_sys, - CLK1 => clk_40, - D_IN => i2c_reg_5, - D_OUT => i2c_reg_5_40 - ); + -- THE_I2C_GO_SYNC : pulse_sync + -- port map( + -- CLK_A_IN => clk_sys, + -- RESET_A_IN => reset_i, + -- PULSE_A_IN => i2c_go_100, + -- CLK_B_IN => clk_40, + -- RESET_B_IN => reset_i, + -- PULSE_B_OUT => i2c_go + -- ); + + -- THE_MIMOSIS_SIGNAL_SYNC : signal_sync + -- generic map( + -- WIDTH => 32, + -- DEPTH => 2 + -- ) + -- port map( + -- RESET => reset_i, + -- CLK0 => clk_sys, + -- CLK1 => clk_40, + -- D_IN => i2c_reg_5, + -- D_OUT => i2c_reg_5_40 + -- ); --------------------------------------------------------------------------- -- Input stage --------------------------------------------------------------------------- - THE_MIMOSIS : entity work.MimosisInput + THE_MIMOSIS : entity work.MimosisInputMulti + generic map( + INPUT_NUMBER => 8 + ) port map( CLK => clk_160, CLK_SYS => clk_sys, RESET => reset_i, - INPUT => inp_i, + INPUT(0) => H00, + INPUT(1) => H01, + INPUT(2) => H10, + INPUT(3) => H11, + INPUT(4) => V00, + INPUT(5) => V01, + INPUT(6) => V10, + INPUT(7) => V11, BUSRDO_RX => cts_rdo_rx, BUSRDO_TX => cts_rdo_additional(0), @@ -844,9 +856,27 @@ begin BUS_TX => busmimosis_tx ); --- inp_i <= H2(3 downto 0) & H1(3 downto 0); - inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); - +--------------------------------------------------------------------------- +-- GBT Core +--------------------------------------------------------------------------- + THE_GBT_CORE : entity work.gbt_core + port map( + CLK_SYS => clk_sys, + CLK => clk_40, + CLK_80 => clk_80, + RESET => reset_i, + + BUS_RX => busgbtcore_rx, + BUS_TX => busgbtcore_tx, + + TESTOUT => LED, + + -- ELINK_RX => H3(2), + ELINK_RX => SCA_TX, + ELINK_TX => SCA_RX + ); + + SCA_CLK <= clk_40; --------------------------------------------------------------------------- -- LED @@ -858,7 +888,7 @@ begin -- LED_SFP_GREEN <= not med2int(0).stat_op(9); -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); - LED <= x"FF"; + -- LED <= x"FF"; LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used diff --git a/pinout/trb5sc_mimosisfeb.lpf b/pinout/trb5sc_mimosisfeb.lpf index f6912b2..162cb81 100644 --- a/pinout/trb5sc_mimosisfeb.lpf +++ b/pinout/trb5sc_mimosisfeb.lpf @@ -136,70 +136,70 @@ IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; # LOCATE COMP "FE_DIFF_61_N" SITE "AC6"; # LOCATE COMP "FE_DIFF_62_N" SITE "AB6"; # LOCATE COMP "FE_DIFF_63_N" SITE "AD7"; -LOCATE COMP "H01_D7" SITE "R29" ; #"FE_DIFF[0]" -LOCATE COMP "H01_D3" SITE "T29" ; #"FE_DIFF[1]" -LOCATE COMP "H00_D1" SITE "P31" ; #"FE_DIFF[2]" -LOCATE COMP "H11_D1" SITE "R30" ; #"FE_DIFF[3]" -LOCATE COMP "H00_D3" SITE "N32" ; #"FE_DIFF[4]" -LOCATE COMP "H00_D5" SITE "U31" ; #"FE_DIFF[5]" -LOCATE COMP "H11_D3" SITE "R32" ; #"FE_DIFF[6]" -LOCATE COMP "H01_D1" SITE "W30" ; #"FE_DIFF[7]" -LOCATE COMP "H01_D5" SITE "T32" ; #"FE_DIFF[8]" -LOCATE COMP "H01_D6" SITE "V32" ; #"FE_DIFF[9]" -LOCATE COMP "H00_D7" SITE "Y26" ; #"FE_DIFF[10]" -LOCATE COMP "H01_D2" SITE "Y28" ; #"FE_DIFF[11]" -LOCATE COMP "H00_D0" SITE "Y29" ; #"FE_DIFF[12]" -LOCATE COMP "H11_D0" SITE "AB26" ; #"FE_DIFF[13]" -LOCATE COMP "H10_D7" SITE "AB28" ; #"FE_DIFF[14]" -LOCATE COMP "H00_D2" SITE "AC26" ; #"FE_DIFF[15]" -LOCATE COMP "H10_D5" SITE "D29" ; #"FE_DIFF[16]" -LOCATE COMP "H00_D4" SITE "F29" ; #"FE_DIFF[17]" -LOCATE COMP "H11_D2" SITE "B32" ; #"FE_DIFF[18]" -LOCATE COMP "H01_D0" SITE "D30" ; #"FE_DIFF[19]" -LOCATE COMP "H10_D1" SITE "F30" ; #"FE_DIFF[20]" -LOCATE COMP "H01_D4" SITE "C32" ; #"FE_DIFF[21]" -LOCATE COMP "H10_D3" SITE "F31" ; #"FE_DIFF[22]" -LOCATE COMP "H00_D6" SITE "F32" ; #"FE_DIFF[23]" -LOCATE COMP "H10_D6" SITE "H31" ; #"FE_DIFF[24]" -LOCATE COMP "H11_D7" SITE "J30" ; #"FE_DIFF[25]" -LOCATE COMP "H10_D4" SITE "K31" ; #"FE_DIFF[26]" -LOCATE COMP "H11_D5" SITE "K32" ; #"FE_DIFF[27]" -LOCATE COMP "H11_D6" SITE "L31" ; #"FE_DIFF[28]" -LOCATE COMP "H10_D0" SITE "J29" ; #"FE_DIFF[29]" -LOCATE COMP "H11_D4" SITE "H27" ; #"FE_DIFF[30]" -LOCATE COMP "H10_D2" SITE "K27" ; #"FE_DIFF[31]" +LOCATE COMP "H01_7" SITE "R29" ; #"FE_DIFF[0]" +LOCATE COMP "H01_3" SITE "T29" ; #"FE_DIFF[1]" +LOCATE COMP "H00_1" SITE "P31" ; #"FE_DIFF[2]" +LOCATE COMP "H11_1" SITE "R30" ; #"FE_DIFF[3]" +LOCATE COMP "H00_3" SITE "N32" ; #"FE_DIFF[4]" +LOCATE COMP "H00_5" SITE "U31" ; #"FE_DIFF[5]" +LOCATE COMP "H11_3" SITE "R32" ; #"FE_DIFF[6]" +LOCATE COMP "H01_1" SITE "W30" ; #"FE_DIFF[7]" +LOCATE COMP "H01_5" SITE "T32" ; #"FE_DIFF[8]" +LOCATE COMP "H01_6" SITE "V32" ; #"FE_DIFF[9]" +LOCATE COMP "H00_7" SITE "Y26" ; #"FE_DIFF[10]" +LOCATE COMP "H01_2" SITE "Y28" ; #"FE_DIFF[11]" +LOCATE COMP "H00_0" SITE "Y29" ; #"FE_DIFF[12]" +LOCATE COMP "H11_0" SITE "AB26" ; #"FE_DIFF[13]" +LOCATE COMP "H10_7" SITE "AB28" ; #"FE_DIFF[14]" +LOCATE COMP "H00_2" SITE "AC26" ; #"FE_DIFF[15]" +LOCATE COMP "H10_5" SITE "D29" ; #"FE_DIFF[16]" +LOCATE COMP "H00_4" SITE "F29" ; #"FE_DIFF[17]" +LOCATE COMP "H11_2" SITE "B32" ; #"FE_DIFF[18]" +LOCATE COMP "H01_0" SITE "D30" ; #"FE_DIFF[19]" +LOCATE COMP "H10_1" SITE "F30" ; #"FE_DIFF[20]" +LOCATE COMP "H01_4" SITE "C32" ; #"FE_DIFF[21]" +LOCATE COMP "H10_3" SITE "F31" ; #"FE_DIFF[22]" +LOCATE COMP "H00_6" SITE "F32" ; #"FE_DIFF[23]" +LOCATE COMP "H10_6" SITE "H31" ; #"FE_DIFF[24]" +LOCATE COMP "H11_7" SITE "J30" ; #"FE_DIFF[25]" +LOCATE COMP "H10_4" SITE "K31" ; #"FE_DIFF[26]" +LOCATE COMP "H11_5" SITE "K32" ; #"FE_DIFF[27]" +LOCATE COMP "H11_6" SITE "L31" ; #"FE_DIFF[28]" +LOCATE COMP "H10_0" SITE "J29" ; #"FE_DIFF[29]" +LOCATE COMP "H11_4" SITE "H27" ; #"FE_DIFF[30]" +LOCATE COMP "H10_2" SITE "K27" ; #"FE_DIFF[31]" LOCATE COMP "FE_CLK[3]" SITE "D4" ; #"FE_DIFF[32]" -LOCATE COMP "V10_D7" SITE "F4" ; #"FE_DIFF[33]" +LOCATE COMP "V10_7" SITE "F4" ; #"FE_DIFF[33]" LOCATE COMP "SCA2_RX" SITE "B1" ; #"FE_DIFF[34]" LOCATE COMP "SCA2_TX" SITE "D3" ; #"FE_DIFF[35]" LOCATE COMP "SCA2_CLK" SITE "F3" ; #"FE_DIFF[36]" -LOCATE COMP "V10_D5" SITE "C1" ; #"FE_DIFF[37]" +LOCATE COMP "V10_5" SITE "C1" ; #"FE_DIFF[37]" #LOCATE COMP "V_D" SITE "F2" ; #"FE_DIFF[38]" -LOCATE COMP "V10_D1" SITE "F1" ; #"FE_DIFF[39]" -LOCATE COMP "V01_D6" SITE "H2" ; #"FE_DIFF[40]" -LOCATE COMP "V00_D3" SITE "J3" ; #"FE_DIFF[41]" -LOCATE COMP "V10_D3" SITE "K2" ; #"FE_DIFF[42]" -LOCATE COMP "V10_D4" SITE "K1" ; #"FE_DIFF[43]" +LOCATE COMP "V10_1" SITE "F1" ; #"FE_DIFF[39]" +LOCATE COMP "V01_6" SITE "H2" ; #"FE_DIFF[40]" +LOCATE COMP "V00_3" SITE "J3" ; #"FE_DIFF[41]" +LOCATE COMP "V10_3" SITE "K2" ; #"FE_DIFF[42]" +LOCATE COMP "V10_4" SITE "K1" ; #"FE_DIFF[43]" LOCATE COMP "SCA_RX" SITE "L2" ; #"FE_DIFF[44]" -LOCATE COMP "V10_D6" SITE "J4" ; #"FE_DIFF[45]" +LOCATE COMP "V10_6" SITE "J4" ; #"FE_DIFF[45]" LOCATE COMP "SCA_CLK" SITE "H6" ; #"FE_DIFF[46]" -LOCATE COMP "V00_D7" SITE "K6" ; #"FE_DIFF[47]" -LOCATE COMP "V01_D2" SITE "R4" ; #"FE_DIFF[48]" +LOCATE COMP "V00_7" SITE "K6" ; #"FE_DIFF[47]" +LOCATE COMP "V01_2" SITE "R4" ; #"FE_DIFF[48]" LOCATE COMP "SCA_TX" SITE "T4" ; #"FE_DIFF[49]" -LOCATE COMP "V00_D5" SITE "P2" ; #"FE_DIFF[50]" -LOCATE COMP "V00_D1" SITE "R3" ; #"FE_DIFF[51]" -LOCATE COMP "V11_D6" SITE "N1" ; #"FE_DIFF[52]" -LOCATE COMP "V01_D4" SITE "U2" ; #"FE_DIFF[53]" -LOCATE COMP "V11_D2" SITE "R1" ; #"FE_DIFF[54]" -LOCATE COMP "V10_D0" SITE "W3" ; #"FE_DIFF[55]" -LOCATE COMP "V00_D2" SITE "T1" ; #"FE_DIFF[56]" -LOCATE COMP "V00_D0" SITE "V1" ; #"FE_DIFF[57]" -LOCATE COMP "V01_D0" SITE "Y7" ; #"FE_DIFF[58]" -LOCATE COMP "V10_D2" SITE "Y5" ; #"FE_DIFF[59]" -LOCATE COMP "V00_D6" SITE "Y4" ; #"FE_DIFF[60]" -LOCATE COMP "V00_D4" SITE "AB7" ; #"FE_DIFF[61]" -LOCATE COMP "V11_D4" SITE "AB5" ; #"FE_DIFF[62]" -LOCATE COMP "V11_D0" SITE "AC7" ; #"FE_DIFF[63]" +LOCATE COMP "V00_5" SITE "P2" ; #"FE_DIFF[50]" +LOCATE COMP "V00_1" SITE "R3" ; #"FE_DIFF[51]" +LOCATE COMP "V11_6" SITE "N1" ; #"FE_DIFF[52]" +LOCATE COMP "V01_4" SITE "U2" ; #"FE_DIFF[53]" +LOCATE COMP "V11_2" SITE "R1" ; #"FE_DIFF[54]" +LOCATE COMP "V10_0" SITE "W3" ; #"FE_DIFF[55]" +LOCATE COMP "V00_2" SITE "T1" ; #"FE_DIFF[56]" +LOCATE COMP "V00_0" SITE "V1" ; #"FE_DIFF[57]" +LOCATE COMP "V01_0" SITE "Y7" ; #"FE_DIFF[58]" +LOCATE COMP "V10_2" SITE "Y5" ; #"FE_DIFF[59]" +LOCATE COMP "V00_6" SITE "Y4" ; #"FE_DIFF[60]" +LOCATE COMP "V00_4" SITE "AB7" ; #"FE_DIFF[61]" +LOCATE COMP "V11_4" SITE "AB5" ; #"FE_DIFF[62]" +LOCATE COMP "V11_0" SITE "AC7" ; #"FE_DIFF[63]" DEFINE PORT GROUP "H0_group" "H0*" ; DEFINE PORT GROUP "H1_group" "H1*" ; diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 46cffb4..ee52b43 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -2,10 +2,14 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library ecp5um; +use ecp5um.components.all; + library work; use work.trb_net_std.all; + entity gbt_core is port( CLK_SYS : in std_logic; @@ -185,18 +189,27 @@ begin end if; end process; + inst_oddrx1f: ODDRX1F + port map ( + D0 => hdlc_from_gbtsc(1), + D1 => hdlc_from_gbtsc(0), + SCLK => CLK, + RST => RESET, + Q => ELINK_TX + ); + - -- HDLC serializer + -- -- HDLC serializer hdlcser_proc: process(CLK_80) - variable bitflip : std_logic := '0'; + -- variable bitflip : std_logic := '0'; begin if rising_edge(CLK_80) then - if bitflip = '1' then - ELINK_TX <= hdlc_from_gbtsc(1); - else - ELINK_TX <= hdlc_from_gbtsc(0); - end if; - bitflip := not bitflip; + -- if bitflip = '1' then + -- ELINK_TX <= hdlc_from_gbtsc(1); + -- else + -- ELINK_TX <= hdlc_from_gbtsc(0); + -- end if; + -- bitflip := not bitflip; hdlc_des <= hdlc_des(2 downto 0) & ELINK_RX; end if; end process; @@ -228,16 +241,16 @@ begin if BUS_RX.addr(3 downto 0) = x"0" then gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); - elsif BUS_RX.addr(3 downto 0) = x"1" then - gbtsc_reset_go <= BUS_RX.data(0); - gbtsc_connect_go <= BUS_RX.data(1); - gbtsc_go <= BUS_RX.data(2); elsif BUS_RX.addr(3 downto 0) = x"2" then gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); elsif BUS_RX.addr(3 downto 0) = x"3" then gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); + elsif BUS_RX.addr(3 downto 0) = x"4" then + gbtsc_reset_go <= BUS_RX.data(0); + gbtsc_connect_go <= BUS_RX.data(1); + gbtsc_go <= BUS_RX.data(2); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; -- 2.51.0