From df0d1c0e8f107fd679bc7a804e99eaf9acc972ff Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 18 Aug 2014 13:54:36 +0200 Subject: [PATCH 1/1] added all files for hub2 --- README | 5 + compile.pl | 197 +++ compile1.pl | 171 +++ compile2.pl | 172 +++ compile_cvs.pl | 197 +++ compilegsi.pl | 171 +++ constraints_hub2_fpga1.lpf | 367 +++++ constraints_hub2_fpga2.lpf | 368 +++++ hub2.xcf | 133 ++ hub2_fpga1.p2t | 21 + hub2_fpga1.prj | 121 ++ hub2_fpga1.vhd | 527 +++++++ hub2_fpga2.lpf | 587 ++++++++ hub2_fpga2.p2t | 21 + hub2_fpga2.prj | 1 + hub2_fpga2.vhd | 960 +++++++++++++ hub2_fpga2.vhd.old | 2117 +++++++++++++++++++++++++++++ hub2_fpga2_cvs.prj | 344 +++++ hub2_full.xcf | 133 ++ hub2_single.xcf | 111 ++ version.vhd | 13 + workdir/serdes_gbe_0.txt | 1 + workdir/serdes_gbe_0_200.txt | 1 + workdir/serdes_gbe_0_200_ext.txt | 1 + workdir/serdes_gbe_0_extclock.txt | 1 + workdir/serdes_gbe_all.txt | 1 + workdir/serdes_sfp_0.txt | 1 + workdir/serdes_sfp_0_extclock.txt | 1 + workdir/serdes_sfp_1.txt | 1 + workdir/serdes_sfp_2.txt | 1 + workdir/serdes_sfp_3.txt | 1 + workdir/serdes_sfp_full_quad.txt | 1 + 32 files changed, 6748 insertions(+) create mode 100644 README create mode 100755 compile.pl create mode 100755 compile1.pl create mode 100755 compile2.pl create mode 100755 compile_cvs.pl create mode 100755 compilegsi.pl create mode 100644 constraints_hub2_fpga1.lpf create mode 100644 constraints_hub2_fpga2.lpf create mode 100644 hub2.xcf create mode 100644 hub2_fpga1.p2t create mode 100644 hub2_fpga1.prj create mode 100644 hub2_fpga1.vhd create mode 100755 hub2_fpga2.lpf create mode 100644 hub2_fpga2.p2t create mode 100644 hub2_fpga2.prj create mode 100644 hub2_fpga2.vhd create mode 100644 hub2_fpga2.vhd.old create mode 100644 hub2_fpga2_cvs.prj create mode 100644 hub2_full.xcf create mode 100644 hub2_single.xcf create mode 100644 version.vhd create mode 120000 workdir/serdes_gbe_0.txt create mode 120000 workdir/serdes_gbe_0_200.txt create mode 120000 workdir/serdes_gbe_0_200_ext.txt create mode 120000 workdir/serdes_gbe_0_extclock.txt create mode 120000 workdir/serdes_gbe_all.txt create mode 120000 workdir/serdes_sfp_0.txt create mode 120000 workdir/serdes_sfp_0_extclock.txt create mode 120000 workdir/serdes_sfp_1.txt create mode 120000 workdir/serdes_sfp_2.txt create mode 120000 workdir/serdes_sfp_3.txt create mode 120000 workdir/serdes_sfp_full_quad.txt diff --git a/README b/README new file mode 100644 index 0000000..6410ed2 --- /dev/null +++ b/README @@ -0,0 +1,5 @@ +in order to build the whole logic: +- copy all .ngo files from trbnet/gbe_ecp2m/ipcores/tsmac3 into workdir +- copy all .ngo files from trbnet/gbe_ecp2m/ipcores/sgmii_gbe_pcs32 into workdir +- copy the .txt file from trbnet/gbe_ecp2m/ipcores/serdes into workdir + diff --git a/compile.pl b/compile.pl new file mode 100755 index 0000000..af646f1 --- /dev/null +++ b/compile.pl @@ -0,0 +1,197 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +########################################### + +# You need the tunnels before! + +use Data::Dumper; +use warnings; +use strict; + +# Path settings for ispLEVER tools +my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools'; #'/usr/local/opt/synplify/8/isptools'; + +# Path settings for SynplifyPRO +my $synplify_path = '/opt/synplify/D-2010.03'; #'/usr/local/opt/synplify/premier'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de"; #"27000\@localhost"; + +# Design top level entity +my $TOPNAME="hub2_fpga2"; # CHANGED + +# FPGA chip description +my $FAMILYNAME="LATTICEECP2M"; # CHANGED +my $DEVICENAME="LFE2M100E"; # CHANGED +my $PACKAGE="FPBGA900"; # CHANGED +my $SPEEDGRADE="5"; # CHANGED + +# benchmarking +my $CTIME_String = localtime(time); +print "Script started: $CTIME_String\n"; +system("echo $CTIME_String > workdir/benchmark.txt"); + +# Create full lpf file +#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +# Generate timestamp for slowcontrol readback +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +# Run Synplify on the design +system("env| grep LM_"); +my $r = ""; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + +# Check for errors +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "ERROR_ERROR_ERROR_ERROR_ERROR\n"; + exit 129; + } +} + +# ispLEVER design flow starts here +# new license file must be given +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +# EDIF2NGD +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +# NGDBUILD +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +# MAP +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|; +execute($c); + +system("rm $TOPNAME.ncd"); + +# MULTIPAR + +# my $fh2 = new FileHandle(">$TOPNAME.p2t"); +# die "could not open file" if (! defined $fh2); +# print $fh2 <close; + +###################################################################### +# -w # overwrite files +# -i 15 # maximum number of routing attempts +# -l 5 # effort level (1-5) +# -n 1 # starting cost table (n=0 loop) +# -y # delay summary report +# -s 12 # number of best results to save +# -t 1 # start placement with cost table X +# -c 1 # number of cost-based cleanup passes of the router +# -e 2 # number of delay-based cleanup passes of the router +# -m nodelist.txt # +# -exp parCDP=1 # +# -exp parCDR=1 # +# -exp parPlcInLimit=0 # +# -exp parPlcInNeighborSize=1 # +# -exp parPathBased=ON # +# -exp parHold=ON # +# -exp parHoldLimit=10000 # +# -exp paruseNBR=1 # +###################################################################### + +# real multipar +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report (setup) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report (hold) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# BitGen +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +$CTIME_String = localtime(time); +print "Script ended: $CTIME_String\n"; +system("echo $CTIME_String >> workdir/benchmark.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/compile1.pl b/compile1.pl new file mode 100755 index 0000000..1b43fcd --- /dev/null +++ b/compile1.pl @@ -0,0 +1,171 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +use Data::Dumper; +use warnings; +use strict; +use FileHandle; + +#Paths to synplify & isplever +my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; +#my $synplify_path = '/d/sugar/lattice/synplify/fpga_c200906sp1/'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; +my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; + +#Name of the top level entity +my $TOPNAME="hub2_fpga1"; +#File +my $PINOUT="../trbnet/pinout/TRB_HUB2_FPGA1.lpf"; + + +#FPGA device +my $FAMILYNAME="LATTICEECP2M"; +my $DEVICENAME="LFE2M100E"; +my $PACKAGE="FPBGA900"; +my $SPEEDGRADE="5"; + +#working directory +my $WORKDIR="workdir"; + +#par options +#my $paroptions ="-w -i 12 -l 5 -n 5 -y -s 12 -t 1 -c 1 -e 2 -m nodelist.txt ". +# " -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=OFF:paruseNBR=1:"; + + +#my $synplify_path = '/home/hadaq/bin/'; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +#$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +#set -e +#set -o errexit + +#create full lpf file from pinout and constraints-file +execute("cp ".$PINOUT." ".$WORKDIR."/".$TOPNAME.".lpf"); +execute("cat constraints_".$TOPNAME.".lpf >> ".$WORKDIR."/".$TOPNAME.".lpf"); + + +#run synplify +my $r=""; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +# my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + +my $currentdir = `pwd`; +chdir $WORKDIR; + +#check & print errors in synplify report +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) { + if(/\@E:/) { + $c="cat $TOPNAME.srr"; + system($c); + exit 129; + } + } + +$ENV{'LM_LICENSE_FILE'}="1702\@localhost"; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5a00/data" -p "$lattice_path/ispfpga/ep5m00/data" "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.last.ncd"); +system("mv $TOPNAME.ncd $TOPNAME.last.ncd"); + + +# +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|; +# execute($c); + +#-g "$TOPNAME.guide.ncd" +#$c=qq|$lattice_path/ispfpga/bin/lin/par $paroptions "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + + +#system(" cat $TOPNAME.dir/*.ncd > $TOPNAME.ncd"); + +# IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 10 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 10 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir $currentdir; + + +# $c=("$lattice_path/ispvmsystem/ispvm -infile $TOPNAME".".xcf -outfiletype -svf"); +# execute($c); +# $c=("perl -i -ne 'print unless(/^!/)' $TOPNAME".".svf"); +# execute($c); +#$c=("impact -batch impact_batch.txt"); +#execute($c); + +#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); +#execute($c); + +#} + +#$c=("impact -batch impact_batch_hub.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/compile2.pl b/compile2.pl new file mode 100755 index 0000000..035f919 --- /dev/null +++ b/compile2.pl @@ -0,0 +1,172 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +use Data::Dumper; +use warnings; +use strict; +use FileHandle; + +#Paths to synplify & isplever +#my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/'; +my $lattice_path = '/d/sugar/lattice/diamond/1.1'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; +#my $synplify_path = '/d/sugar/lattice/synplify/fpga_c200906sp1/'; +#my $synplify_path = '/d/sugar/lattice/synplify/syn_c200903/fpga_c200903'; +my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; + + +#Name of the top level entity +my $TOPNAME="hub2_fpga2"; +#File +my $PINOUT="../trbnet/pinout/TRB_HUB2_FPGA2.lpf"; + + +#FPGA device +my $FAMILYNAME="LATTICEECP2M"; +my $DEVICENAME="LFE2M100E"; +my $PACKAGE="FPBGA900"; +my $SPEEDGRADE="5"; + +#working directory +my $WORKDIR="workdir"; + +#par options +#my $paroptions ="-w -i 12 -l 5 -n 5 -y -s 12 -t 1 -c 1 -e 2 -m nodelist.txt ". +# " -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=OFF:paruseNBR=1:"; + + +#my $synplify_path = '/home/hadaq/bin/'; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +#$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +#set -e +#set -o errexit + +#create full lpf file from pinout and constraints-file +execute("cp ".$PINOUT." ".$WORKDIR."/".$TOPNAME.".lpf"); +execute("cat constraints_".$TOPNAME.".lpf >> ".$WORKDIR."/".$TOPNAME.".lpf"); + + +#run synplify +my $r=""; +#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + +my $currentdir = `pwd`; +chdir $WORKDIR; + +#check & print errors in synplify report +my $fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) { + if(/\@E:/) { + $c="cat $TOPNAME.srr"; + system($c); + exit 129; + } + } + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5a00/data" -p "$lattice_path/ispfpga/ep5m00/data" "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.last.ncd"); +system("mv $TOPNAME.ncd $TOPNAME.last.ncd"); + + +# +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|; +# execute($c); + +#-g "$TOPNAME.guide.ncd" +#$c=qq|$lattice_path/ispfpga/bin/lin/par $paroptions "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + + +#system(" cat $TOPNAME.dir/*.ncd > $TOPNAME.ncd"); + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 10 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 10 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir $currentdir; + + +# $c=("$lattice_path/ispvmsystem/ispvm -infile $TOPNAME".".xcf -outfiletype -svf"); +# execute($c); +# $c=("perl -i -ne 'print unless(/^!/)' $TOPNAME".".svf"); +# execute($c); +#$c=("impact -batch impact_batch.txt"); +#execute($c); + +#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); +#execute($c); + +#} + +#$c=("impact -batch impact_batch_hub.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/compile_cvs.pl b/compile_cvs.pl new file mode 100755 index 0000000..638a9e4 --- /dev/null +++ b/compile_cvs.pl @@ -0,0 +1,197 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +########################################### + +# You need the tunnels before! + +use Data::Dumper; +use warnings; +use strict; + +# Path settings for ispLEVER tools +my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools'; #'/usr/local/opt/synplify/8/isptools'; + +# Path settings for SynplifyPRO +my $synplify_path = '/opt/synplify/D-2010.03'; #'/usr/local/opt/synplify/premier'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de"; #"27000\@localhost"; + +# Design top level entity +my $TOPNAME="hub2_fpga2"; # CHANGED + +# FPGA chip description +my $FAMILYNAME="LATTICEECP2M"; # CHANGED +my $DEVICENAME="LFE2M100E"; # CHANGED +my $PACKAGE="FPBGA900"; # CHANGED +my $SPEEDGRADE="5"; # CHANGED + +# benchmarking +my $CTIME_String = localtime(time); +print "Script started: $CTIME_String\n"; +system("echo $CTIME_String > workdir/benchmark.txt"); + +# Create full lpf file +#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +# Generate timestamp for slowcontrol readback +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +# Run Synplify on the design +system("env| grep LM_"); +my $r = ""; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME"."_cvs".".prj"; +$r=execute($c, "do_not_exit" ); + +# Check for errors +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "ERROR_ERROR_ERROR_ERROR_ERROR\n"; + exit 129; + } +} + +# ispLEVER design flow starts here +# new license file must be given +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +# EDIF2NGD +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +# NGDBUILD +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +# MAP +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|; +execute($c); + +system("rm $TOPNAME.ncd"); + +# MULTIPAR + +# my $fh2 = new FileHandle(">$TOPNAME.p2t"); +# die "could not open file" if (! defined $fh2); +# print $fh2 <close; + +###################################################################### +# -w # overwrite files +# -i 15 # maximum number of routing attempts +# -l 5 # effort level (1-5) +# -n 1 # starting cost table (n=0 loop) +# -y # delay summary report +# -s 12 # number of best results to save +# -t 1 # start placement with cost table X +# -c 1 # number of cost-based cleanup passes of the router +# -e 2 # number of delay-based cleanup passes of the router +# -m nodelist.txt # +# -exp parCDP=1 # +# -exp parCDR=1 # +# -exp parPlcInLimit=0 # +# -exp parPlcInNeighborSize=1 # +# -exp parPathBased=ON # +# -exp parHold=ON # +# -exp parHoldLimit=10000 # +# -exp paruseNBR=1 # +###################################################################### + +# real multipar +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report (setup) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report (hold) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# BitGen +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +$CTIME_String = localtime(time); +print "Script ended: $CTIME_String\n"; +system("echo $CTIME_String >> workdir/benchmark.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/compilegsi.pl b/compilegsi.pl new file mode 100755 index 0000000..f4b7149 --- /dev/null +++ b/compilegsi.pl @@ -0,0 +1,171 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +use Data::Dumper; +use warnings; +use strict; +use FileHandle; + +#Paths to synplify & isplever +my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools'; +my $synplify_path = '/opt/synplicity/syn_c200903/fpga_c200903'; + +#Name of the top level entity +my $TOPNAME="hub2_fpga2"; +#File +my $PINOUT="../trbnet/pinout/TRB_HUB2_FPGA2.lpf"; + + +#FPGA device +my $FAMILYNAME="LATTICEECP2M"; +my $DEVICENAME="LFE2M100E"; +my $PACKAGE="FPBGA900"; +my $SPEEDGRADE="5"; + +#working directory +my $WORKDIR="workdir"; + +#par options +#my $paroptions ="-w -i 12 -l 5 -n 5 -y -s 12 -t 1 -c 1 -e 2 -m nodelist.txt ". +# " -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=OFF:paruseNBR=1:"; + + +#my $synplify_path = '/home/hadaq/bin/'; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; + +#$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; +$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de"; + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +#set -e +#set -o errexit + +#create full lpf file from pinout and constraints-file +execute("cp ".$PINOUT." ".$WORKDIR."/".$TOPNAME.".lpf"); +execute("cat constraints_".$TOPNAME.".lpf >> ".$WORKDIR."/".$TOPNAME.".lpf"); + + +#run synplify +my $r=""; + +#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj"; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + +my $currentdir = `pwd`; +chdir $WORKDIR; + +#check & print errors in synplify report +my $fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) { + if(/\@E:/) { + $c="cat $TOPNAME.srr"; + system($c); + exit 129; + } + } + +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5a00/data" -p "$lattice_path/ispfpga/ep5m00/data" "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.last.ncd"); +system("mv $TOPNAME.ncd $TOPNAME.last.ncd"); + + +# +# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|; +# execute($c); + +#-g "$TOPNAME.guide.ncd" +#$c=qq|$lattice_path/ispfpga/bin/lin/par $paroptions "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf" |; +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + + +#system(" cat $TOPNAME.dir/*.ncd > $TOPNAME.ncd"); + +# IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 10 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 10 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + + + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir $currentdir; + + +# $c=("$lattice_path/ispvmsystem/ispvm -infile $TOPNAME".".xcf -outfiletype -svf"); +# execute($c); +# $c=("perl -i -ne 'print unless(/^!/)' $TOPNAME".".svf"); +# execute($c); +#$c=("impact -batch impact_batch.txt"); +#execute($c); + +#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); +#execute($c); + +#} + +#$c=("impact -batch impact_batch_hub.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/constraints_hub2_fpga1.lpf b/constraints_hub2_fpga1.lpf new file mode 100644 index 0000000..504402b --- /dev/null +++ b/constraints_hub2_fpga1.lpf @@ -0,0 +1,367 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +######################################### +# Constraints +######################################### + IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + FREQUENCY PORT CLK100_P 100.000000 MHz HOLD_MARGIN 0.100000 nS ; +# FREQUENCY PORT ADO_CLK_OUT_P 100.000000 MHz ; + FREQUENCY PORT CLK_F1_TO_F2 100.000000 MHz ; +# FREQUENCY PORT CLK_F2_TO_F1_P 100.000000 MHz ; +# FREQUENCY PORT FROM_TRB_TO_ADDON_CLK_P 100.000000 MHz ; + FREQUENCY NET CLK100_P_c 100.0 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET clk 100.0 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY PORT F2_TO_F1_1 100 MHz ; + + LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_twisted_serdes_THE_SERDES/PCSC_INST" SITE "ULPCS" ; + LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_normal_serdes_THE_SERDES/PCSC_INST" SITE "LLPCS" ; + LOCATE COMP "THE_MEDIA_INTERFACE_2/gen_twisted_serdes_THE_SERDES/PCSC_INST" SITE "LRPCS" ; + LOCATE COMP "THE_MEDIA_INTERFACE_3/gen_twisted_serdes_THE_SERDES/PCSC_INST" SITE "URPCS" ; + + FREQUENCY NET "THE_MEDIA_INTERFACE_0/ff_txfullclk" 200.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET "THE_MEDIA_INTERFACE_1/ff_txfullclk" 200.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET "THE_MEDIA_INTERFACE_2/ff_txfullclk" 200.000000 MHz HOLD_MARGIN 0.100000 nS ; + FREQUENCY NET "THE_MEDIA_INTERFACE_3/ff_txfullclk" 200.000000 MHz HOLD_MARGIN 0.100000 nS ; + +USE EDGE NET "F2_TO_F1_c_1" ; +# PROHIBIT PRIMARY NET "F2_TO_F1_c_1" ; +# PROHIBIT SECONDARY NET "F2_TO_F1_c_1" ; + + CLOCK_TO_OUT PORT "F1_TO_F2*" 20 ns CLKNET CLK100_P_c ; + INPUT_SETUP PORT "F2_TO_F1*" 3 ns CLKPORT F2_TO_F1_1 ; + + +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE_1/gen_rx_logic_0_THE_CNT_RESET_PROC_send_reset_words_0" 40 ns; +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE_1/gen_rx_logic_1_THE_CNT_RESET_PROC_send_reset_words_1" 40 ns; +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE_1/gen_rx_logic_0_THE_CNT_RESET_PROC_make_trbnet_reset_0" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE_1/gen_rx_logic_1_THE_CNT_RESET_PROC_make_trbnet_reset_1" 20 ns; +MULTICYCLE FROM CELL "THE_RESET_SYNC/sync_q_1" 2.000000 X ; +MULTICYCLE FROM CELL "THE_RESET_SYNC/gen_others_gen_flipflops_2_sync_q_2" 20 ns ; +MULTICYCLE FROM CELL "THE_RESET_SYNC/gen_others_*" 20 ns ; +MULTICYCLE FROM CELL "THE_HUB/proc_SYNC_RESET_reset_i" 20 ns; +MULTICYCLE FROM CELL "THE_HUB/reset_i" 20 ns; + +MULTICYCLE FROM CELL "THE_HUB/reset_i*" 20 ns; +MULTICYCLE FROM CELL "THE_HUB/gen_internal_reset*" 20 ns; +MULTICYCLE FROM CELL "med_stat_op_*" 30 ns; +MULTICYCLE FROM CELL "THE_HUB/buf_REGISTERS*" 30 ns; +MULTICYCLE TO CELL "THE_HUB/buf_REGISTERS*" 30 ns; +MULTICYCLE FROM CELL "async_pulse" 30 ns; +MULTICYCLE FROM CELL "THE_HUB/lsm_data*" 20 ns; +MULTICYCLE TO CELL "THE_HUB/lsm_data*" 20 ns; +MULTICYCLE FROM CELL "THE_HUB/next_lsm_data*" 20 ns; +MULTICYCLE TO CELL "THE_HUB/next_lsm_data*" 20 ns; + + +# REGION "MED0" "R9C2" 18 26 ; +REGION "MED1" "R87C2" 18 26 ; +REGION "MED2" "R80C100" 25 26 ; +REGION "MED3" "R9C100" 18 26 ; +REGION "MEDT" "R33C113" 17 15 ; + + + +REGION "BUFFERS_FULL_HUB_3" "R2C39" 32 52 ; +REGION "BUFFERS_FULL_HUB_1" "R33C28" 47 54 ; +REGION "BUFFERS_FULL_HUB_0" "R80C39" 32 52 ; + +REGION "BUFFERS_NN_HUB_3" "R7C48" 32 32 ; +REGION "BUFFERS_NN_HUB_1" "R33C35" 47 40 ; +REGION "BUFFERS_NN_HUB_0" "R80C50" 32 32 ; + +REGION "BUFFERS_LN_HUB_3" "R2C39" 34 38 ; +REGION "BUFFERS_LN_HUB_1" "R33C15" 47 40 ; +REGION "BUFFERS_LN_HUB_0" "R78C30" 34 43 ; + +REGION "BUFFERS_RN_HUB_3" "R2C64" 35 45 ; +REGION "BUFFERS_RN_HUB_1" "R33C62" 47 53 ; #47 49 +REGION "BUFFERS_RN_HUB_0" "R80C64" 32 38 ; + +# REGION "MUXES_UL" "R30C11" 27 20 ; +REGION "MUXES_UR" "R30C80" 27 40 ; +REGION "MUXES_LL" "R56C11" 27 40 ; +REGION "MUXES_LR" "R45C80" 35 40 ; + +REGION "REGIO_REG" "R9C2" 32 30 ; + + +#Before moving of sbuf +# REGION "BUFFERS_FULL_HUB_3" "R2C29" 32 72 ; +# REGION "BUFFERS_FULL_HUB_1" "R33C18" 47 74 ; +# REGION "BUFFERS_FULL_HUB_0" "R80C29" 32 72 ; +# +# REGION "BUFFERS_NN_HUB_3" "R7C48" 32 32 ; +# REGION "BUFFERS_NN_HUB_1" "R33C35" 47 40 ; +# REGION "BUFFERS_NN_HUB_0" "R80C50" 32 32 ; +# +# REGION "BUFFERS_LN_HUB_3" "R2C29" 34 48 ; +# REGION "BUFFERS_LN_HUB_1" "R33C5" 47 50 ; +# REGION "BUFFERS_LN_HUB_0" "R78C20" 34 53 ; +# +# REGION "BUFFERS_RN_HUB_3" "R2C64" 35 55 ; +# REGION "BUFFERS_RN_HUB_1" "R33C62" 47 63 ; #47 49 +# REGION "BUFFERS_RN_HUB_0" "R80C64" 32 48 ; +# +# # REGION "MUXES_UL" "R30C11" 27 20 ; +# REGION "MUXES_UR" "R30C95" 27 20 ; +# REGION "MUXES_LL" "R56C11" 27 20 ; +# REGION "MUXES_LR" "R45C95" 35 20 ; +#End Before moving of sbuf + +# LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_2/media_interface_group" REGION "MED2" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_3/media_interface_group" REGION "MED3" ; +LOCATE UGROUP "gen_inter_fpga_THE_MEDIA_INTERFACE_T/media_interface_group" REGION "MEDT" ; + + + + + + +# REGION "BUFFERS_FULL_HUB_0" "R2C29" 32 72 ; +# REGION "BUFFERS_FULL_HUB_1" "R29C25" 47 80 ; +# REGION "BUFFERS_FULL_HUB_3" "R75C29" 37 72 ; +# +# REGION "BUFFERS_NN_HUB_0" "R2C49" 32 32 ; +# REGION "BUFFERS_NN_HUB_1" "R29C45" 47 40 ; +# REGION "BUFFERS_NN_HUB_3" "R75C49" 37 32 ; +# +# REGION "BUFFERS_LN_HUB_0" "R2C29" 32 36 ; +# REGION "BUFFERS_LN_HUB_1" "R29C25" 47 40 ; +# REGION "BUFFERS_LN_HUB_3" "R75C29" 37 36 ; +# +# REGION "BUFFERS_RN_HUB_0" "R2C65" 32 36 ; +# REGION "BUFFERS_RN_HUB_1" "R29C65" 47 40 ; +# REGION "BUFFERS_RN_HUB_3" "R75C65" 37 36 ; +# +# REGION "MUXES_UL" "R30C6" 27 20 ; +# REGION "MUXES_UR" "R30C105" 27 20 ; +# REGION "MUXES_LL" "R56C6" 27 20 ; +# REGION "MUXES_LR" "R56C105" 27 20 ; + + + +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_0" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_1" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_RN_HUB_3" ; + +#0&1 is uplink! +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; + +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; + + + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_0" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_1" ; + + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_LN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_RN_HUB_3" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; + +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "MUXES_UR" ; + +LOCATE UGROUP "THE_HUB/hub_control/RegIO_group" REGION "REGIO_REG" ; +LOCATE UGROUP "THE_HUB/THE_BUS_HANDLER/Bus_handler_group" REGION "REGIO_REG" ; +LOCATE UGROUP "THE_HUB/gen_ctrl_api_CTRL_API/API_group" REGION "REGIO_REG" ; + + + +# LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LL" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LL" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LL" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LL" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_7_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_8_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_9_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_10_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_11_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_12_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_13_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_14_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_15_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_bufs_16_gen_iobufs_2_gen_trmbuf_IOBUF/TRMBUF_group" REGION "MUXES_UR" ; + +LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "MUXES_LL" ; +LOCATE UGROUP "THE_HUB/gen_muxes_5_MPLEX/MUX_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_6_MPLEX/MUX_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_7_MPLEX/MUX_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_8_MPLEX/MUX_group" REGION "MUXES_LR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_9_MPLEX/MUX_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_10_MPLEX/MUX_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_11_MPLEX/MUX_group" REGION "MUXES_UR" ; +LOCATE UGROUP "THE_HUB/gen_muxes_12_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_muxes_13_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_muxes_14_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_muxes_15_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "THE_HUB/gen_muxes_16_MPLEX/MUX_group" REGION "MUXES_UR" ; + +LOCATE UGROUP "THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_NN_HUB_0" ; +LOCATE UGROUP "THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_NN_HUB_1" ; +LOCATE UGROUP "THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_NN_HUB_3" ; diff --git a/constraints_hub2_fpga2.lpf b/constraints_hub2_fpga2.lpf new file mode 100644 index 0000000..b8c898e --- /dev/null +++ b/constraints_hub2_fpga2.lpf @@ -0,0 +1,368 @@ +COMMERCIAL; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +######################################################################################################### +######################################################################################################### +######################################### +# Constraints +######################################### + + +######################################### +# IP Cores +######################################### + +#TSMAC +#Begin multicycle path from constraints +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +# MULTICYCLE FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +# MULTICYCLE FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +#End multicycle path from constraints + +#Begin false path from constraints +# BLOCK PATH FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; +# BLOCK PATH FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; +#End false path from constraints + + +######################################### +# Frequencies +######################################### +FREQUENCY PORT CLK_F1_TO_F2 100.000000 MHz ; +FREQUENCY NET CLK_IN 200.000000 MHz ; +FREQUENCY NET CLK_100 100.000000 MHz ; +FREQUENCY PORT F1_TO_F2_1 100.000000 MHz ; + +FREQUENCY NET "THE_MEDIA_INTERFACE_3/gen_serdes_0_200_THE_SERDES/ff_txfullclk" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_INTERFACE_2/gen_serdes_0_200_ext_THE_SERDES/ff_txfullclk" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_INTERFACE_1/gen_serdes_0_200_THE_SERDES/ff_txfullclk" 100.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/CLK_125_OUT_inferred_clock" 125.00 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/refclk2core" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/ff_txfullclk" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/refclkcore" 125.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; + +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.REFCK2CORE" 125.000000 MHz ; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; + +USE EDGE NET "CLK_F1_TO_F2_c" ; + +GSR_NET NET "GSR_N"; + +CLOCK_TO_OUT PORT "F2_TO_F1*" 20 ns CLKNET CLK_100 ; +INPUT_SETUP PORT "F1_TO_F2*" 3 ns CLKPORT CLK_F1_TO_F2 ; + +######################################### +# Locate Serdes +######################################### + +LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST" SITE "LLPCS" ; + +#LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/PCSC_INST" SITE "LLPCS" ; +#LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LLPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LRPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_2/gen_serdes_0_ext_200_THE_SERDES/PCSC_INST" SITE "URPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_3/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "ULPCS" ; + + + +######################################### +# Locate Logic +######################################### +# REGION "MED0" "R86C2" 19 36 ; +REGION "MED0" "R86C2" 19 45 ; +REGION "MED1" "R86C90" 19 36 ; +REGION "MED2" "R9C90" 18 36 ; +REGION "MED3" "R9C2" 18 36 ; +# REGION "MEDT" "R40C100" 17 25 ; + +REGION "BUFFERS_N_HUB_0" "R2C40" 30 63 ; +REGION "BUFFERS_N_HUB_1" "R28C35" 47 80 ; +REGION "BUFFERS_N_HUB_3" "R70C40" 40 63 ; +# REGION "GBE_REGION" "R34C2" 63 68 ; +#REGION "GBE_REGION" "R32C2" 63 68 ; +#REGION "GBE_REGION" "R50C2" 34 52 ; +REGION "GBE_REGION" "R32C2" 63 68 ; + +#REGION "GBE_ipu2gbe_region" "R48C2" 36 43; +#REGION "GBE_packet_region" "R66C50" 45 28; +#REGION "GBE_frame_region" "R77C44" 34 10; +#REGION "GBE_conf_region" "R48C44" 18 22; + +# OLD +#REGION "BUFFERS_N_HUB_0" "R2C40" 35 63 ; +#REGION "BUFFERS_N_HUB_1" "R35C35" 40 80 ; +#REGION "BUFFERS_N_HUB_3" "R70C40" 40 63 ; +#REGION "GBE_REGION" "R25C2" 63 68 ; + +LOCATE UGROUP "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/media_interface_group" REGION "MED0" ; +#LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_2/media_interface_group" REGION "MED2" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_3/media_interface_group" REGION "MED3" ; +# LOCATE UGROUP "THE_MEDIA_INTERFACE_T/media_interface_group" REGION "MEDT" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; + + +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_0/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_1/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_3/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_0" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_1" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_0" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_1" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/hub_control/RegIO_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_ethernet_hub_GBE/GBE_BUF_group" REGION "GBE_REGION" ; + +######################################### +# Longer Delays for Reset +######################################### +MULTICYCLE FROM CELL "THE_RESET_SYNC/sync_q_1" 20 ns ; +MULTICYCLE FROM CELL "THE_RESET_SYNC/gen_others_gen_flipflops_2_sync_q_2" 20 ns ; +MULTICYCLE FROM CELL "gen_ethernet_hub_THE_HUB/THE_HUB/proc_SYNC_RESET_reset_i" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io*" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io_0" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/gen_internal_reset_0_SYNC_RESET_MUX_IO_reset_i_mux_io_0" 20 ns ; + + +# +# COMMERCIAL ; +# BLOCK RESETPATHS ; +# BLOCK ASYNCPATHS ; +# +# ######################################### +# # Constraints +# ######################################### +# +# +# ######################################### +# # Frequencies +# ######################################### +# FREQUENCY PORT CLK_F1_TO_F2 100.000000 MHz ; +# FREQUENCY PORT CLK_F2_TO_F1 100.000000 MHz ; +# FREQUENCY NET clk_in 200.000000 MHz ; +# FREQUENCY NET CLK 100.000000 MHz ; +# FREQUENCY NET clk_100 100.000000 MHz ; +# FREQUENCY PORT THE_MEDIA_INTERFACE_2/gen_serdes_0_ext_200_THE_SERDES/PCSC_INST 200.000 MHz ; +# FREQUENCY PORT F1_TO_F2_13 100 MHz; +# FREQUENCY NET "GBE/clk_125" 125.000000 MHz ; +# FREQUENCY PORT GBE/PCS_SERDES/SERDES_GBE/PCSC_INST 125.000 MHz ; +# +# +# # FREQUENCY NET "THE_MEDIA_INTERFACE_0/ff_txhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_1/ff_txhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_2/ff_txhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_3/ff_txhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_0/ff_rxhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_1/ff_rxhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_2/ff_rxhalfclk" 100.000000 MHz ; +# # FREQUENCY NET "THE_MEDIA_INTERFACE_3/ff_rxhalfclk" 100.000000 MHz ; +# +# USE EDGE NET "CLK_F1_TO_F2_c" ; +# # PROHIBIT PRIMARY NET "CLK_F1_TO_F2_c" ; +# # PROHIBIT SECONDARY NET "CLK_F1_TO_F2_c" ; +# +# CLOCK_TO_OUT PORT "F2_TO_F1*" 20 ns CLKNET CLK_100 ; +# INPUT_SETUP PORT "F1_TO_F2*" 3 ns CLKPORT CLK_F1_TO_F2 ; +# +# +# +# ######################################### +# # Locate Serdes +# ######################################### +# LOCATE COMP "GBE/PCS_SERDES/SERDES_GBE/PCSC_INST" SITE "LLPCS" ; +# LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LLPCS" ; +# LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LRPCS" ; +# LOCATE COMP "THE_MEDIA_INTERFACE_2/gen_serdes_0_ext_200_THE_SERDES/PCSC_INST" SITE "URPCS" ; +# LOCATE COMP "THE_MEDIA_INTERFACE_3/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "ULPCS" ; +# +# +# +# ######################################### +# # Locate Logic +# ######################################### +# REGION "MED0" "R86C2" 19 36 ; +# REGION "MED1" "R86C90" 19 36 ; +# REGION "MED2" "R9C90" 18 36 ; +# REGION "MED3" "R9C2" 18 36 ; +# REGION "MEDT" "R40C110" 17 25 ; +# +# REGION "MUXES_UL" "R30C6" 27 20 ; +# REGION "MUXES_UR" "R30C105" 27 20 ; +# REGION "MUXES_LL" "R56C6" 27 20 ; +# REGION "MUXES_LR" "R56C105" 27 20 ; +# +# REGION "BUFFERS_N_HUB_0" "R2C40" 30 63 ; +# REGION "BUFFERS_N_HUB_1" "R28C35" 47 80 ; +# REGION "BUFFERS_N_HUB_3" "R70C40" 40 63 ; +# +# REGION "GBE_REGION" "R34C2" 63 68 ; +# +# LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ; +# LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ; +# LOCATE UGROUP "THE_MEDIA_INTERFACE_2/media_interface_group" REGION "MED2" ; +# LOCATE UGROUP "THE_MEDIA_INTERFACE_3/media_interface_group" REGION "MED3" ; +# LOCATE UGROUP "THE_MEDIA_INTERFACE_T/media_interface_group" REGION "MEDT" ; +# +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "MUXES_LR" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "MUXES_UR" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "MUXES_UL" ; +# +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# +# +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# +# +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_normal_hub_THE_HUB/hub_control/RegIO_group" REGION "BUFFERS_N_HUB_3" ; +# +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +# +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; +# +# LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/hub_control/RegIO_group" REGION "BUFFERS_N_HUB_3" ; +# +# +# ######################################### +# # Place Serdes Clocks in General Routing +# ######################################### +# # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE_0/ff_rxhalfclk" ; +# # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE_0/ff_rxhalfclk" ; +# # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE_1/ff_rxhalfclk" ; +# # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE_1/ff_rxhalfclk" ; +# # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE_2/ff_rxhalfclk" ; +# # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE_2/ff_rxhalfclk" ; +# # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE_3/ff_rxhalfclk" ; +# # PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE_3/ff_rxhalfclk" ; +# +# ######################################### +# # Longer Delays for Reset +# ######################################### +# MULTICYCLE FROM CELL "THE_RESET_SYNC/sync_q_1" 20 ns ; +# MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io*" 20 ns ; +# MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io_0" 20 ns ; +# MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/gen_internal_reset_0_SYNC_RESET_MUX_IO_reset_i_mux_io_0" 20 ns ; +# + + diff --git a/hub2.xcf b/hub2.xcf new file mode 100644 index 0000000..f1b571e --- /dev/null +++ b/hub2.xcf @@ -0,0 +1,133 @@ + + + + + + JTAG + + 1 + NA + Generic JTAG Device + JTAG-NOP + All + JTAG-NOP + + 10 + 1111111111 + 1 + 0 + + Bypass + + + + 2 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /d/jspc22/trb/cvs/hub2/workdir/hub2_fpga1.bit + /home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 4/8/2011 14:28:42 + Fast Program + + + + 3 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /home/hadaq/hub2_fpga2_06_28.bit + /home/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 6/28/2010 13:38:53 + Fast Program + + + + 4 + Lattice + ispPAC Power Manager II + ispPAC-POWR1014A + 0x00145043 + 48-pin TQFP + ispPAC-POWR1014A-XXT48 + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + TMS LOW; + TCK LOW; + TDI LOW; + TDO LOW; + CableEN HIGH; + + + + EzUSB-0 + + diff --git a/hub2_fpga1.p2t b/hub2_fpga1.p2t new file mode 100644 index 0000000..fba4c00 --- /dev/null +++ b/hub2_fpga1.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 19 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + diff --git a/hub2_fpga1.prj b/hub2_fpga1.prj new file mode 100644 index 0000000..0d64766 --- /dev/null +++ b/hub2_fpga1.prj @@ -0,0 +1,121 @@ +#-- Synplicity, Inc. +#-- Version 9.0 +#-- Project file ../rich/rich.prj +#-- Written on Mon Aug 11 17:12:10 2008 + + +#add_file options + +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "version.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf4.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf3.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf2.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_med_16_IC.vhd" + + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/pll_in100_out100.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd" + + +add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd" +add_file -vhdl -lib work "hub2_fpga1.vhd" + + + +#implementation: "workdir" +impl -add workdir -type fpga + + +#device options +set_option -technology LATTICE-ECP2M +set_option -part LFE2M100E +set_option -package F900C +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -resource_sharing 0 +set_option -top_module "hub2_fpga1" + +#map options +set_option -frequency 110 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +set_option -force_gsr auto +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 + + + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/hub2_fpga1.edf" + + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" diff --git a/hub2_fpga1.vhd b/hub2_fpga1.vhd new file mode 100644 index 0000000..edf0f11 --- /dev/null +++ b/hub2_fpga1.vhd @@ -0,0 +1,527 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; + + +entity hub2_fpga1 is + generic( + USED_QUADS : integer range 1 to 3 := 3; + USE_INTER_FPGA_LINES : integer range 0 to 1 := c_YES + ); + port( + --Clocks + CLK100_P : in std_logic; + CLK_F1_TO_F2 : out std_logic; + --Resets + RESET_N : in std_logic; + --LED + SFP_LED_GREEN : out std_logic_vector(16 downto 1); + SFP_LED_ORANGE : out std_logic_vector(16 downto 1); + --Connection to TRB + ADO_TTL : inout std_logic_vector(45 downto 0); + --FPGA2 + F1_TO_F2 : out std_logic_vector(31 downto 0); + F2_TO_F1 : in std_logic_vector(31 downto 0); + --SFP + TXP : out std_logic_vector(16 downto 5); + TXN : out std_logic_vector(16 downto 5); + RXP : in std_logic_vector(16 downto 5); + RXN : in std_logic_vector(16 downto 5); + TX_DIS : out std_logic_vector(16 downto 5); --disable sfp + SFP_LOS : in std_logic_vector(16 downto 5); --sfp loss of signal + SFP_MOD0 : in std_logic_vector(16 downto 5); --sfp detect + SFP_MOD1 : in std_logic_vector(16 downto 5); --i2c + SFP_MOD2 : in std_logic_vector(16 downto 5); --i2c + --ONEWIRE + ONEWIRE : inout std_logic; + ONEWIRE_MONITOR : out std_logic; + --DEBUG + TEST1 : out std_logic_vector(26 downto 0) + ); + attribute syn_useioff : boolean; + attribute syn_useioff of F1_TO_F2 : signal is true; + attribute syn_useioff of F2_TO_F1 : signal is true; + attribute syn_useioff of ONEWIRE : signal is false; + attribute syn_useioff of ONEWIRE_MONITOR : signal is false; + +end entity; + +architecture hub2_fpga1_arch of hub2_fpga1 is + + attribute syn_sharing : string; + attribute syn_sharing of hub2_fpga1_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of hub2_fpga1_arch : architecture is "firm"; + + constant mii : integer := USED_QUADS*4 + USE_INTER_FPGA_LINES; + + signal clk_en : std_logic; + signal clk_100 : std_logic; + signal clk : std_logic; + signal pll_lock : std_logic; + signal reset_in : std_logic := '1'; + signal reset : std_logic := '1'; + signal next_reset : std_logic := '1'; + signal reset_async : std_logic := '1'; + signal reset_counter : std_logic_vector(11 downto 0); + signal buf_test1: std_logic_vector(26 downto 1); + + signal med_data_in : std_logic_vector(17*16-1 downto 0); + signal med_data_out : std_logic_vector(17*16-1 downto 0); + signal med_packet_num_in : std_logic_vector(17*c_NUM_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector(17*c_NUM_WIDTH-1 downto 0); + signal med_dataready_in : std_logic_vector(16 downto 0); + signal med_dataready_out : std_logic_vector(16 downto 0); + signal med_read_in : std_logic_vector(16 downto 0); + signal med_read_out : std_logic_vector(16 downto 0); + + signal med_stat_op : std_logic_vector(17*16-1 downto 0); + signal med_ctrl_op : std_logic_vector(17*16-1 downto 0); + signal med_stat_debug : std_logic_vector(17*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector(17*16-1 downto 0); + signal sd_present : std_logic_vector(12 downto 1); + signal buf_SFP_LED_GREEN : std_logic_vector(16 downto 1); + signal buf_SFP_LED_ORANGE: std_logic_vector(16 downto 1); + signal buf_SFP_LOS : std_logic_vector(16 downto 5); + signal buf_SFP_MOD0 : std_logic_vector(16 downto 5); + signal HUB_STAT_DEBUG : std_logic_vector(31 downto 0); + + signal make_trbnet_reset : std_logic; + signal async_sampler : std_logic_vector(7 downto 0) := (others => '0'); + signal async_pulse : std_logic := '0'; + + signal IOBUF_STAT_INIT_OBUF_DEBUG : std_logic_vector (mii*32*2**(c_MUX_WIDTH-1)-1 downto 0); + signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector (mii*32*2**(c_MUX_WIDTH-1)-1 downto 0); + +begin + + clk_en <= '1'; + reset_in <= not RESET_N; + reset_async <= not pll_lock or async_pulse; + clk <= clk_100; + reset <= next_reset; + make_trbnet_reset <= MED_STAT_OP(13) or MED_STAT_OP(13+16); + + THE_PLL : pll_in100_out100 + port map( CLK => CLK100_P, + CLKOP => clk_100, + LOCK => pll_lock + ); + + + THE_ASYNC_SAMPLER_PROC: process( CLK100_P ) + begin + if( rising_edge(CLK100_P) ) then + async_sampler(7 downto 0) <= async_sampler(6 downto 0) & reset_in; + async_pulse <= and_all(async_sampler); + end if; + end process; + +--------------------------------------------------------------------- +-- Reset process +--------------------------------------------------------------------- + + THE_RESET_COUNTER_PROC: process( pll_lock, clk_100 ) + begin + if( pll_lock = '0' or async_pulse = '1') then + -- asynchronous reset by PLL lock signal only + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( rising_edge(clk_100) ) then + if ( make_trbnet_reset = '1' ) then + -- synchronous reset by network + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( reset_counter = x"EEE" ) then + reset_counter <= x"EEE"; + next_reset <= '0'; + else + reset_counter <= reset_counter + 1; + next_reset <= '1'; + end if; + end if; + end process; +-- THE_RESET_COUNTER_PROC: process( CLK100_P ) +-- begin +-- if rising_edge(CLK100_P) then +-- reset_counter <= reset_counter + 1; +-- next_reset <= '1'; +-- if reset_in = '1' or pll_lock = '0' or make_trbnet_reset = '1' then +-- reset_counter <= (others => '0'); +-- next_reset <= '1'; +-- elsif( reset_counter = x"EE" ) then +-- next_reset <= '0'; +-- reset_counter <= x"EE"; +-- end if; +-- end if; +-- end process; + +-- THE_RESET_SYNC : signal_sync +-- generic map( +-- DEPTH => 2, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => reset_in, +-- D_IN(0) => next_reset, +-- CLK0 => clk, +-- CLK1 => clk, +-- D_OUT(0) => reset +-- ); + +--------------------------------------------------------------------- +-- Serdes +--------------------------------------------------------------------- + + PROC_SFP_LOS : process(CLK) + begin + if rising_edge(CLK) then + buf_SFP_LOS <= SFP_LOS; + buf_SFP_MOD0<= SFP_MOD0; + end if; + end process; + + gen_inter_fpga : if USE_INTER_FPGA_LINES = 1 generate + THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC + port map( + CLK => CLK, + CLK_EN => clk_en, + RESET => reset, + + --Internal Connection + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + + DATA_OUT => F1_TO_F2(31 downto 16), + DATA_VALID_OUT => F1_TO_F2(15), + DATA_CTRL_OUT => F1_TO_F2(14), + DATA_CLK_OUT => CLK_F1_TO_F2, --F1_TO_F2(13), + DATA_IN => F2_TO_F1(31 downto 16), + DATA_VALID_IN => F2_TO_F1(15), + DATA_CTRL_IN => F2_TO_F1(14), + DATA_CLK_IN => F2_TO_F1(1), + + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => med_stat_debug(63 downto 0) + ); + end generate; + + THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_4_gbe + generic map( + REVERSE_ORDER => c_NO + ) + port map( + CLK => CLK100_P, + SYSCLK => clk, + RESET => reset, + CLEAR => reset_async, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out(5*16-1 downto 1*16), + MED_PACKET_NUM_IN => med_packet_num_out(5*3-1 downto 1*3), + MED_DATAREADY_IN => med_dataready_out(4 downto 1), + MED_READ_OUT => med_read_in(4 downto 1), + MED_DATA_OUT => med_data_in(5*16-1 downto 1*16), + MED_PACKET_NUM_OUT => med_packet_num_in(5*3-1 downto 1*3), + MED_DATAREADY_OUT => med_dataready_in(4 downto 1), + MED_READ_IN => med_read_out(4 downto 1), + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => RXP(8 downto 5), + SD_RXD_N_IN => RXN(8 downto 5), + SD_TXD_P_OUT => TXP(8 downto 5), + SD_TXD_N_OUT => TXN(8 downto 5), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(8 downto 5), + SD_LOS_IN => buf_SFP_LOS(8 downto 5), + -- Status and control port + STAT_OP => med_stat_op(5*16-1 downto 1*16), + CTRL_OP => med_ctrl_op(5*16-1 downto 1*16), + STAT_DEBUG => med_stat_debug(5*64-1 downto 1*64), + CTRL_DEBUG => med_ctrl_debug(5*16-1 downto 1*16) + ); + + THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_4_gbe + generic map( + REVERSE_ORDER => c_YES + ) + port map( + CLK => CLK100_P, + SYSCLK => clk, + RESET => reset, + CLEAR => reset_async, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out(9*16-1 downto 5*16), + MED_PACKET_NUM_IN => med_packet_num_out(9*3-1 downto 5*3), + MED_DATAREADY_IN => med_dataready_out(8 downto 5), + MED_READ_OUT => med_read_in(8 downto 5), + MED_DATA_OUT => med_data_in(9*16-1 downto 5*16), + MED_PACKET_NUM_OUT => med_packet_num_in(9*3-1 downto 5*3), + MED_DATAREADY_OUT => med_dataready_in(8 downto 5), + MED_READ_IN => med_read_out(8 downto 5), + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => RXP(12 downto 9), + SD_RXD_N_IN => RXN(12 downto 9), + SD_TXD_P_OUT => TXP(12 downto 9), + SD_TXD_N_OUT => TXN(12 downto 9), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(12 downto 9), + SD_LOS_IN => buf_SFP_LOS(12 downto 9), + -- Status and control port + STAT_OP => med_stat_op(9*16-1 downto 5*16), + CTRL_OP => med_ctrl_op(9*16-1 downto 5*16), + STAT_DEBUG => med_stat_debug(9*64-1 downto 5*64), + CTRL_DEBUG => med_ctrl_debug(9*16-1 downto 5*16) + ); + + THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_4_gbe + generic map( + REVERSE_ORDER => c_YES + ) + port map( + CLK => CLK100_P, + SYSCLK => clk, + RESET => reset, + CLEAR => reset_async, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out(13*16-1 downto 9*16), + MED_PACKET_NUM_IN => med_packet_num_out(13*3-1 downto 9*3), + MED_DATAREADY_IN => med_dataready_out(12 downto 9), + MED_READ_OUT => med_read_in(12 downto 9), + MED_DATA_OUT => med_data_in(13*16-1 downto 9*16), + MED_PACKET_NUM_OUT => med_packet_num_in(13*3-1 downto 9*3), + MED_DATAREADY_OUT => med_dataready_in(12 downto 9), + MED_READ_IN => med_read_out(12 downto 9), + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => RXP(16 downto 13), + SD_RXD_N_IN => RXN(16 downto 13), + SD_TXD_P_OUT => TXP(16 downto 13), + SD_TXD_N_OUT => TXN(16 downto 13), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(16 downto 13), + SD_LOS_IN => buf_SFP_LOS(16 downto 13), + -- Status and control port + STAT_OP => med_stat_op(13*16-1 downto 9*16), + CTRL_OP => med_ctrl_op(13*16-1 downto 9*16), + STAT_DEBUG => med_stat_debug(13*64-1 downto 9*64), + CTRL_DEBUG => med_ctrl_debug(13*16-1 downto 9*16) + ); + + +-- THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_4_gbe +-- generic map( +-- REVERSE_ORDER => c_YES +-- ) +-- port map( +-- CLK => CLK100_P, +-- SYSCLK => clk, +-- RESET => reset, +-- CLEAR => reset, +-- CLK_EN => clk_en, +-- --Internal Connection +-- MED_DATA_IN => med_data_out(17*16-1 downto 13*16), +-- MED_PACKET_NUM_IN => med_packet_num_out(17*3-1 downto 13*3), +-- MED_DATAREADY_IN => med_dataready_out(16 downto 13), +-- MED_READ_OUT => med_read_in(16 downto 13), +-- MED_DATA_OUT => med_data_in(17*16-1 downto 13*16), +-- MED_PACKET_NUM_OUT => med_packet_num_in(17*3-1 downto 13*3), +-- MED_DATAREADY_OUT => med_dataready_in(16 downto 13), +-- MED_READ_IN => med_read_out(16 downto 13), +-- REFCLK2CORE_OUT => open, +-- --SFP Connection +-- SD_RXD_P_IN => RXP(16 downto 13), +-- SD_RXD_N_IN => RXN(16 downto 13), +-- SD_TXD_P_OUT => TXP(16 downto 13), +-- SD_TXD_N_OUT => TXN(16 downto 13), +-- SD_REFCLK_P_IN => open, +-- SD_REFCLK_N_IN => open, +-- SD_PRSNT_N_IN => buf_SFP_MOD0(16 downto 13), +-- SD_LOS_IN => buf_SFP_LOS(16 downto 13), +-- -- Status and control port +-- STAT_OP => med_stat_op(17*16-1 downto 13*16), +-- CTRL_OP => med_ctrl_op(17*16-1 downto 13*16), +-- STAT_DEBUG => med_stat_debug(17*64-1 downto 13*64), +-- CTRL_DEBUG => med_ctrl_debug(17*16-1 downto 13*16) +-- ); + + med_ctrl_debug <= (others => '0'); + +--------------------------------------------------------------------- +-- The Hub +--------------------------------------------------------------------- + + + THE_HUB : trb_net16_hub_base + generic map ( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => mii, + MII_IS_UPLINK => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + MII_IS_DOWNLINK => (0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), + MII_IS_UPLINK_ONLY => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + HARDWARE_VERSION => x"62100000", + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT=> med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + + INT_INIT_READ_IN => (others => '0'), + INT_INIT_DATAREADY_IN => (others => '0'), + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_IN => (others => '0'), + INT_REPLY_DATAREADY_IN => (others => '0'), + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + ONEWIRE => ONEWIRE, + ONEWIRE_MONITOR_IN => '0', + ONEWIRE_MONITOR_OUT => ONEWIRE_MONITOR, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => HUB_STAT_DEBUG, + IOBUF_STAT_INIT_OBUF_DEBUG => IOBUF_STAT_INIT_OBUF_DEBUG (mii*32*2**(c_MUX_WIDTH-1)-1 downto 0), + IOBUF_STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG (mii*32*2**(c_MUX_WIDTH-1)-1 downto 0) + ); + + +--------------------------------------------------------------------- +-- Funny LEDs ;-) +--------------------------------------------------------------------- + + buf_SFP_LED_GREEN (4 downto 1) <= (others => '1'); + buf_SFP_LED_ORANGE(4 downto 1) <= (others => '1'); + gen_non_leds : if USED_QUADS < 3 generate + buf_SFP_LED_GREEN (16 downto USED_QUADS*4+5) <= (others => '1'); + buf_SFP_LED_ORANGE(16 downto USED_QUADS*4+5) <= (others => '1'); + end generate; + + gen_leds : for i in 1 to USED_QUADS*4 generate + buf_SFP_LED_ORANGE(i+4) <= not (med_stat_op(i*16+10) or med_stat_op(i*16+11) or med_stat_op(i*16+14)); + buf_SFP_LED_GREEN(i+4) <= not med_stat_op(i*16+9); + end generate; + + SFP_LED_GREEN <= buf_SFP_LED_GREEN; + SFP_LED_ORANGE <= buf_SFP_LED_ORANGE; + + TEST1(11) <= MED_STAT_OP(13); + TEST1(12) <= reset; + TEST1(13) <= MED_CTRL_OP(15+16); + TEST1(14) <= MED_CTRL_OP(15); + TEST1(22 downto 15) <= med_stat_debug(15 downto 8); + TEST1(23) <= med_stat_debug(0); + TEST1(24) <= med_stat_debug(1); + + +-- buf_test1(18 downto 11) <= MED_STAT_DEBUG(7 downto 0); +-- -- buf_test1(26 downto 19) <= med_data_out(19 downto 16) & med_data_out(3 downto 1) & MED_STAT_DEBUG(8); +-- -- -- buf_test1(8 downto 1) <= med_dataready_in(0) & med_data_in(6 downto 0); + +-- buf_test1(26 downto 11) <= MED_DATA_OUT(7 downto 0) & MED_DATA_IN(7 downto 0); --MED_STAT_DEBUG(1*64+47 downto 1*64+32); +-- buf_test1(2 downto 1) <= MED_DATAREADY_OUT(0) & MED_DATAREADY_IN(0); +-- buf_test1(4 downto 3) <= MED_DATAREADY_OUT(1) & MED_DATAREADY_IN(1); +-- buf_test1(8 downto 5) <= MED_DATA_IN(19 downto 16); + + +-- buf_test1(26 downto 11) <= MED_STAT_DEBUG(1*64+39 downto 1*64+32) & MED_STAT_DEBUG(0*64+39 downto 0*64+32); +-- buf_test1(4 downto 1) <= MED_STAT_DEBUG(1*64+60 downto 1*64+59) & MED_STAT_DEBUG(0*64+60 downto 0*64+59); +-- buf_test1(8 downto 5) <= MED_STAT_OP(15+64) & MED_STAT_OP(13+64) & MED_STAT_OP(15) & MED_STAT_OP(13); + +-- -- -- buf_test1(26 downto 11) <= med_stat_debug(15 downto 0); --HUB_STAT_DEBUG(31 downto 16); + +-- buf_test1(2 downto 1) <= MED_STAT_DEBUG(1*64+60 downto 1*64+59); +-- buf_test1(6 downto 3) <= MED_STAT_DEBUG(1*64+3 downto 1*64+0); +-- buf_test1(8 downto 5) <= "0000"; +-- +-- PROC_LED : process(clk) +-- begin +-- if rising_edge(clk) then +-- TEST1(4 downto 1) <= IOBUF_STAT_REPLY_OBUF_DEBUG(3*32+10 downto 3*32+7); --wcnt sfp1 +-- TEST1(8 downto 5) <= IOBUF_STAT_REPLY_OBUF_DEBUG(3*32+15 downto 3*32+12); --bsm sfp1 +-- TEST1(14 downto 9) <= MED_DATA_OUT(5 downto 0); --data link 0 +-- TEST1(15) <= MED_DATAREADY_OUT(0); --dataready link 0 +-- TEST1(18 downto 16) <= MED_PACKET_NUM_OUT(2 downto 0); --packet num link 0 +-- TEST1(24 downto 19) <= MED_DATA_IN(21 downto 16); --data sfp1 +-- TEST1(26 downto 25) <= MED_DATAREADY_IN(2 downto 1); --packet num sfp1 +-- ADO_TTL(42) <= IOBUF_STAT_INIT_OBUF_DEBUG(3*32+3); --sbuf sfp0 dataready in +-- ADO_TTL(43) <= IOBUF_STAT_INIT_OBUF_DEBUG(7*32+3); --sbuf sfp1 dataready in +-- ADO_TTL(44) <= IOBUF_STAT_INIT_OBUF_DEBUG(11*32+3); --sbuf sfp2 dataready in +-- end if; +-- end process; +-- TEST1(0) <= CLK; +-- TEST1(0) <= '0'; + +-- end if; +-- end process; + + +--HUB_STAT_DEBUG +-- STAT_DEBUG(0) <= got_trm(0); +-- STAT_DEBUG(1) <= got_trm(1); +-- STAT_DEBUG(2) <= REPLY_POOL_DATAREADY; +-- STAT_DEBUG(3) <= REPLY_DATAREADY_IN(0); +-- STAT_DEBUG(4) <= buf_REPLY_READ_OUT(0); +-- STAT_DEBUG(5) <= comb_REPLY_muxed_DATA(14); +-- +-- STAT_DEBUG(6) <= REPLY_DATA_IN(14); +-- STAT_DEBUG(7) <= REPLY_DATA_IN(30); +-- STAT_DEBUG(8) <= got_all_DHDR; --REPLY_DATA_IN(46); +-- STAT_DEBUG(9) <= locked; +-- STAT_DEBUG(13 downto 10) <= reply_fsm_state(3 downto 0); +-- STAT_DEBUG(14) <= REPLY_POOL_next_read; + + +-- fsm_stat_debug(3 downto 0) <= state_bits; +-- fsm_stat_debug(4) <= align_me; +-- fsm_stat_debug(5) <= buf_swap_bytes; +-- fsm_stat_debug(6) <= resync; +-- fsm_stat_debug(7) <= sfp_missing_in; +-- fsm_stat_debug(8) <= sfp_los_in; +-- STAT_DEBUG(i*64+47 downto i*64+32) <= rx_data(i*16+15 downto i*16); +--starting at fsm_stat_debug(48) +-- ff_disp_err_ch3 => link_error(3)(9 downto 8), +-- ff_cv_ch3 => link_error(3)(1 downto 0), +-- ffs_rlos_lo_ch3 => link_error(3)(2), +-- ffs_cc_underrun_ch3 => link_error(3)(3), +-- ffs_cc_overrun_ch3 => link_error(3)(4), +-- ffs_txfbfifo_error_ch3 => link_error(3)(5), +-- ffs_rxfbfifo_error_ch3 => link_error(3)(6), +-- ffs_rlol_ch3 => link_error(3)(7), + + +end architecture; \ No newline at end of file diff --git a/hub2_fpga2.lpf b/hub2_fpga2.lpf new file mode 100755 index 0000000..346c9cf --- /dev/null +++ b/hub2_fpga2.lpf @@ -0,0 +1,587 @@ +COMMERCIAL; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +######################################################################################################### +######################################################################################################### +######################################### +# Constraints +######################################### + + +######################################### +# IP Cores +######################################### + +#TSMAC +#Begin multicycle path from constraints +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +# MULTICYCLE FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X; +# MULTICYCLE TO CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +# MULTICYCLE FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X; +#End multicycle path from constraints + +#Begin false path from constraints +# BLOCK PATH FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; +# BLOCK PATH FROM CELL "gen_ethernet_hub_GBE/MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; +#End false path from constraints + + +######################################### +# Frequencies +######################################### +FREQUENCY PORT CLK_F1_TO_F2 100.000000 MHz ; +FREQUENCY NET CLK_IN 200.000000 MHz ; +FREQUENCY NET CLK_100 100.000000 MHz ; +FREQUENCY PORT F1_TO_F2_1 100.000000 MHz ; + +FREQUENCY NET "THE_MEDIA_INTERFACE_3/gen_serdes_0_200_THE_SERDES/ff_txfullclk" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_INTERFACE_2/gen_serdes_0_200_ext_THE_SERDES/ff_txfullclk" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_INTERFACE_1/gen_serdes_0_200_THE_SERDES/ff_txfullclk" 100.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125" 125.000000 MHz ; +#gk 29.04.10 +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/refclk2core" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/ff_txfullclk" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/refclockcore" 125.000000 MHz ; + +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; +FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; + +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.REFCK2CORE" 125.000000 MHz ; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; +FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; + +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/refclk2core" 125.000000 MHz ; +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/ff_txfullclk" 125.000000 MHz ; +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; + +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/refclockcore" 125.000000 MHz ; + +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; +#FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; + +#FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/PCSC_INST.REFCK2CORE" 125.000000 MHz ; +#FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; +#FREQUENCY PORT "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; + +USE EDGE NET "CLK_F1_TO_F2_c" ; + +CLOCK_TO_OUT PORT "F2_TO_F1*" 20 ns CLKNET CLK_100 ; +INPUT_SETUP PORT "F1_TO_F2*" 3 ns CLKPORT CLK_F1_TO_F2 ; + +######################################### +# Locate Serdes +######################################### + +# gk 29.04.10 +LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/clk_ext_SERDES_GBE/PCSC_INST" SITE "LLPCS" ; +#LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/SERDES_GBE/PCSC_INST" SITE "LLPCS" ; +# LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LLPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "LRPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_2/gen_serdes_0_ext_200_THE_SERDES/PCSC_INST" SITE "URPCS" ; +LOCATE COMP "THE_MEDIA_INTERFACE_3/gen_serdes_0_200_THE_SERDES/PCSC_INST" SITE "ULPCS" ; + + + +######################################### +# Locate Logic +######################################### +# REGION "MED0" "R86C2" 19 36 ; +REGION "MED0" "R86C2" 19 45 ; +REGION "MED1" "R86C90" 19 36 ; +REGION "MED2" "R9C90" 18 36 ; +REGION "MED3" "R9C2" 30 36 ; +# REGION "MEDT" "R40C100" 17 25 ; + +REGION "BUFFERS_N_HUB_0" "R2C40" 30 63 ; +REGION "BUFFERS_N_HUB_1" "R28C44" 47 72 ; +REGION "BUFFERS_N_HUB_3" "R77C40" 35 63 ; +# REGION "GBE_REGION" "R34C2" 63 68 ; +REGION "GBE_REGION" "R32C2" 63 68 ; + +# OLD +#REGION "BUFFERS_N_HUB_0" "R2C40" 35 63 ; +#REGION "BUFFERS_N_HUB_1" "R35C35" 40 80 ; +#REGION "BUFFERS_N_HUB_3" "R70C40" 40 63 ; +#REGION "GBE_REGION" "R25C2" 63 68 ; + +#gk 29.04.10 +LOCATE UGROUP "gen_ethernet_hub_GBE/imp_gen_serdes_extclk_gen_PCS_SERDES/media_interface_group" REGION "MED0" ; +#LOCATE UGROUP "gen_ethernet_hub_GBE/imp_gen_PCS_SERDES/media_interface_group" REGION "MED0" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_2/media_interface_group" REGION "MED2" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_3/media_interface_group" REGION "MED3" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE_T/media_interface_group" REGION "MED3" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; + + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_normal_hub_THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_0/IOBUF_group" REGION "BUFFERS_N_HUB_0" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_1/IOBUF_group" REGION "BUFFERS_N_HUB_1" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_IOBUF_3/IOBUF_group" REGION "BUFFERS_N_HUB_3" ; + + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_0" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "BUFFERS_N_HUB_1" ; +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_ethernet_hub_THE_HUB/THE_HUB/hub_control/RegIO_group" REGION "BUFFERS_N_HUB_3" ; + +LOCATE UGROUP "gen_ethernet_hub_GBE/GBE_BUF_group" REGION "GBE_REGION" ; + +######################################### +# Longer Delays for Reset +######################################### +MULTICYCLE FROM CELL "THE_RESET_SYNC/sync_q_1" 20 ns ; +MULTICYCLE FROM CELL "THE_RESET_SYNC/gen_others_gen_flipflops_2_sync_q_2" 20 ns ; +MULTICYCLE FROM CELL "gen_ethernet_hub_THE_HUB/THE_HUB/proc_SYNC_RESET_reset_i" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io*" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/reset_i_mux_io_0" 20 ns ; +MULTICYCLE FROM CELL "gen_normal_hub_THE_HUB/gen_internal_reset_0_SYNC_RESET_MUX_IO_reset_i_mux_io_0" 20 ns ; + + + +######################################################################################################### +######################################################################################################### + +IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN; + +######################################### +# Clock & Reset +######################################### +# LOCATE COMP "CLK_F2_TO_F1" SITE "AC30"; +LOCATE COMP "CLK_F1_TO_F2" SITE "N1"; + +IOBUF PORT "CLK_F1_TO_F2" IO_TYPE=LVDS25 PULLMODE=NONE ; +# IOBUF PORT "CLK_F2_TO_F1" IO_TYPE=LVDS25 PULLMODE=NONE ; + +GSR_NET NET "GSR_N"; + +# LOCATE COMP "ADDON_RESET" SITE "C17"; +# LOCATE COMP "RESET_N" SITE "B17"; +# LOCATE COMP "SUPPL_RESET_N" SITE "A17"; + + +######################################### +# Connection to FPGA1 +######################################### +# LOCATE COMP "F1_TO_F2_0" SITE "AD2"; +# LOCATE COMP "F1_TO_F2_1" SITE "AC5"; +# LOCATE COMP "F1_TO_F2_2" SITE "AC4"; +# LOCATE COMP "F1_TO_F2_3" SITE "AA5"; +# LOCATE COMP "F1_TO_F2_4" SITE "AA8"; +# LOCATE COMP "F1_TO_F2_5" SITE "Y3"; +# LOCATE COMP "F1_TO_F2_6" SITE "Y7"; +# LOCATE COMP "F1_TO_F2_7" SITE "Y5"; +# LOCATE COMP "F1_TO_F2_8" SITE "W2"; +# LOCATE COMP "F1_TO_F2_9" SITE "W5"; +# LOCATE COMP "F1_TO_F2_10" SITE "V5"; +# LOCATE COMP "F1_TO_F2_11" SITE "V9"; +# LOCATE COMP "F1_TO_F2_12" SITE "V8"; +# LOCATE COMP "F1_TO_F2_13" SITE "U9"; +LOCATE COMP "F1_TO_F2_14" SITE "U7"; +LOCATE COMP "F1_TO_F2_15" SITE "R1"; +LOCATE COMP "F1_TO_F2_16" SITE "R8"; +LOCATE COMP "F1_TO_F2_17" SITE "R5"; +LOCATE COMP "F1_TO_F2_18" SITE "P6"; +LOCATE COMP "F1_TO_F2_19" SITE "P9"; +LOCATE COMP "F1_TO_F2_20" SITE "P5"; +LOCATE COMP "F1_TO_F2_21" SITE "N5"; +LOCATE COMP "F1_TO_F2_22" SITE "N9"; +LOCATE COMP "F1_TO_F2_23" SITE "N8"; +LOCATE COMP "F1_TO_F2_24" SITE "L8"; +LOCATE COMP "F1_TO_F2_25" SITE "L9"; +LOCATE COMP "F1_TO_F2_26" SITE "K7"; +LOCATE COMP "F1_TO_F2_27" SITE "J5"; +LOCATE COMP "F1_TO_F2_28" SITE "H1"; +LOCATE COMP "F1_TO_F2_29" SITE "F1"; +LOCATE COMP "F1_TO_F2_30" SITE "E3"; +LOCATE COMP "F1_TO_F2_31" SITE "E2"; +DEFINE PORT GROUP "f1f2_group" "F1_TO_F2*" ; +IOBUF GROUP "f1f2_group" IO_TYPE=LVDS25 PULLMODE=NONE ; + +LOCATE COMP "F2_TO_F1_0" SITE "AC1"; +LOCATE COMP "F2_TO_F1_1" SITE "AC7"; +LOCATE COMP "F2_TO_F1_2" SITE "AB2"; +LOCATE COMP "F2_TO_F1_3" SITE "AB4"; +LOCATE COMP "F2_TO_F1_4" SITE "AA1"; +LOCATE COMP "F2_TO_F1_5" SITE "Y1"; +LOCATE COMP "F2_TO_F1_6" SITE "Y9"; +LOCATE COMP "F2_TO_F1_7" SITE "W3"; +LOCATE COMP "F2_TO_F1_8" SITE "V1"; +LOCATE COMP "F2_TO_F1_9" SITE "U1"; +LOCATE COMP "F2_TO_F1_10" SITE "U3"; +LOCATE COMP "F2_TO_F1_11" SITE "U5"; +LOCATE COMP "F2_TO_F1_12" SITE "T3"; +LOCATE COMP "F2_TO_F1_13" SITE "T5"; +LOCATE COMP "F2_TO_F1_14" SITE "R3"; +LOCATE COMP "F2_TO_F1_15" SITE "P3"; +LOCATE COMP "F2_TO_F1_16" SITE "M1"; +LOCATE COMP "F2_TO_F1_17" SITE "M4"; +LOCATE COMP "F2_TO_F1_18" SITE "M6"; +LOCATE COMP "F2_TO_F1_19" SITE "L1"; +LOCATE COMP "F2_TO_F1_20" SITE "L3"; +LOCATE COMP "F2_TO_F1_21" SITE "L5"; +LOCATE COMP "F2_TO_F1_22" SITE "K2"; +LOCATE COMP "F2_TO_F1_23" SITE "K6"; +LOCATE COMP "F2_TO_F1_24" SITE "J3"; +LOCATE COMP "F2_TO_F1_25" SITE "H3"; +LOCATE COMP "F2_TO_F1_26" SITE "J8"; +LOCATE COMP "F2_TO_F1_27" SITE "H5"; +LOCATE COMP "F2_TO_F1_28" SITE "G2"; +LOCATE COMP "F2_TO_F1_29" SITE "G5"; +LOCATE COMP "F2_TO_F1_30" SITE "G6"; +LOCATE COMP "F2_TO_F1_31" SITE "E1"; +DEFINE PORT GROUP "f2f1_group" "F2_TO_F1*" ; +IOBUF GROUP "f2f1_group" IO_TYPE=LVDS25 PULLMODE=NONE ; + + +######################################### +# LED +######################################### +LOCATE COMP "SFP_LED_GREEN_17" SITE "AG19"; +LOCATE COMP "SFP_LED_GREEN_18" SITE "AJ17"; +LOCATE COMP "SFP_LED_GREEN_19" SITE "E23"; +LOCATE COMP "SFP_LED_GREEN_20" SITE "E26"; +LOCATE COMP "SFP_LED_ORANGE_17" SITE "AG22"; +LOCATE COMP "SFP_LED_ORANGE_18" SITE "AH17"; +LOCATE COMP "SFP_LED_ORANGE_19" SITE "D23"; +LOCATE COMP "SFP_LED_ORANGE_20" SITE "D26"; +# DEFINE PORT GROUP "sfp_led_group" "SFP_LED*" ; +# IOBUF GROUP "sfp_led_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +######################################### +# SFP Control Signals +######################################### +LOCATE COMP "SFP_MOD0_17" SITE "AG20"; +LOCATE COMP "SFP_MOD0_18" SITE "AE24"; +LOCATE COMP "SFP_MOD0_19" SITE "AD24"; +LOCATE COMP "SFP_MOD0_20" SITE "AC18"; +# LOCATE COMP "SFP_MOD1_17" SITE "AG21"; +# LOCATE COMP "SFP_MOD1_18" SITE "AE25"; +# LOCATE COMP "SFP_MOD1_19" SITE "AD17"; +# LOCATE COMP "SFP_MOD1_20" SITE "AC19"; +# LOCATE COMP "SFP_MOD2_17" SITE "AG18"; +# LOCATE COMP "SFP_MOD2_18" SITE "AE17"; +# LOCATE COMP "SFP_MOD2_19" SITE "AD16"; +# LOCATE COMP "SFP_MOD2_20" SITE "AC17"; +DEFINE PORT GROUP "sfp_mod_group" "SFP_MOD*" ; +IOBUF GROUP "sfp_mod_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + +LOCATE COMP "SFP_LOS_17" SITE "AF21"; +LOCATE COMP "SFP_LOS_18" SITE "AE18"; +LOCATE COMP "SFP_LOS_19" SITE "AD23"; +LOCATE COMP "SFP_LOS_20" SITE "AC23"; +DEFINE PORT GROUP "sfp_los_group" "SFP_LOS*" ; +IOBUF GROUP "sfp_los_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + +LOCATE COMP "SFP_DIS_17" SITE "AF19"; +LOCATE COMP "SFP_DIS_18" SITE "AE20"; +LOCATE COMP "SFP_DIS_19" SITE "AD18"; +LOCATE COMP "SFP_DIS_20" SITE "AC20"; +DEFINE PORT GROUP "tx_dis_group" "SFP_DIS*" ; +IOBUF GROUP "tx_dis_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + +#not supported by transceivers +# LOCATE COMP "TX_FAULT_17" SITE "AF26"; +# LOCATE COMP "TX_FAULT_18" SITE "AE21"; +# LOCATE COMP "TX_FAULT_19" SITE "AD20"; +# LOCATE COMP "TX_FAULT_20" SITE "AB18"; +# DEFINE PORT GROUP "tx_fault_group" "TX_FAULT*" ; +# IOBUF GROUP "tx_fault_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + +######################################### +# Onewire Monitor +######################################### +LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "AG16"; #former ADO_TTL(46) +IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVTTL33 PULLMODE=UP ; + +######################################### +# Test Connectors +######################################### +LOCATE COMP "TEST_2_0" SITE "A16"; +LOCATE COMP "TEST_2_1" SITE "B16"; +LOCATE COMP "TEST_2_2" SITE "G17"; +LOCATE COMP "TEST_2_3" SITE "G16"; +LOCATE COMP "TEST_2_4" SITE "H16"; +LOCATE COMP "TEST_2_5" SITE "F16"; +LOCATE COMP "TEST_2_6" SITE "J16"; +LOCATE COMP "TEST_2_7" SITE "G15"; +LOCATE COMP "TEST_2_8" SITE "C16"; +LOCATE COMP "TEST_2_9" SITE "D16"; +LOCATE COMP "TEST_2_10" SITE "J15"; +LOCATE COMP "TEST_2_11" SITE "H15"; +LOCATE COMP "TEST_2_12" SITE "A15"; +LOCATE COMP "TEST_2_13" SITE "B15"; +LOCATE COMP "TEST_2_14" SITE "F15"; +LOCATE COMP "TEST_2_15" SITE "E16"; +LOCATE COMP "TEST_2_16" SITE "C14"; +LOCATE COMP "TEST_2_17" SITE "E15"; +LOCATE COMP "TEST_2_18" SITE "G14"; +LOCATE COMP "TEST_2_19" SITE "J14"; +LOCATE COMP "TEST_2_20" SITE "F14"; +LOCATE COMP "TEST_2_21" SITE "H14"; +LOCATE COMP "TEST_2_22" SITE "A14"; +LOCATE COMP "TEST_2_23" SITE "B14"; +LOCATE COMP "TEST_2_24" SITE "D13"; +LOCATE COMP "TEST_2_25" SITE "F13"; +LOCATE COMP "TEST_2_26" SITE "G13"; +LOCATE COMP "TEST_2_27" SITE "J11"; +LOCATE COMP "TEST_2_28" SITE "D4"; +LOCATE COMP "TEST_2_29" SITE "D5"; +LOCATE COMP "TEST_2_30" SITE "E5"; +LOCATE COMP "TEST_2_31" SITE "F6"; +DEFINE PORT GROUP "test2_group" "TEST_2*" ; +IOBUF GROUP "test2_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +###################################################################################################### + +######################################### +# Connection to TRB +######################################### +# LOCATE COMP "ADO_LV_0" SITE "E29"; +# LOCATE COMP "ADO_LV_1" SITE "E30"; +# LOCATE COMP "ADO_LV_2" SITE "H25"; +# LOCATE COMP "ADO_LV_3" SITE "G24"; +# LOCATE COMP "ADO_LV_4" SITE "H26"; +# LOCATE COMP "ADO_LV_5" SITE "J26"; +# LOCATE COMP "ADO_LV_6" SITE "K22"; +# LOCATE COMP "ADO_LV_7" SITE "K23"; +# LOCATE COMP "ADO_LV_8" SITE "L23"; +# LOCATE COMP "ADO_LV_9" SITE "L24"; +# LOCATE COMP "ADO_LV_10" SITE "L27"; +# LOCATE COMP "ADO_LV_11" SITE "L28"; +# LOCATE COMP "ADO_LV_12" SITE "M26"; +# LOCATE COMP "ADO_LV_13" SITE "M25"; +# LOCATE COMP "ADO_LV_14" SITE "N23"; +# LOCATE COMP "ADO_LV_15" SITE "N24"; +# LOCATE COMP "ADO_LV_16" SITE "P26"; +# LOCATE COMP "ADO_LV_17" SITE "P25"; +# LOCATE COMP "ADO_LV_18" SITE "N29"; +# LOCATE COMP "ADO_LV_19" SITE "N30"; +# LOCATE COMP "ADO_LV_20" SITE "R29"; +# LOCATE COMP "ADO_LV_21" SITE "P30"; +# LOCATE COMP "ADO_LV_22" SITE "T28"; +# LOCATE COMP "ADO_LV_23" SITE "T29"; +# LOCATE COMP "ADO_LV_24" SITE "U27"; +# LOCATE COMP "ADO_LV_25" SITE "U28"; +# LOCATE COMP "ADO_LV_26" SITE "W29"; +# LOCATE COMP "ADO_LV_27" SITE "W30"; +# LOCATE COMP "ADO_LV_28" SITE "G25"; +# LOCATE COMP "ADO_LV_29" SITE "F26"; +# LOCATE COMP "ADO_LV_30" SITE "H24"; +# LOCATE COMP "ADO_LV_31" SITE "H23"; +# LOCATE COMP "ADO_LV_32" SITE "J28"; +# LOCATE COMP "ADO_LV_33" SITE "H28"; +# LOCATE COMP "ADO_LV_34" SITE "K25"; +# LOCATE COMP "ADO_LV_35" SITE "K24"; +# LOCATE COMP "ADO_LV_36" SITE "M22"; +# LOCATE COMP "ADO_LV_37" SITE "L22"; +# LOCATE COMP "ADO_LV_38" SITE "M28"; +# LOCATE COMP "ADO_LV_39" SITE "M27"; +# LOCATE COMP "ADO_LV_40" SITE "P22"; +# LOCATE COMP "ADO_LV_41" SITE "N22"; +# LOCATE COMP "ADO_LV_42" SITE "P24"; +# LOCATE COMP "ADO_LV_43" SITE "P23"; +# LOCATE COMP "ADO_LV_44" SITE "P28"; +# LOCATE COMP "ADO_LV_45" SITE "P29"; +# LOCATE COMP "ADO_LV_46" SITE "R30"; +# LOCATE COMP "ADO_LV_47" SITE "T30"; +# LOCATE COMP "ADO_LV_48" SITE "U26"; +# LOCATE COMP "ADO_LV_49" SITE "V26"; +# LOCATE COMP "ADO_LV_50" SITE "W28"; +# LOCATE COMP "ADO_LV_51" SITE "W27"; +# LOCATE COMP "ADO_LV_52" SITE "V29"; +# LOCATE COMP "ADO_LV_53" SITE "U29"; +# LOCATE COMP "ADO_LV_54" SITE "V22"; +# LOCATE COMP "ADO_LV_55" SITE "W22"; +# LOCATE COMP "ADO_LV_56" SITE "Y28"; +# LOCATE COMP "ADO_LV_57" SITE "AA29"; +# LOCATE COMP "ADO_LV_58" SITE "AB27"; +# LOCATE COMP "ADO_LV_59" SITE "AB26"; +# LOCATE COMP "ADO_LV_60" SITE "AB28"; +# LOCATE COMP "ADO_LV_61" SITE "AB29"; +# DEFINE PORT GROUP "ado_lv_group" "ADO_LV*" ; +# IOBUF GROUP "ado_lv_group" IO_TYPE=LVDS25 PULLMODE=NONE ; + +# LOCATE COMP "ADO_TTL_0" SITE "AF10"; +# LOCATE COMP "ADO_TTL_1" SITE "AE8"; +# LOCATE COMP "ADO_TTL_2" SITE "AE11"; +# LOCATE COMP "ADO_TTL_3" SITE "AD9"; +# LOCATE COMP "ADO_TTL_4" SITE "AE10"; +# LOCATE COMP "ADO_TTL_5" SITE "AD10"; +# LOCATE COMP "ADO_TTL_6" SITE "AE13"; +# LOCATE COMP "ADO_TTL_7" SITE "AC12"; +# LOCATE COMP "ADO_TTL_8" SITE "AG2"; +# LOCATE COMP "ADO_TTL_9" SITE "AG3"; +# LOCATE COMP "ADO_TTL_10" SITE "AD13"; +# LOCATE COMP "ADO_TTL_11" SITE "AC13"; +# LOCATE COMP "ADO_TTL_12" SITE "AE14"; +# LOCATE COMP "ADO_TTL_13" SITE "AC14"; +# LOCATE COMP "ADO_TTL_14" SITE "AF3"; +# LOCATE COMP "ADO_TTL_15" SITE "AF4"; +# LOCATE COMP "ADO_TTL_16" SITE "AG4"; +# LOCATE COMP "ADO_TTL_17" SITE "AG5"; +# LOCATE COMP "ADO_TTL_18" SITE "AD11"; +# LOCATE COMP "ADO_TTL_19" SITE "AF13"; +# LOCATE COMP "ADO_TTL_20" SITE "AF12"; +# LOCATE COMP "ADO_TTL_21" SITE "AD14"; +# LOCATE COMP "ADO_TTL_22" SITE "AG8"; +# LOCATE COMP "ADO_TTL_23" SITE "AF8"; +# LOCATE COMP "ADO_TTL_24" SITE "AE15"; +# LOCATE COMP "ADO_TTL_25" SITE "AC15"; +# LOCATE COMP "ADO_TTL_26" SITE "AD15"; +# LOCATE COMP "ADO_TTL_27" SITE "AF15"; +# LOCATE COMP "ADO_TTL_28" SITE "AG10"; +# LOCATE COMP "ADO_TTL_29" SITE "AG9"; +# LOCATE COMP "ADO_TTL_30" SITE "AH14"; +# LOCATE COMP "ADO_TTL_31" SITE "AG12"; +# LOCATE COMP "ADO_TTL_32" SITE "AG15"; +# LOCATE COMP "ADO_TTL_33" SITE "AG13"; +# LOCATE COMP "ADO_TTL_34" SITE "AF16"; +# LOCATE COMP "ADO_TTL_35" SITE "AH15"; +# LOCATE COMP "ADO_TTL_36" SITE "AC16"; +# LOCATE COMP "ADO_TTL_37" SITE "AE16"; +# LOCATE COMP "ADO_TTL_38" SITE "AG11"; +# LOCATE COMP "ADO_TTL_39" SITE "AF11"; +# LOCATE COMP "ADO_TTL_40" SITE "AJ14"; +# LOCATE COMP "ADO_TTL_41" SITE "AK14"; +# LOCATE COMP "ADO_TTL_42" SITE "AK15"; +# LOCATE COMP "ADO_TTL_43" SITE "AK16"; +# LOCATE COMP "ADO_TTL_44" SITE "AF18"; +# LOCATE COMP "ADO_TTL_45" SITE "AJ15"; +# LOCATE COMP "ADO_TTL_46" SITE "AG16"; #occupied by 1-wire monitor +# DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ; + +#only used in ttl mode +# LOCATE COMP "F1_TO_F2B_0" SITE "AD1"; +# LOCATE COMP "F1_TO_F2B_1" SITE "AD3"; +# LOCATE COMP "F1_TO_F2B_2" SITE "AC3"; +# LOCATE COMP "F1_TO_F2B_3" SITE "AA6"; +# LOCATE COMP "F1_TO_F2B_4" SITE "AA9"; +# LOCATE COMP "F1_TO_F2B_5" SITE "AB1"; +# LOCATE COMP "F1_TO_F2B_6" SITE "AA7"; +# LOCATE COMP "F1_TO_F2B_7" SITE "Y6"; +# LOCATE COMP "F1_TO_F2B_8" SITE "Y4"; +# LOCATE COMP "F1_TO_F2B_9" SITE "W6"; +# LOCATE COMP "F1_TO_F2B_10" SITE "V6"; +# LOCATE COMP "F1_TO_F2B_11" SITE "V7"; +# LOCATE COMP "F1_TO_F2B_12" SITE "U6"; +# LOCATE COMP "F1_TO_F2B_13" SITE "U8"; +# LOCATE COMP "F1_TO_F2B_14" SITE "T8"; +# LOCATE COMP "F1_TO_F2B_15" SITE "T1"; +# LOCATE COMP "F1_TO_F2B_16" SITE "T9"; +# LOCATE COMP "F1_TO_F2B_17" SITE "R4"; +# LOCATE COMP "F1_TO_F2B_18" SITE "P8"; +# LOCATE COMP "F1_TO_F2B_19" SITE "P7"; +# LOCATE COMP "F1_TO_F2B_20" SITE "P4"; +# LOCATE COMP "F1_TO_F2B_21" SITE "N6"; +# LOCATE COMP "F1_TO_F2B_22" SITE "N7"; +# LOCATE COMP "F1_TO_F2B_23" SITE "M9"; +# LOCATE COMP "F1_TO_F2B_24" SITE "L6"; +# LOCATE COMP "F1_TO_F2B_25" SITE "L7"; +# LOCATE COMP "F1_TO_F2B_26" SITE "K8"; +# LOCATE COMP "F1_TO_F2B_27" SITE "J4"; +# LOCATE COMP "F1_TO_F2B_28" SITE "J1"; +# LOCATE COMP "F1_TO_F2B_29" SITE "G3"; +# LOCATE COMP "F1_TO_F2B_30" SITE "E4"; +# LOCATE COMP "F1_TO_F2B_31" SITE "D1"; +# LOCATE COMP "F2_TO_F1B_0" SITE "AC2"; +# LOCATE COMP "F2_TO_F1B_1" SITE "AC6"; +# LOCATE COMP "F2_TO_F1B_2" SITE "AB3"; +# LOCATE COMP "F2_TO_F1B_3" SITE "AB5"; +# LOCATE COMP "F2_TO_F1B_4" SITE "AA2"; +# LOCATE COMP "F2_TO_F1B_5" SITE "Y2"; +# LOCATE COMP "F2_TO_F1B_6" SITE "Y8"; +# LOCATE COMP "F2_TO_F1B_7" SITE "W4"; +# LOCATE COMP "F2_TO_F1B_8" SITE "W1"; +# LOCATE COMP "F2_TO_F1B_9" SITE "V2"; +# LOCATE COMP "F2_TO_F1B_10" SITE "U2"; +# LOCATE COMP "F2_TO_F1B_11" SITE "U4"; +# LOCATE COMP "F2_TO_F1B_12" SITE "T2"; +# LOCATE COMP "F2_TO_F1B_13" SITE "T4"; +# LOCATE COMP "F2_TO_F1B_14" SITE "R2"; +# LOCATE COMP "F2_TO_F1B_15" SITE "P2"; +# LOCATE COMP "F2_TO_F1B_16" SITE "N2"; +# LOCATE COMP "F2_TO_F1B_17" SITE "M3"; +# LOCATE COMP "F2_TO_F1B_18" SITE "M5"; +# LOCATE COMP "F2_TO_F1B_19" SITE "M2"; +# LOCATE COMP "F2_TO_F1B_20" SITE "L2"; +# LOCATE COMP "F2_TO_F1B_21" SITE "L4"; +# LOCATE COMP "F2_TO_F1B_22" SITE "K1"; +# LOCATE COMP "F2_TO_F1B_23" SITE "K5"; +# LOCATE COMP "F2_TO_F1B_24" SITE "J2"; +# LOCATE COMP "F2_TO_F1B_25" SITE "H2"; +# LOCATE COMP "F2_TO_F1B_26" SITE "H7"; +# LOCATE COMP "F2_TO_F1B_27" SITE "H4"; +# LOCATE COMP "F2_TO_F1B_28" SITE "G1"; +# LOCATE COMP "F2_TO_F1B_29" SITE "G4"; +# LOCATE COMP "F2_TO_F1B_30" SITE "F5"; +# LOCATE COMP "F2_TO_F1B_31" SITE "F2"; + +######################################### +# Connection to ETRAX +######################################### +# LOCATE COMP "FS_PE_1" SITE "AF2"; +# LOCATE COMP "FS_PE_2" SITE "AE2"; +# LOCATE COMP "FS_PE_5" SITE "F7"; +# LOCATE COMP "FS_PE_6" SITE "D8"; +# LOCATE COMP "FS_PE_7" SITE "J13"; +# LOCATE COMP "FS_PE_8" SITE "G11"; +# LOCATE COMP "FS_PE_9" SITE "H13"; +# LOCATE COMP "FS_PE_10" SITE "H12"; +# LOCATE COMP "FS_PE_11" SITE "E8"; +# LOCATE COMP "FS_PE_12" SITE "D9"; +# LOCATE COMP "FS_PE_13" SITE "D12"; +# LOCATE COMP "FS_PE_14" SITE "E13"; +# LOCATE COMP "FS_PE_15" SITE "J12"; +# LOCATE COMP "FS_PE_16" SITE "H10"; +# DEFINE PORT GROUP "fs_pe_group" "FS_PE*" ; +# IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; diff --git a/hub2_fpga2.p2t b/hub2_fpga2.p2t new file mode 100644 index 0000000..f8d5f8f --- /dev/null +++ b/hub2_fpga2.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 7 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: + diff --git a/hub2_fpga2.prj b/hub2_fpga2.prj new file mode 100644 index 0000000..30258f5 --- /dev/null +++ b/hub2_fpga2.prj @@ -0,0 +1 @@ +#-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file i:/vhdl_pro/newhub3/hub2\work.hub2_fpga2.prj #-- Written on Wed Mar 03 12:12:16 2010 #device options set_option -technology LATTICE-ecp2m set_option -part LFE2M100E set_option -speed_grade -5 #compilation/mapping options set_option -default_enum_encoding default set_option -symbolic_fsm_compiler true set_option -resource_sharing true #use verilog 2001 standard option set_option -vlog_std v2001 #map options set_option -frequency 200 set_option -fanout_limit 100 set_option -auto_constrain_io true set_option -disable_io_insertion false set_option -retiming false set_option -pipe false set_option -force_gsr false set_option -compiler_compatible true set_option -dup false #simulation options set_option -write_verilog true set_option -write_vhdl true #timing analysis options set_option -num_critical_paths 3 set_option -num_startend_points 0 #automatic place and route (vendor) options set_option -write_apr_constraint 0 #synplifyPro options. set_option -fixgatedclocks 3 #synplifyPro options. set_option -fixgeneratedclocks 3 #-- add_file options # ECP2M library -- really needed? #add_file -vhdl -lib work "/usr/local/opt/synplify/8/isptools/cae_library/synthesis/vhdl/ecp2m.vhd" #add_file -vhdl -lib work "/opt/lattice/ispLEVER8.0/isptools/cae_library/synthesis/vhdl/ecp2m.vhd" # GbE specific files add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net_gbe_components.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/mb_mac_sim.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_ipu2gbe.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ip_configurator.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_buf.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_setup.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/slv_mac_memory.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/slv_register.vhd" # IPexpress files add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/ip_mem.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/mac_init_mem.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_4096x9.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_2048x8.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_16kx8.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_64kx8.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd" #add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_1024x18.vhd" #add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/debug_fifo_2kx16.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd" add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_64kx9.vhd" # TRBnet files add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" add_file -vhdl -lib work "../trbnet/basics/rom_16x16.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_api_ipu_streaming.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "../trbnet/basics/wide_adder_17x16.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_hub_streaming_port.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_med_16_IC.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/pll_in200_out100.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" # real "local" files add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "hub2_fpga2.vhd" # implementation: "workdir" impl -add workdir -type fpga # device options set_option -technology LATTICE-ECP2M set_option -part LFE2M100E set_option -package F900C set_option -speed_grade -5 # compilation/mapping options set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 set_option -top_module hub2_fpga2 # map options set_option -frequency 100 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -retiming 0 set_option -pipe 0 # set_option -force_gsr auto set_option -force_gsr false set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 # simulation options set_option -write_verilog 0 set_option -write_vhdl 1 # automatic place and route (vendor) options set_option -write_apr_constraint 0 # set result format/file last project -result_format "edif" project -result_file "workdir/hub2_fpga2.edf" #-- error message log file project -log_file "workdir/hub2_fpga2.srr" #implementation attributes set_option -vlog_std v2001 set_option -project_relative_includes 1 impl -active "workdir" #-- run Synplify with 'arrange VHDL file' project -run hdl_info_gen -fileorder project -run \ No newline at end of file diff --git a/hub2_fpga2.vhd b/hub2_fpga2.vhd new file mode 100644 index 0000000..3dfc108 --- /dev/null +++ b/hub2_fpga2.vhd @@ -0,0 +1,960 @@ +--Port 19&20 is uplink, Port 18 is downlinks, 17 is reserved for Ethernet + +--the hub logic reports +--sfp 18 = port 0 Slowcontrol +--sfp 19 = port 1 Slowcontrol 2 +--lvds = port 2 to FPGA1 +--sfp 20 = port 3 CTS + +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; + + +entity hub2_fpga2 is +generic( USE_ETHERNET : integer range c_NO to c_YES := c_YES; + USE_200_MHZ : integer range c_NO to c_YES := c_YES + ); +port( +-- CLK_F2_TO_F1 : out std_logic; -- unused + CLK_F1_TO_F2 : in std_logic; +-- ADDON_RESET : in std_logic; -- unused +-- RESET_N : in std_logic; -- unused +-- SUPPL_RESET_N : in std_logic; -- unused + --Connection to TRB +-- ADO_LV : inout std_logic_vector(61 downto 0); +-- ADO_TTL : inout std_logic_vector(45 downto 0); + --Connection to FPGA1 + F1_TO_F2 : in std_logic_vector(31 downto 0); + F2_TO_F1 : out std_logic_vector(31 downto 0); + --Optical Links + SFP_TXP : out std_logic_vector(20 downto 17); + SFP_TXN : out std_logic_vector(20 downto 17); + SFP_RXP : in std_logic_vector(20 downto 17); + SFP_RXN : in std_logic_vector(20 downto 17); + SFP_REFCLKP : in std_logic_vector(20 downto 17); + SFP_REFCLKN : in std_logic_vector(20 downto 17); + SFP_LED_GREEN : out std_logic_vector(20 downto 17); + SFP_LED_ORANGE : out std_logic_vector(20 downto 17); + SFP_MOD0 : in std_logic_vector(20 downto 17); + SFP_LOS : in std_logic_vector(20 downto 17); + SFP_DIS : out std_logic_vector(20 downto 17); + --Other + ONEWIRE_MONITOR_IN : in std_logic; + --Debugging + TEST_2 : out std_logic_vector(31 downto 0) +); + +attribute syn_useioff : boolean; +attribute syn_useioff of F1_TO_F2 : signal is true; +attribute syn_useioff of F2_TO_F1 : signal is true; + +attribute syn_useioff of SFP_LED_GREEN : signal is false; +attribute syn_useioff of SFP_LED_ORANGE : signal is false; + +end entity; + +architecture hub2_fpga2_arch of hub2_fpga2 is + +component slv_register is +generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component; + +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +constant mii : integer := 4; + +-- Clocks and reset +signal clk_in : std_logic; -- clock from SerDes reference output (100MHz or 200MHz) +signal clk_100 : std_logic; -- 100MHz system clock +signal clk_en : std_logic; +signal reset_i_q : std_logic; -- fast async reset for SerDes +signal pll_locked : std_logic; +signal reset_counter : std_logic_vector(11 downto 0); +signal next_reset : std_logic; +signal reset_i : std_logic; +signal make_reset_via_network_q : std_logic; +signal make_reset_via_network : std_logic; +signal gsr_n : std_logic; + +signal test_clk : std_logic; -- MUST BE ZERO!!! + +signal buf_SFP_LOS : std_logic_vector(20 downto 17); +signal buf_SFP_MOD0 : std_logic_vector(20 downto 17); + +signal med_data_in : std_logic_vector(4*16-1 downto 0); +signal med_data_out : std_logic_vector(4*16-1 downto 0); +signal med_packet_num_in : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_packet_num_out : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_dataready_in : std_logic_vector(3 downto 0); +signal med_dataready_out : std_logic_vector(3 downto 0); +signal med_read_in : std_logic_vector(3 downto 0); +signal med_read_out : std_logic_vector(3 downto 0); + +signal med_stat_op : std_logic_vector(4*16-1 downto 0); +signal med_ctrl_op : std_logic_vector(4*16-1 downto 0); +signal med_stat_debug : std_logic_vector(4*64-1 downto 0); +signal med_ctrl_debug : std_logic_vector(4*64-1 downto 0); + +signal buf_SFP_LED_ORANGE : std_logic_vector(20 downto 17); +signal buf_SFP_LED_GREEN : std_logic_vector(20 downto 17); + +signal cts_number : std_logic_vector(15 downto 0); +signal cts_code : std_logic_vector(7 downto 0); +signal cts_information : std_logic_vector(7 downto 0); +signal cts_start_readout : std_logic; +signal cts_readout_type : std_logic_vector(3 downto 0); +signal cts_data : std_logic_vector(31 downto 0); +signal cts_dataready : std_logic; +signal cts_readout_finished : std_logic; +signal cts_read : std_logic; +signal cts_length : std_logic_vector(15 downto 0); +signal cts_status_bits : std_logic_vector(31 downto 0); +signal fee_data : std_logic_vector(15 downto 0); +signal fee_dataready : std_logic; +signal fee_read : std_logic; +signal fee_status_bits : std_logic_vector(31 downto 0); +signal fee_busy : std_logic; +signal my_address : std_logic_vector(15 downto 0); + +signal stage_stat_regs : std_logic_vector (31 downto 0); +signal stage_ctrl_regs : std_logic_vector (31 downto 0); + +--REGIO INTERFACE +signal regio_addr_out : std_logic_vector(16-1 downto 0); +signal regio_read_enable_out : std_logic; +signal regio_write_enable_out : std_logic; +signal regio_data_out : std_logic_vector(32-1 downto 0); +signal regio_data_in : std_logic_vector(32-1 downto 0) := (others => '0'); +signal regio_dataready_in : std_logic := '0'; +signal regio_no_more_data_in : std_logic := '0'; +signal regio_write_ack_in : std_logic := '0'; +signal regio_unknown_addr_in : std_logic := '0'; +signal regio_timeout_out : std_logic; + +signal mb_ctrl_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_read : std_logic; +signal mb_ctrl_reg_write : std_logic; +signal mb_ctrl_reg_ack : std_logic; + +signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_stat_reg_read : std_logic; +signal mb_stat_reg_write : std_logic; +signal mb_stat_reg_ack : std_logic; + +signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used +signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); +signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); +signal mb_ip_mem_read : std_logic; +signal mb_ip_mem_write : std_logic; +signal mb_ip_mem_ack : std_logic; + +signal ip_cfg_mem_clk : std_logic; +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); + +signal buf_test : std_logic_vector(31 downto 0); + +signal analyzer_debug : std_logic_vector(63 downto 0); + +-- gk 22.04.10 +signal ctrl_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_data : std_logic_vector(31 downto 0); +signal gbe_stp_reg_ack : std_logic; +signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); +signal gbe_stp_reg_read : std_logic; +signal gbe_stp_reg_write : std_logic; +signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); + + +begin + +--------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------- +gen_no_pll : if USE_200_MHZ = c_NO generate +THE_PLL : pll_in100_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +gen_pll : if USE_200_MHZ = c_YES generate +THE_PLL : pll_in200_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +clk_en <= '1'; +test_clk <= '0'; + +--------------------------------------------------------------------- +-- Reset process +--------------------------------------------------------------------- +THE_RESET_COUNTER_PROC: process( pll_locked, clk_100 ) +begin + if( pll_locked = '0' ) then + -- asynchronous reset by PLL lock signal only + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( rising_edge(clk_100) ) then + if ( make_reset_via_network_q = '1' ) then + -- synchronous reset by network + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( reset_counter = x"EEE" ) then + reset_counter <= x"EEE"; + next_reset <= '0'; + else + reset_counter <= reset_counter + 1; + next_reset <= '1'; + end if; + end if; +end process THE_RESET_COUNTER_PROC; + +-- Fast aysnchronous reset for SerDes +reset_i_q <= not pll_locked; + +gsr_n <= pll_locked; + +-- "normal" synchronous reset signal +reset_i <= next_reset; + +-- reset by TRBnet (port 0,1 and 3 are uplinks) +make_reset_via_network <= MED_STAT_OP(3*16+13) or MED_STAT_OP(0*16+13) or MED_STAT_OP(1*16+13); + +THE_RESET_TRG_SYNC: signal_sync +generic map( + DEPTH => 2, + WIDTH => 1 ) +port map( + RESET => '0', + D_IN(0) => make_reset_via_network, + CLK0 => clk_100, + CLK1 => clk_100, + D_OUT(0) => make_reset_via_network_q +); + +--------------------------------------------------------------------- +-- Serdes +--------------------------------------------------------------------- + +-- Input synchronization +THE_SFP_LOS_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + buf_SFP_LOS <= SFP_LOS; + buf_SFP_MOD0 <= SFP_MOD0; + end if; +end process THE_SFP_LOS_PROC; + +--------------------------------------------------------------------- +-- one normal port (SFP18) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(1*16-1 downto 0*16), + MED_PACKET_NUM_IN => med_packet_num_out(1*3-1 downto 0*3), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(1*16-1 downto 0*16), + MED_PACKET_NUM_OUT => med_packet_num_in(1*3-1 downto 0*3), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(18), + SD_RXD_N_IN => SFP_RXN(18), + SD_TXD_P_OUT => SFP_TXP(18), + SD_TXD_N_OUT => SFP_TXN(18), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(18), + SD_LOS_IN => buf_SFP_LOS(18), + SD_TXDIS_OUT => SFP_DIS(18), + STAT_OP => med_stat_op(1*16-1 downto 0*16), + CTRL_OP => med_ctrl_op(1*16-1 downto 0*16), + STAT_DEBUG => med_stat_debug(1*64-1 downto 0*64), + CTRL_DEBUG => med_ctrl_debug(1*64-1 downto 0*64) +); + +--------------------------------------------------------------------- +-- one normal port (SFP19) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + EXT_CLOCK => c_YES, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(2*16-1 downto 1*16), + MED_PACKET_NUM_IN => med_packet_num_out(2*3-1 downto 1*3), + MED_DATAREADY_IN => med_dataready_out(1), + MED_READ_OUT => med_read_in(1), + MED_DATA_OUT => med_data_in(2*16-1 downto 1*16), + MED_PACKET_NUM_OUT => med_packet_num_in(2*3-1 downto 1*3), + MED_DATAREADY_OUT => med_dataready_in(1), + MED_READ_IN => med_read_out(1), + REFCLK2CORE_OUT => clk_in, + SD_RXD_P_IN => SFP_RXP(19), + SD_RXD_N_IN => SFP_RXN(19), + SD_TXD_P_OUT => SFP_TXP(19), + SD_TXD_N_OUT => SFP_TXN(19), + SD_REFCLK_P_IN => SFP_REFCLKP(19), + SD_REFCLK_N_IN => SFP_REFCLKN(19), + SD_PRSNT_N_IN => buf_SFP_MOD0(19), + SD_LOS_IN => buf_SFP_LOS(19), + SD_TXDIS_OUT => SFP_DIS(19), + STAT_OP => med_stat_op(2*16-1 downto 1*16), + CTRL_OP => med_ctrl_op(2*16-1 downto 1*16), + STAT_DEBUG => med_stat_debug(2*64-1 downto 1*64), + CTRL_DEBUG => med_ctrl_debug(2*64-1 downto 1*64) +); + +--------------------------------------------------------------------- +-- Connection between both FPGAs on HUB2 PCB +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC +port map( + CLK => clk_100, + CLK_EN => clk_en, + RESET => reset_i, + --Internal Connection + MED_DATA_IN => med_data_out(3*16-1 downto 2*16), + MED_PACKET_NUM_IN => med_packet_num_out(3*3-1 downto 2*3), + MED_DATAREADY_IN => med_dataready_out(2), + MED_READ_OUT => med_read_in(2), + MED_DATA_OUT => med_data_in(3*16-1 downto 2*16), + MED_PACKET_NUM_OUT => med_packet_num_in(3*3-1 downto 2*3), + MED_DATAREADY_OUT => med_dataready_in(2), + MED_READ_IN => med_read_out(2), + DATA_OUT => F2_TO_F1(31 downto 16), + DATA_VALID_OUT => F2_TO_F1(15), + DATA_CTRL_OUT => F2_TO_F1(14), + DATA_CLK_OUT => F2_TO_F1(1), + DATA_IN => F1_TO_F2(31 downto 16), + DATA_VALID_IN => F1_TO_F2(15), + DATA_CTRL_IN => F1_TO_F2(14), + DATA_CLK_IN => CLK_F1_TO_F2, + STAT_OP => med_stat_op(3*16-1 downto 2*16), + CTRL_OP => med_ctrl_op(3*16-1 downto 2*16), + STAT_DEBUG => med_stat_debug(3*64-1 downto 2*64) +); +--------------------------------------------------------------------- +-- Uplink port (SFP20) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(4*16-1 downto 3*16), + MED_PACKET_NUM_IN => med_packet_num_out(4*3-1 downto 3*3), + MED_DATAREADY_IN => med_dataready_out(3), + MED_READ_OUT => med_read_in(3), + MED_DATA_OUT => med_data_in(4*16-1 downto 3*16), + MED_PACKET_NUM_OUT => med_packet_num_in(4*3-1 downto 3*3), + MED_DATAREADY_OUT => med_dataready_in(3), + MED_READ_IN => med_read_out(3), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(20), + SD_RXD_N_IN => SFP_RXN(20), + SD_TXD_P_OUT => SFP_TXP(20), + SD_TXD_N_OUT => SFP_TXN(20), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(20), + SD_LOS_IN => buf_SFP_LOS(20), + SD_TXDIS_OUT => SFP_DIS(20), + STAT_OP => med_stat_op(4*16-1 downto 3*16), + CTRL_OP => med_ctrl_op(4*16-1 downto 3*16), + STAT_DEBUG => med_stat_debug(4*64-1 downto 3*64), + CTRL_DEBUG => med_ctrl_debug(4*64-1 downto 3*64) +); + +med_ctrl_debug <= (others => '0'); + +--------------------------------------------------------------------- +-- The Hub +--------------------------------------------------------------------- +gen_normal_hub : if USE_ETHERNET = c_NO generate +THE_HUB: trb_net16_hub_base +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => mii, + MII_IS_UPLINK => (0 => 1, 1 => 1, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (others => 1), + INT_NUMBER => 0, + INT_CHANNELS => (0,1,3,3,3,3,3,3), + INIT_ENDPOINT_ID => x"0002", + USE_ONEWIRE => c_MONITOR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + BROADCAST_SPECIAL_ADDR => x"32" +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => CLK_EN, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + INT_INIT_READ_IN => (others => '0'), + INT_INIT_DATAREADY_IN => (others => '0'), + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_IN => (others => '0'), + INT_REPLY_DATAREADY_IN => (others => '0'), + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + --REGIO INTERFACE + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => buf_test +); + +TEST_2 <= (others => '0'); + +--REGISTER_IT_PROC: process( buf_test(31) ) +--begin +-- if rising_edge( buf_test(31) ) then +-- TEST_2(30 downto 0) <= buf_test(30 downto 0); +-- end if; +--end process REGISTER_IT_PROC; +-- +--TEST_2(31) <= buf_test(31); + +end generate; + +gen_ethernet_hub : if USE_ETHERNET = c_YES generate +THE_HUB: trb_net16_hub_streaming_port +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + INIT_ADDRESS => x"affe", +-- MII_NUMBER => mii, +-- MII_IS_UPLINK => ((mii-1) => 1, others => 0), +-- MII_IS_DOWNLINK => ((mii-1) => 0, others => 1), +-- 4 = SFP17 (GbE) +-- 3 = SFP20 (TRBnet) +-- 2 = LVDS (TRBnet) +-- 1 = SFP19 (TRBnet) +-- 0 = SFP18 (TRBnet) + MII_NUMBER => mii, +-- MII_IS_UPLINK => (0 => 1, 1 => 1, 2 => 0, 3 => 1, others => 1), +-- MII_IS_DOWNLINK => (others => 1), + MII_IS_UPLINK => (0 => 1, 1 => 1, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (0 => 0, 1 => 0, 2 => 1, 3 => 1, others => 1), + MII_IS_UPLINK_ONLY => (0 => 1, 1 => 1, 2 => 0, 3 => 0, others => 0), + USE_ONEWIRE => c_MONITOR, + HARDWARE_VERSION => x"62210000", -- gk 26.05.10 + INIT_ENDPOINT_ID => x"0002", + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + BROADCAST_SPECIAL_ADDR => x"33" +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => clk_en, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + --Event information coming from CTSCTS_READOUT_TYPE_OUT + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => open, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + MY_ADDRESS_OUT => my_address, + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Fixed status and control ports + MPLEX_CTRL => (others => '0'), + STAT_DEBUG => open, --buf_test, + CTRL_DEBUG => (others => '0') +); + +--------------------------------------------------------------------- +-- The GbE machine for blasting out data from TRBnet +--------------------------------------------------------------------- + +GBE: trb_net16_gbe_buf +generic map( + DO_SIMULATION => 0, + USE_125MHZ_EXTCLK => 1 +) +port map( + CLK => clk_100, + TEST_CLK => test_clk, + CLK_125_IN => '0', + RESET => reset_i, + GSR_N => gsr_n, + -- Debug + STAGE_STAT_REGS_OUT => stage_stat_regs, -- should be come STATUS or similar + STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE! + -- gk 22.04.10 not used any more, ip_configurator moved inside + -- configuration interface + IP_CFG_START_IN => stage_ctrl_regs(15), + IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8), + IP_CFG_DONE_OUT => open, + IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr, + IP_CFG_MEM_DATA_IN => ip_cfg_mem_data, + IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk, + MR_RESET_IN => stage_ctrl_regs(3), + MR_MODE_IN => stage_ctrl_regs(1), + MR_RESTART_IN => stage_ctrl_regs(0), + -- gk 29.03.10 + -- interface to ip_configurator memory + SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), + SLV_READ_IN => mb_ip_mem_read, + SLV_WRITE_IN => mb_ip_mem_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ip_mem_ack, + SLV_DATA_IN => mb_ip_mem_data_wr, + SLV_DATA_OUT => mb_ip_mem_data_rd, + -- gk 26.04.10 + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0), + BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs, + BUS_DATA_OUT => gbe_stp_reg_data_rd, + BUS_WRITE_EN_IN => gbe_stp_reg_write, + BUS_READ_EN_IN => gbe_stp_reg_read, + BUS_ACK_OUT => gbe_stp_reg_ack, + -- gk 23.04.10 + LED_PACKET_SENT_OUT => buf_SFP_LED_ORANGE(17), + LED_AN_DONE_N_OUT => buf_SFP_LED_GREEN(17), + -- CTS interface + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + -- Data payload interface + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + --SFP Connection + SFP_RXD_P_IN => SFP_RXP(17), + SFP_RXD_N_IN => SFP_RXN(17), + SFP_TXD_P_OUT => SFP_TXP(17), + SFP_TXD_N_OUT => SFP_TXN(17), + SFP_REFCLK_P_IN => SFP_REFCLKP(17), + SFP_REFCLK_N_IN => SFP_REFCLKN(17), + SFP_PRSNT_N_IN => buf_SFP_MOD0(17), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN => buf_SFP_LOS(17), -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT => SFP_DIS(17), -- SFP disable + ANALYZER_DEBUG_OUT => analyzer_debug --open +); + +--------------------------------------------------------------------- +-- LogicAnalyzer signals +--------------------------------------------------------------------- + +--buf_test(31 downto 0) <= (others => '0'); + +buf_test(15) <= clk_100; + +buf_test(4) <= fee_busy; +buf_test(3) <= fee_read; +buf_test(2) <= fee_dataready; +buf_test(1) <= cts_readout_finished; +buf_test(0) <= cts_start_readout; + +-- output to pads +--TEST_2 <= buf_test; +REGISTER_IT_PROC: process( buf_test(15) ) +begin + if rising_edge( buf_test(15) ) then + TEST_2(31 downto 16) <= buf_test(31 downto 16); + TEST_2(14 downto 0) <= buf_test(14 downto 0); + end if; +end process REGISTER_IT_PROC; + +TEST_2(15) <= buf_test(15); + +end generate; + +--------------------------------------------------------------------- +-- The Bus Handler for all Slow Control Activities +--------------------------------------------------------------------- +-- reserved address space C000 - FFFF +THE_BUS_HANDLER: trb_net16_regio_bus_handler +generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => ( 0 => x"8000", 1 => x"8200", 2 => x"8100", 3=> x"8300", others => x"0000" ), -- gk 22.04.10 + PORT_ADDR_MASK => ( 0 => 0, 1 => 0, 2 => 8, 3 => 8, others => 0) -- gk 22.04.10 +) +port map( + CLK => clk_100, + RESET => reset_i, + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + -- my registers + -- first one - control + BUS_ADDR_OUT(1*16-1 downto 0*16) => ctrl_reg_addr, + BUS_DATA_OUT(1*32-1 downto 0*32) => mb_ctrl_reg_data_wr, + BUS_READ_ENABLE_OUT(0) => mb_ctrl_reg_read, + BUS_WRITE_ENABLE_OUT(0) => mb_ctrl_reg_write, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(1*32-1 downto 0*32) => mb_ctrl_reg_data_rd, + BUS_DATAREADY_IN(0) => mb_ctrl_reg_ack, + BUS_WRITE_ACK_IN(0) => mb_ctrl_reg_ack, + BUS_NO_MORE_DATA_IN(0) => '0', + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- second one - status + BUS_ADDR_OUT(2*16-1 downto 1*16) => open, + BUS_DATA_OUT(2*32-1 downto 1*32) => mb_stat_reg_data_wr, + BUS_READ_ENABLE_OUT(1) => mb_stat_reg_read, + BUS_WRITE_ENABLE_OUT(1) => mb_stat_reg_write, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(2*32-1 downto 1*32) => mb_stat_reg_data_rd, + BUS_DATAREADY_IN(1) => mb_stat_reg_ack, + BUS_WRITE_ACK_IN(1) => mb_stat_reg_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + ---- + STAT_DEBUG => open +); + +--------------------------------------------------------------------- +-- MB CTRL REGISTER +--------------------------------------------------------------------- +MB_CTRL_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_ctrl_reg_read, + SLV_WRITE_IN => mb_ctrl_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ctrl_reg_ack, + SLV_DATA_IN => mb_ctrl_reg_data_wr, + SLV_DATA_OUT => mb_ctrl_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_ctrl_regs, + REG_DATA_OUT => stage_ctrl_regs, + -- Status lines + STAT => open +); + +-- gk 26.04.10 +-- gk 22.04.10 register to manage gbe setup registers +-- GBE_SETUP_REGISTER : slv_register +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_READ_IN => gbe_stp_reg_read, +-- SLV_WRITE_IN => gbe_stp_reg_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => gbe_stp_reg_ack, +-- SLV_DATA_IN => gbe_stp_reg_data_wr, +-- SLV_DATA_OUT => gbe_stp_reg_data_rd, +-- -- I/O to the backend +-- REG_DATA_IN => gbe_stp_data, +-- REG_DATA_OUT => gbe_stp_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- MB STAT REGISTER +--------------------------------------------------------------------- +MB_STAT_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_stat_reg_read, + SLV_WRITE_IN => mb_stat_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_stat_reg_ack, + SLV_DATA_IN => mb_stat_reg_data_wr, + SLV_DATA_OUT => mb_stat_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_stat_regs, + REG_DATA_OUT => open, + -- Status lines + STAT => open +); + +-- gk 29.03.10 component moved to gbe_buf +--------------------------------------------------------------------- +-- MB IP CONFIG MEMORY +--------------------------------------------------------------------- +-- MB_IP_CONFIG: slv_mac_memory +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), +-- SLV_READ_IN => mb_ip_mem_read, +-- SLV_WRITE_IN => mb_ip_mem_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => mb_ip_mem_ack, +-- SLV_DATA_IN => mb_ip_mem_data_wr, +-- SLV_DATA_OUT => mb_ip_mem_data_rd, +-- -- I/O to the backend +-- MEM_CLK_IN => ip_cfg_mem_clk, +-- MEM_ADDR_IN => ip_cfg_mem_addr, +-- MEM_DATA_OUT => ip_cfg_mem_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- Funny LEDs ;-) +--------------------------------------------------------------------- +buf_SFP_LED_ORANGE(18) <= not (med_stat_op(10) or med_stat_op(11)); +buf_SFP_LED_GREEN(18) <= not med_stat_op(9); + +buf_SFP_LED_ORANGE(19) <= not (med_stat_op(10+16) or med_stat_op(11+16)); +buf_SFP_LED_GREEN(19) <= not med_stat_op(9+16); + +buf_SFP_LED_ORANGE(20) <= not (med_stat_op(10+48) or med_stat_op(11+48)); +buf_SFP_LED_GREEN(20) <= not med_stat_op(9+48); + +-- gk 24.04.10 +--buf_SFP_LED_ORANGE(17) <= '0'; +--buf_SFP_LED_GREEN(17) <= '1'; + + +THE_LED_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + SFP_LED_GREEN <= buf_SFP_LED_GREEN; + SFP_LED_ORANGE <= buf_SFP_LED_ORANGE; + end if; +end process THE_LED_PROC; + +--------------------------------------------------------------------- +--Debugging +--------------------------------------------------------------------- + + +end architecture; \ No newline at end of file diff --git a/hub2_fpga2.vhd.old b/hub2_fpga2.vhd.old new file mode 100644 index 0000000..c406cc9 --- /dev/null +++ b/hub2_fpga2.vhd.old @@ -0,0 +1,2117 @@ +<<<<<<< hub2_fpga2.vhd +--Port 19&20 is uplink, Port 18 is downlinks, 17 is reserved for Ethernet + +--the hub logic reports +--sfp 18 = port 0 +--sfp 19 = port 1 Slowcontrol +--lvds = port 2 to FPGA1 +--sfp 20 = port 3 CTS + +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; + + +entity hub2_fpga2 is +generic( USE_ETHERNET : integer range c_NO to c_YES := c_YES; + USE_200_MHZ : integer range c_NO to c_YES := c_YES + ); +port( +-- CLK_F2_TO_F1 : out std_logic; -- unused + CLK_F1_TO_F2 : in std_logic; +-- ADDON_RESET : in std_logic; -- unused +-- RESET_N : in std_logic; -- unused +-- SUPPL_RESET_N : in std_logic; -- unused + --Connection to TRB +-- ADO_LV : inout std_logic_vector(61 downto 0); +-- ADO_TTL : inout std_logic_vector(45 downto 0); + --Connection to FPGA1 + F1_TO_F2 : in std_logic_vector(31 downto 0); + F2_TO_F1 : out std_logic_vector(31 downto 0); + --Optical Links + SFP_TXP : out std_logic_vector(20 downto 17); + SFP_TXN : out std_logic_vector(20 downto 17); + SFP_RXP : in std_logic_vector(20 downto 17); + SFP_RXN : in std_logic_vector(20 downto 17); + SFP_REFCLKP : in std_logic_vector(20 downto 17); + SFP_REFCLKN : in std_logic_vector(20 downto 17); + SFP_LED_GREEN : out std_logic_vector(20 downto 17); + SFP_LED_ORANGE : out std_logic_vector(20 downto 17); + SFP_MOD0 : in std_logic_vector(20 downto 17); + SFP_LOS : in std_logic_vector(20 downto 17); + SFP_DIS : out std_logic_vector(20 downto 17); + --Other + ONEWIRE_MONITOR_IN : in std_logic; + --Debugging + TEST_2 : out std_logic_vector(31 downto 0) +); + +attribute syn_useioff : boolean; +attribute syn_useioff of F1_TO_F2 : signal is true; +attribute syn_useioff of F2_TO_F1 : signal is true; + +attribute syn_useioff of SFP_LED_GREEN : signal is false; +attribute syn_useioff of SFP_LED_ORANGE : signal is false; + +end entity; + +architecture hub2_fpga2_arch of hub2_fpga2 is + +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 0; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_TX_IN : in std_logic; -- gk 28.04.01 + CLK_125_RX_IN : in std_logic; -- gk 28.04.01 + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 26.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + BUS_WRITE_EN_IN : in std_logic; + BUS_READ_EN_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- PacketConstructor interface + IG_CTS_CTR_TST : out std_logic_vector(2 downto 0); + IG_REM_CTR_TST : out std_logic_vector(3 downto 0); + IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + IG_DATA_TST : out std_logic_vector(15 downto 0); + IG_WCNT_TST : out std_logic_vector(15 downto 0); + IG_RCNT_TST : out std_logic_vector(16 downto 0); + IG_RD_EN_TST : out std_logic; + IG_WR_EN_TST : out std_logic; + IG_EMPTY_TST : out std_logic; + IG_AEMPTY_TST : out std_logic; + IG_FULL_TST : out std_logic; + IG_AFULL_TST : out std_logic; + PC_WR_EN_TST : out std_logic; + PC_DATA_TST : out std_logic_vector (7 downto 0); + PC_READY_TST : out std_logic; + PC_START_OF_SUB_TST : out std_logic; + PC_END_OF_DATA_TST : out std_logic; + PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0); + PC_TRIG_NR_TST : out std_logic_vector(31 downto 0); + PC_PADDING_TST : out std_logic; + PC_DECODING_TST : out std_logic_vector(31 downto 0); + PC_EVENT_ID_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0); + PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0); + PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + PC_SHF_EMPTY_TST : out std_logic; + PC_SHF_FULL_TST : out std_logic; + PC_DF_EMPTY_TST : out std_logic; + PC_DF_FULL_TST : out std_logic; + PC_ALL_CTR_TST : out std_logic_vector(4 downto 0); + PC_SUB_CTR_TST : out std_logic_vector(4 downto 0); + PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0); + PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0); + PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameConstructor interface + FC_WR_EN_TST : out std_logic; + FC_DATA_TST : out std_logic_vector(7 downto 0); + FC_H_READY_TST : out std_logic; + FC_READY_TST : out std_logic; + FC_IP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_IDENT_TST : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0); + FC_SOD_TST : out std_logic; + FC_EOD_TST : out std_logic; + FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0); + FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameTransmitter interface + FT_DATA_TST : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_TST : out std_logic; + FT_START_OF_PACKET_TST : out std_logic; + FT_BSM_INIT_TST : out std_logic_vector(3 downto 0); + FT_BSM_MAC_TST : out std_logic_vector(3 downto 0); + FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- MAC interface + MAC_HADDR_TST : out std_logic_vector(7 downto 0); + MAC_HDATA_TST : out std_logic_vector(7 downto 0); + MAC_HCS_TST : out std_logic; + MAC_HWRITE_TST : out std_logic; + MAC_HREAD_TST : out std_logic; + MAC_HREADY_TST : out std_logic; + MAC_HDATA_EN_TST : out std_logic; + MAC_FIFOAVAIL_TST : out std_logic; + MAC_FIFOEOF_TST : out std_logic; + MAC_FIFOEMPTY_TST : out std_logic; + MAC_TX_READ_TST : out std_logic; + MAC_TX_DONE_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- pcs and serdes + PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0); + PCS_AN_COMPLETE_TST : out std_logic; + PCS_AN_PAGE_RX_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +component slv_register is +generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component; + +component slv_mac_memory is +port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component; + +constant mii : integer := 4; + +-- Clocks and reset +signal clk_in : std_logic; -- clock from SerDes reference output (100MHz or 200MHz) +signal clk_100 : std_logic; -- 100MHz system clock +signal clk_en : std_logic; +signal reset_i_q : std_logic; -- fast async reset for SerDes +signal pll_locked : std_logic; +signal reset_counter : std_logic_vector(11 downto 0); +signal next_reset : std_logic; +signal reset_i : std_logic; +signal make_reset_via_network_q : std_logic; +signal make_reset_via_network : std_logic; +signal gsr_n : std_logic; + +signal test_clk : std_logic; -- MUST BE ZERO!!! + +signal buf_SFP_LOS : std_logic_vector(20 downto 17); +signal buf_SFP_MOD0 : std_logic_vector(20 downto 17); + +signal med_data_in : std_logic_vector(4*16-1 downto 0); +signal med_data_out : std_logic_vector(4*16-1 downto 0); +signal med_packet_num_in : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_packet_num_out : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_dataready_in : std_logic_vector(3 downto 0); +signal med_dataready_out : std_logic_vector(3 downto 0); +signal med_read_in : std_logic_vector(3 downto 0); +signal med_read_out : std_logic_vector(3 downto 0); + +signal med_stat_op : std_logic_vector(4*16-1 downto 0); +signal med_ctrl_op : std_logic_vector(4*16-1 downto 0); +signal med_stat_debug : std_logic_vector(4*64-1 downto 0); +signal med_ctrl_debug : std_logic_vector(4*64-1 downto 0); + +signal buf_SFP_LED_ORANGE : std_logic_vector(20 downto 17); +signal buf_SFP_LED_GREEN : std_logic_vector(20 downto 17); + +signal cts_number : std_logic_vector(15 downto 0); +signal cts_code : std_logic_vector(7 downto 0); +signal cts_information : std_logic_vector(7 downto 0); +signal cts_start_readout : std_logic; +signal cts_readout_type : std_logic_vector(3 downto 0); +signal cts_data : std_logic_vector(31 downto 0); +signal cts_dataready : std_logic; +signal cts_readout_finished : std_logic; +signal cts_read : std_logic; +signal cts_length : std_logic_vector(15 downto 0); +signal cts_status_bits : std_logic_vector(31 downto 0); +signal fee_data : std_logic_vector(15 downto 0); +signal fee_dataready : std_logic; +signal fee_read : std_logic; +signal fee_status_bits : std_logic_vector(31 downto 0); +signal fee_busy : std_logic; +signal my_address : std_logic_vector(15 downto 0); + +signal stage_stat_regs : std_logic_vector (31 downto 0); +signal stage_ctrl_regs : std_logic_vector (31 downto 0); + +--REGIO INTERFACE +signal regio_addr_out : std_logic_vector(16-1 downto 0); +signal regio_read_enable_out : std_logic; +signal regio_write_enable_out : std_logic; +signal regio_data_out : std_logic_vector(32-1 downto 0); +signal regio_data_in : std_logic_vector(32-1 downto 0) := (others => '0'); +signal regio_dataready_in : std_logic := '0'; +signal regio_no_more_data_in : std_logic := '0'; +signal regio_write_ack_in : std_logic := '0'; +signal regio_unknown_addr_in : std_logic := '0'; +signal regio_timeout_out : std_logic; + +signal mb_ctrl_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_read : std_logic; +signal mb_ctrl_reg_write : std_logic; +signal mb_ctrl_reg_ack : std_logic; + +signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_stat_reg_read : std_logic; +signal mb_stat_reg_write : std_logic; +signal mb_stat_reg_ack : std_logic; + +signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used +signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); +signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); +signal mb_ip_mem_read : std_logic; +signal mb_ip_mem_write : std_logic; +signal mb_ip_mem_ack : std_logic; + +signal ip_cfg_mem_clk : std_logic; +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); + +signal buf_test : std_logic_vector(31 downto 0); + +signal analyzer_debug : std_logic_vector(63 downto 0); + +-- gk 22.04.10 +signal ctrl_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_data : std_logic_vector(31 downto 0); +signal gbe_stp_reg_ack : std_logic; +signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); +signal gbe_stp_reg_read : std_logic; +signal gbe_stp_reg_write : std_logic; +signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); + +begin + +--------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------- +gen_no_pll : if USE_200_MHZ = c_NO generate +THE_PLL : pll_in100_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +gen_pll : if USE_200_MHZ = c_YES generate +THE_PLL : pll_in200_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +clk_en <= '1'; +test_clk <= '0'; + +--------------------------------------------------------------------- +-- Reset process +--------------------------------------------------------------------- +THE_RESET_COUNTER_PROC: process( pll_locked, clk_100 ) +begin + if( pll_locked = '0' ) then + -- asynchronous reset by PLL lock signal only + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( rising_edge(clk_100) ) then + if ( make_reset_via_network_q = '1' ) then + -- synchronous reset by network + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( reset_counter = x"EEE" ) then + reset_counter <= x"EEE"; + next_reset <= '0'; + else + reset_counter <= reset_counter + 1; + next_reset <= '1'; + end if; + end if; +end process THE_RESET_COUNTER_PROC; + +-- Fast aysnchronous reset for SerDes +reset_i_q <= not pll_locked; + +gsr_n <= pll_locked; + +-- "normal" synchronous reset signal +reset_i <= next_reset; + +-- reset by TRBnet (port 0 and 3 are uplinks) +make_reset_via_network <= MED_STAT_OP(3*16+13) or MED_STAT_OP(0*16+13); + +THE_RESET_TRG_SYNC: signal_sync +generic map( + DEPTH => 2, + WIDTH => 1 ) +port map( + RESET => '0', + D_IN(0) => make_reset_via_network, + CLK0 => clk_100, + CLK1 => clk_100, + D_OUT(0) => make_reset_via_network_q +); + +--------------------------------------------------------------------- +-- Serdes +--------------------------------------------------------------------- + +-- Input synchronization +THE_SFP_LOS_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + buf_SFP_LOS <= SFP_LOS; + buf_SFP_MOD0 <= SFP_MOD0; + end if; +end process THE_SFP_LOS_PROC; + +--------------------------------------------------------------------- +-- one normal port (SFP18) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(1*16-1 downto 0*16), + MED_PACKET_NUM_IN => med_packet_num_out(1*3-1 downto 0*3), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(1*16-1 downto 0*16), + MED_PACKET_NUM_OUT => med_packet_num_in(1*3-1 downto 0*3), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(18), + SD_RXD_N_IN => SFP_RXN(18), + SD_TXD_P_OUT => SFP_TXP(18), + SD_TXD_N_OUT => SFP_TXN(18), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(18), + SD_LOS_IN => buf_SFP_LOS(18), + SD_TXDIS_OUT => SFP_DIS(18), + STAT_OP => med_stat_op(1*16-1 downto 0*16), + CTRL_OP => med_ctrl_op(1*16-1 downto 0*16), + STAT_DEBUG => med_stat_debug(1*64-1 downto 0*64), + CTRL_DEBUG => med_ctrl_debug(1*64-1 downto 0*64) +); + +--------------------------------------------------------------------- +-- one normal port (SFP19) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + EXT_CLOCK => c_YES, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(2*16-1 downto 1*16), + MED_PACKET_NUM_IN => med_packet_num_out(2*3-1 downto 1*3), + MED_DATAREADY_IN => med_dataready_out(1), + MED_READ_OUT => med_read_in(1), + MED_DATA_OUT => med_data_in(2*16-1 downto 1*16), + MED_PACKET_NUM_OUT => med_packet_num_in(2*3-1 downto 1*3), + MED_DATAREADY_OUT => med_dataready_in(1), + MED_READ_IN => med_read_out(1), + REFCLK2CORE_OUT => clk_in, + SD_RXD_P_IN => SFP_RXP(19), + SD_RXD_N_IN => SFP_RXN(19), + SD_TXD_P_OUT => SFP_TXP(19), + SD_TXD_N_OUT => SFP_TXN(19), + SD_REFCLK_P_IN => SFP_REFCLKP(19), + SD_REFCLK_N_IN => SFP_REFCLKN(19), + SD_PRSNT_N_IN => buf_SFP_MOD0(19), + SD_LOS_IN => buf_SFP_LOS(19), + SD_TXDIS_OUT => SFP_DIS(19), + STAT_OP => med_stat_op(2*16-1 downto 1*16), + CTRL_OP => med_ctrl_op(2*16-1 downto 1*16), + STAT_DEBUG => med_stat_debug(2*64-1 downto 1*64), + CTRL_DEBUG => med_ctrl_debug(2*64-1 downto 1*64) +); + +--------------------------------------------------------------------- +-- Connection between both FPGAs on HUB2 PCB +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC +port map( + CLK => clk_100, + CLK_EN => clk_en, + RESET => reset_i, + --Internal Connection + MED_DATA_IN => med_data_out(3*16-1 downto 2*16), + MED_PACKET_NUM_IN => med_packet_num_out(3*3-1 downto 2*3), + MED_DATAREADY_IN => med_dataready_out(2), + MED_READ_OUT => med_read_in(2), + MED_DATA_OUT => med_data_in(3*16-1 downto 2*16), + MED_PACKET_NUM_OUT => med_packet_num_in(3*3-1 downto 2*3), + MED_DATAREADY_OUT => med_dataready_in(2), + MED_READ_IN => med_read_out(2), + DATA_OUT => F2_TO_F1(31 downto 16), + DATA_VALID_OUT => F2_TO_F1(15), + DATA_CTRL_OUT => F2_TO_F1(14), + DATA_CLK_OUT => F2_TO_F1(1), + DATA_IN => F1_TO_F2(31 downto 16), + DATA_VALID_IN => F1_TO_F2(15), + DATA_CTRL_IN => F1_TO_F2(14), + DATA_CLK_IN => CLK_F1_TO_F2, + STAT_OP => med_stat_op(3*16-1 downto 2*16), + CTRL_OP => med_ctrl_op(3*16-1 downto 2*16), + STAT_DEBUG => med_stat_debug(3*64-1 downto 2*64) +); +--------------------------------------------------------------------- +-- Uplink port (SFP20) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(4*16-1 downto 3*16), + MED_PACKET_NUM_IN => med_packet_num_out(4*3-1 downto 3*3), + MED_DATAREADY_IN => med_dataready_out(3), + MED_READ_OUT => med_read_in(3), + MED_DATA_OUT => med_data_in(4*16-1 downto 3*16), + MED_PACKET_NUM_OUT => med_packet_num_in(4*3-1 downto 3*3), + MED_DATAREADY_OUT => med_dataready_in(3), + MED_READ_IN => med_read_out(3), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(20), + SD_RXD_N_IN => SFP_RXN(20), + SD_TXD_P_OUT => SFP_TXP(20), + SD_TXD_N_OUT => SFP_TXN(20), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(20), + SD_LOS_IN => buf_SFP_LOS(20), + SD_TXDIS_OUT => SFP_DIS(20), + STAT_OP => med_stat_op(4*16-1 downto 3*16), + CTRL_OP => med_ctrl_op(4*16-1 downto 3*16), + STAT_DEBUG => med_stat_debug(4*64-1 downto 3*64), + CTRL_DEBUG => med_ctrl_debug(4*64-1 downto 3*64) +); + +med_ctrl_debug <= (others => '0'); + +--------------------------------------------------------------------- +-- The Hub +--------------------------------------------------------------------- +gen_normal_hub : if USE_ETHERNET = c_NO generate +THE_HUB: trb_net16_hub_base +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => mii, + MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (others => 1), + INT_NUMBER => 0, + INT_CHANNELS => (0,1,3,3,3,3,3,3), + INIT_ENDPOINT_ID => x"0002", + USE_ONEWIRE => c_MONITOR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => CLK_EN, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + INT_INIT_READ_IN => (others => '0'), + INT_INIT_DATAREADY_IN => (others => '0'), + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_IN => (others => '0'), + INT_REPLY_DATAREADY_IN => (others => '0'), + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + --REGIO INTERFACE + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => buf_test +); + +TEST_2 <= (others => '0'); + +--REGISTER_IT_PROC: process( buf_test(31) ) +--begin +-- if rising_edge( buf_test(31) ) then +-- TEST_2(30 downto 0) <= buf_test(30 downto 0); +-- end if; +--end process REGISTER_IT_PROC; +-- +--TEST_2(31) <= buf_test(31); + +end generate; + +gen_ethernet_hub : if USE_ETHERNET = c_YES generate +THE_HUB: trb_net16_hub_streaming_port +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + INIT_ADDRESS => x"affe", +-- MII_NUMBER => mii, +-- MII_IS_UPLINK => ((mii-1) => 1, others => 0), +-- MII_IS_DOWNLINK => ((mii-1) => 0, others => 1), +-- 4 = SFP17 (GbE) +-- 3 = SFP20 (TRBnet) +-- 2 = LVDS (TRBnet) +-- 1 = SFP19 (TRBnet) +-- 0 = SFP18 (TRBnet) + MII_NUMBER => mii, + MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (others => 1), + USE_ONEWIRE => c_MONITOR, + HARDWARE_VERSION => x"62210000", -- gk 26.05.10 + INIT_ENDPOINT_ID => x"0002", + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => clk_en, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + --Event information coming from CTSCTS_READOUT_TYPE_OUT + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => open, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + MY_ADDRESS_OUT => my_address, + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Fixed status and control ports + MPLEX_CTRL => (others => '0'), + STAT_DEBUG => open, --buf_test, + CTRL_DEBUG => (others => '0') +); + +--------------------------------------------------------------------- +-- The GbE machine for blasting out data from TRBnet +--------------------------------------------------------------------- +GBE: trb_net16_gbe_buf +generic map( + DO_SIMULATION => 0, + USE_125MHZ_EXTCLK => 1 +) +port map( + CLK => clk_100, + TEST_CLK => test_clk, + CLK_125_TX_IN => '0', + CLK_125_RX_IN => '0', + RESET => reset_i, + GSR_N => gsr_n, + -- Debug + STAGE_STAT_REGS_OUT => stage_stat_regs, -- should be come STATUS or similar + STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE! + -- gk 22.04.10 not used any more, ip_configurator moved inside + -- configuration interface + IP_CFG_START_IN => stage_ctrl_regs(15), + IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8), + IP_CFG_DONE_OUT => open, + IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr, + IP_CFG_MEM_DATA_IN => ip_cfg_mem_data, + IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk, + MR_RESET_IN => stage_ctrl_regs(3), + MR_MODE_IN => stage_ctrl_regs(1), + MR_RESTART_IN => stage_ctrl_regs(0), + -- gk 29.03.10 + -- interface to ip_configurator memory + SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), + SLV_READ_IN => mb_ip_mem_read, + SLV_WRITE_IN => mb_ip_mem_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ip_mem_ack, + SLV_DATA_IN => mb_ip_mem_data_wr, + SLV_DATA_OUT => mb_ip_mem_data_rd, + -- gk 26.04.10 + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0), + BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs, + BUS_DATA_OUT => gbe_stp_reg_data_rd, + BUS_WRITE_EN_IN => gbe_stp_reg_write, + BUS_READ_EN_IN => gbe_stp_reg_read, + BUS_ACK_OUT => gbe_stp_reg_ack, + -- gk 23.04.10 + LED_PACKET_SENT_OUT => buf_SFP_LED_ORANGE(17), + LED_AN_DONE_N_OUT => buf_SFP_LED_GREEN(17), + -- CTS interface + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + -- Data payload interface + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + --SFP Connection + SFP_RXD_P_IN => SFP_RXP(17), + SFP_RXD_N_IN => SFP_RXN(17), + SFP_TXD_P_OUT => SFP_TXP(17), + SFP_TXD_N_OUT => SFP_TXN(17), + SFP_REFCLK_P_IN => SFP_REFCLKP(17), + SFP_REFCLK_N_IN => SFP_REFCLKN(17), + SFP_PRSNT_N_IN => buf_SFP_MOD0(17), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN => buf_SFP_LOS(17), -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT => SFP_DIS(17), -- SFP disable + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- PacketConstructor interface + IG_CTS_CTR_TST => open, + IG_REM_CTR_TST => open, + IG_BSM_LOAD_TST => open, + IG_BSM_SAVE_TST => open, + IG_DATA_TST(15 downto 8) => open, + IG_DATA_TST(7 downto 0) => buf_test(23 downto 16), --open, + IG_WCNT_TST => open, + IG_RCNT_TST => open, + IG_RD_EN_TST => buf_test(5), --open, + IG_WR_EN_TST => buf_test(6), --open, + IG_EMPTY_TST => open, + IG_AEMPTY_TST => buf_test(7), --open, + IG_FULL_TST => open, + IG_AFULL_TST => buf_test(8), --open, + PC_WR_EN_TST => buf_test(13), --open, + PC_DATA_TST => buf_test(31 downto 24), --open, + PC_READY_TST => buf_test(11), --open, + PC_START_OF_SUB_TST => buf_test(9), --open, + PC_END_OF_DATA_TST => buf_test(10), --open, + PC_SUB_SIZE_TST => open, + PC_TRIG_NR_TST => open, + PC_PADDING_TST => buf_test(12), --open, + PC_DECODING_TST => open, + PC_EVENT_ID_TST => open, + PC_QUEUE_DEC_TST => open, + PC_BSM_CONSTR_TST => open, + PC_BSM_LOAD_TST => open, + PC_BSM_SAVE_TST => open, + PC_ALL_CTR_TST => open, + PC_SUB_CTR_TST => open, + PC_SHF_EMPTY_TST => open, + PC_SHF_FULL_TST => open, + PC_DF_EMPTY_TST => open, + PC_DF_FULL_TST => open, + PC_BYTES_LOADED_TST => open, + PC_SIZE_LEFT_TST => open, + PC_SUB_SIZE_TO_SAVE_TST => open, + PC_SUB_SIZE_LOADED_TST => open, + PC_SUB_BYTES_LOADED_TST => open, + PC_QUEUE_SIZE_TST => open, + PC_ACT_QUEUE_SIZE_TST => open, + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameConstructor interface + FC_WR_EN_TST => open, --buf_test(15), + FC_DATA_TST => open, + FC_H_READY_TST => open, --buf_test(18), --open, + FC_READY_TST => buf_test(14), --open, + FC_IP_SIZE_TST => open, + FC_UDP_SIZE_TST => open, + FC_IDENT_TST => open, + FC_FLAGS_OFFSET_TST => open, + FC_SOD_TST => open, --buf_test(16), --open, + FC_EOD_TST => open, --buf_test(17), --open, + FC_BSM_CONSTR_TST(7 downto 3) => open, + FC_BSM_CONSTR_TST(2 downto 0) => open, --buf_test(28 downto 26), --open, + FC_BSM_TRANS_TST(3) => open, + FC_BSM_TRANS_TST(2 downto 0) => open, --buf_test(31 downto 29), --open, + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameTransmitter interface + FT_DATA_TST(7 downto 3) => open, + FT_DATA_TST(2 downto 0) => open, + FT_TX_EMPTY_TST => open, --buf_test(19), --open, + FT_START_OF_PACKET_TST => open, --buf_test(20), --open, + FT_BSM_INIT_TST => open, + FT_BSM_MAC_TST => open, + FT_BSM_TRANS_TST => open, + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- MAC interface + MAC_HADDR_TST => open, + MAC_HDATA_TST => open, + MAC_HCS_TST => open, + MAC_HWRITE_TST => open, + MAC_HREAD_TST => open, + MAC_HREADY_TST => open, + MAC_HDATA_EN_TST => open, + MAC_FIFOAVAIL_TST => open, --buf_test(23), --open, + MAC_FIFOEOF_TST => open, --buf_test(24), --open, + MAC_FIFOEMPTY_TST => open, --buf_test(25), --open, + MAC_TX_READ_TST => open, --buf_test(21), --open, + MAC_TX_DONE_TST => open, --buf_test(22), --open, + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- pcs and serdes + PCS_AN_LP_ABILITY_TST => open, + PCS_AN_COMPLETE_TST => open, + PCS_AN_PAGE_RX_TST => open, + -- debug ports + ANALYZER_DEBUG_OUT => analyzer_debug --open +); + +--------------------------------------------------------------------- +-- LogicAnalyzer signals +--------------------------------------------------------------------- + +--buf_test(31 downto 0) <= (others => '0'); + +buf_test(15) <= clk_100; + +buf_test(4) <= fee_busy; +buf_test(3) <= fee_read; +buf_test(2) <= fee_dataready; +buf_test(1) <= cts_readout_finished; +buf_test(0) <= cts_start_readout; + +-- output to pads +--TEST_2 <= buf_test; +REGISTER_IT_PROC: process( buf_test(15) ) +begin + if rising_edge( buf_test(15) ) then + TEST_2(31 downto 16) <= buf_test(31 downto 16); + TEST_2(14 downto 0) <= buf_test(14 downto 0); + end if; +end process REGISTER_IT_PROC; + +TEST_2(15) <= buf_test(15); + +end generate; + +--------------------------------------------------------------------- +-- The Bus Handler for all Slow Control Activities +--------------------------------------------------------------------- +-- reserved address space C000 - FFFF +THE_BUS_HANDLER: trb_net16_regio_bus_handler +generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => ( 0 => x"8000", 1 => x"8200", 2 => x"8100", 3=> x"8300", others => x"0000" ), -- gk 22.04.10 + PORT_ADDR_MASK => ( 0 => 0, 1 => 0, 2 => 8, 3 => 8, others => 0) -- gk 22.04.10 +) +port map( + CLK => clk_100, + RESET => reset_i, + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + -- my registers + -- first one - control + BUS_ADDR_OUT(1*16-1 downto 0*16) => ctrl_reg_addr, + BUS_DATA_OUT(1*32-1 downto 0*32) => mb_ctrl_reg_data_wr, + BUS_READ_ENABLE_OUT(0) => mb_ctrl_reg_read, + BUS_WRITE_ENABLE_OUT(0) => mb_ctrl_reg_write, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(1*32-1 downto 0*32) => mb_ctrl_reg_data_rd, + BUS_DATAREADY_IN(0) => mb_ctrl_reg_ack, + BUS_WRITE_ACK_IN(0) => mb_ctrl_reg_ack, + BUS_NO_MORE_DATA_IN(0) => '0', + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- second one - status + BUS_ADDR_OUT(2*16-1 downto 1*16) => open, + BUS_DATA_OUT(2*32-1 downto 1*32) => mb_stat_reg_data_wr, + BUS_READ_ENABLE_OUT(1) => mb_stat_reg_read, + BUS_WRITE_ENABLE_OUT(1) => mb_stat_reg_write, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(2*32-1 downto 1*32) => mb_stat_reg_data_rd, + BUS_DATAREADY_IN(1) => mb_stat_reg_ack, + BUS_WRITE_ACK_IN(1) => mb_stat_reg_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + ---- + STAT_DEBUG => open +); + +--------------------------------------------------------------------- +-- MB CTRL REGISTER +--------------------------------------------------------------------- +MB_CTRL_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_ctrl_reg_read, + SLV_WRITE_IN => mb_ctrl_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ctrl_reg_ack, + SLV_DATA_IN => mb_ctrl_reg_data_wr, + SLV_DATA_OUT => mb_ctrl_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_ctrl_regs, + REG_DATA_OUT => stage_ctrl_regs, + -- Status lines + STAT => open +); + +-- gk 26.04.10 +-- gk 22.04.10 register to manage gbe setup registers +-- GBE_SETUP_REGISTER : slv_register +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_READ_IN => gbe_stp_reg_read, +-- SLV_WRITE_IN => gbe_stp_reg_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => gbe_stp_reg_ack, +-- SLV_DATA_IN => gbe_stp_reg_data_wr, +-- SLV_DATA_OUT => gbe_stp_reg_data_rd, +-- -- I/O to the backend +-- REG_DATA_IN => gbe_stp_data, +-- REG_DATA_OUT => gbe_stp_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- MB STAT REGISTER +--------------------------------------------------------------------- +MB_STAT_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_stat_reg_read, + SLV_WRITE_IN => mb_stat_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_stat_reg_ack, + SLV_DATA_IN => mb_stat_reg_data_wr, + SLV_DATA_OUT => mb_stat_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_stat_regs, + REG_DATA_OUT => open, + -- Status lines + STAT => open +); + +-- gk 29.03.10 component moved to gbe_buf +--------------------------------------------------------------------- +-- MB IP CONFIG MEMORY +--------------------------------------------------------------------- +-- MB_IP_CONFIG: slv_mac_memory +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), +-- SLV_READ_IN => mb_ip_mem_read, +-- SLV_WRITE_IN => mb_ip_mem_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => mb_ip_mem_ack, +-- SLV_DATA_IN => mb_ip_mem_data_wr, +-- SLV_DATA_OUT => mb_ip_mem_data_rd, +-- -- I/O to the backend +-- MEM_CLK_IN => ip_cfg_mem_clk, +-- MEM_ADDR_IN => ip_cfg_mem_addr, +-- MEM_DATA_OUT => ip_cfg_mem_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- Funny LEDs ;-) +--------------------------------------------------------------------- +buf_SFP_LED_ORANGE(18) <= not (med_stat_op(10) or med_stat_op(11)); +buf_SFP_LED_GREEN(18) <= not med_stat_op(9); + +buf_SFP_LED_ORANGE(19) <= not (med_stat_op(10+16) or med_stat_op(11+16)); +buf_SFP_LED_GREEN(19) <= not med_stat_op(9+16); + +buf_SFP_LED_ORANGE(20) <= not (med_stat_op(10+48) or med_stat_op(11+48)); +buf_SFP_LED_GREEN(20) <= not med_stat_op(9+48); + +-- gk 24.04.10 +--buf_SFP_LED_ORANGE(17) <= '0'; +--buf_SFP_LED_GREEN(17) <= '1'; + + +THE_LED_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + SFP_LED_GREEN <= buf_SFP_LED_GREEN; + SFP_LED_ORANGE <= buf_SFP_LED_ORANGE; + end if; +end process THE_LED_PROC; + +--------------------------------------------------------------------- +--Debugging +--------------------------------------------------------------------- + + +end architecture; +======= +--Port 19&20 is uplink, Port 18 is downlinks, 17 is reserved for Ethernet + +--the hub logic reports +--sfp 18 = port 0 +--sfp 19 = port 1 Slowcontrol +--lvds = port 2 to FPGA1 +--sfp 20 = port 3 CTS + +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; + + +entity hub2_fpga2 is +generic( USE_ETHERNET : integer range c_NO to c_YES := c_YES; + USE_200_MHZ : integer range c_NO to c_YES := c_YES + ); +port( +-- CLK_F2_TO_F1 : out std_logic; -- unused + CLK_F1_TO_F2 : in std_logic; +-- ADDON_RESET : in std_logic; -- unused +-- RESET_N : in std_logic; -- unused +-- SUPPL_RESET_N : in std_logic; -- unused + --Connection to TRB +-- ADO_LV : inout std_logic_vector(61 downto 0); +-- ADO_TTL : inout std_logic_vector(45 downto 0); + --Connection to FPGA1 + F1_TO_F2 : in std_logic_vector(31 downto 0); + F2_TO_F1 : out std_logic_vector(31 downto 0); + --Optical Links + SFP_TXP : out std_logic_vector(20 downto 17); + SFP_TXN : out std_logic_vector(20 downto 17); + SFP_RXP : in std_logic_vector(20 downto 17); + SFP_RXN : in std_logic_vector(20 downto 17); + SFP_REFCLKP : in std_logic_vector(20 downto 17); + SFP_REFCLKN : in std_logic_vector(20 downto 17); + SFP_LED_GREEN : out std_logic_vector(20 downto 17); + SFP_LED_ORANGE : out std_logic_vector(20 downto 17); + SFP_MOD0 : in std_logic_vector(20 downto 17); + SFP_LOS : in std_logic_vector(20 downto 17); + SFP_DIS : out std_logic_vector(20 downto 17); + --Other + ONEWIRE_MONITOR_IN : in std_logic; + --Debugging + TEST_2 : out std_logic_vector(31 downto 0) +); + +attribute syn_useioff : boolean; +attribute syn_useioff of F1_TO_F2 : signal is true; +attribute syn_useioff of F2_TO_F1 : signal is true; + +attribute syn_useioff of SFP_LED_GREEN : signal is false; +attribute syn_useioff of SFP_LED_ORANGE : signal is false; + +end entity; + +architecture hub2_fpga2_arch of hub2_fpga2 is + +component slv_register is +generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component; + +component trb_net16_gbe_buf is +generic( + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); +port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector (31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component; + +constant mii : integer := 4; + +-- Clocks and reset +signal clk_in : std_logic; -- clock from SerDes reference output (100MHz or 200MHz) +signal clk_100 : std_logic; -- 100MHz system clock +signal clk_en : std_logic; +signal reset_i_q : std_logic; -- fast async reset for SerDes +signal pll_locked : std_logic; +signal reset_counter : std_logic_vector(11 downto 0); +signal next_reset : std_logic; +signal reset_i : std_logic; +signal make_reset_via_network_q : std_logic; +signal make_reset_via_network : std_logic; +signal gsr_n : std_logic; + +signal test_clk : std_logic; -- MUST BE ZERO!!! + +signal buf_SFP_LOS : std_logic_vector(20 downto 17); +signal buf_SFP_MOD0 : std_logic_vector(20 downto 17); + +signal med_data_in : std_logic_vector(4*16-1 downto 0); +signal med_data_out : std_logic_vector(4*16-1 downto 0); +signal med_packet_num_in : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_packet_num_out : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal med_dataready_in : std_logic_vector(3 downto 0); +signal med_dataready_out : std_logic_vector(3 downto 0); +signal med_read_in : std_logic_vector(3 downto 0); +signal med_read_out : std_logic_vector(3 downto 0); + +signal med_stat_op : std_logic_vector(4*16-1 downto 0); +signal med_ctrl_op : std_logic_vector(4*16-1 downto 0); +signal med_stat_debug : std_logic_vector(4*64-1 downto 0); +signal med_ctrl_debug : std_logic_vector(4*64-1 downto 0); + +signal buf_SFP_LED_ORANGE : std_logic_vector(20 downto 17); +signal buf_SFP_LED_GREEN : std_logic_vector(20 downto 17); + +signal cts_number : std_logic_vector(15 downto 0); +signal cts_code : std_logic_vector(7 downto 0); +signal cts_information : std_logic_vector(7 downto 0); +signal cts_start_readout : std_logic; +signal cts_readout_type : std_logic_vector(3 downto 0); +signal cts_data : std_logic_vector(31 downto 0); +signal cts_dataready : std_logic; +signal cts_readout_finished : std_logic; +signal cts_read : std_logic; +signal cts_length : std_logic_vector(15 downto 0); +signal cts_status_bits : std_logic_vector(31 downto 0); +signal fee_data : std_logic_vector(15 downto 0); +signal fee_dataready : std_logic; +signal fee_read : std_logic; +signal fee_status_bits : std_logic_vector(31 downto 0); +signal fee_busy : std_logic; +signal my_address : std_logic_vector(15 downto 0); + +signal stage_stat_regs : std_logic_vector (31 downto 0); +signal stage_ctrl_regs : std_logic_vector (31 downto 0); + +--REGIO INTERFACE +signal regio_addr_out : std_logic_vector(16-1 downto 0); +signal regio_read_enable_out : std_logic; +signal regio_write_enable_out : std_logic; +signal regio_data_out : std_logic_vector(32-1 downto 0); +signal regio_data_in : std_logic_vector(32-1 downto 0) := (others => '0'); +signal regio_dataready_in : std_logic := '0'; +signal regio_no_more_data_in : std_logic := '0'; +signal regio_write_ack_in : std_logic := '0'; +signal regio_unknown_addr_in : std_logic := '0'; +signal regio_timeout_out : std_logic; + +signal mb_ctrl_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_ctrl_reg_read : std_logic; +signal mb_ctrl_reg_write : std_logic; +signal mb_ctrl_reg_ack : std_logic; + +signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); +signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); +signal mb_stat_reg_read : std_logic; +signal mb_stat_reg_write : std_logic; +signal mb_stat_reg_ack : std_logic; + +signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used +signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); +signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); +signal mb_ip_mem_read : std_logic; +signal mb_ip_mem_write : std_logic; +signal mb_ip_mem_ack : std_logic; + +signal ip_cfg_mem_clk : std_logic; +signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); +signal ip_cfg_mem_data : std_logic_vector(31 downto 0); + +signal buf_test : std_logic_vector(31 downto 0); + +signal analyzer_debug : std_logic_vector(63 downto 0); + +-- gk 22.04.10 +signal ctrl_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); +signal gbe_stp_data : std_logic_vector(31 downto 0); +signal gbe_stp_reg_ack : std_logic; +signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); +signal gbe_stp_reg_read : std_logic; +signal gbe_stp_reg_write : std_logic; +signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); + + +begin + +--------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------- +gen_no_pll : if USE_200_MHZ = c_NO generate +THE_PLL : pll_in100_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +gen_pll : if USE_200_MHZ = c_YES generate +THE_PLL : pll_in200_out100 +port map( CLK => clk_in, + CLKOP => clk_100, + LOCK => pll_locked + ); +end generate; + +clk_en <= '1'; +test_clk <= '0'; + +--------------------------------------------------------------------- +-- Reset process +--------------------------------------------------------------------- +THE_RESET_COUNTER_PROC: process( pll_locked, clk_100 ) +begin + if( pll_locked = '0' ) then + -- asynchronous reset by PLL lock signal only + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( rising_edge(clk_100) ) then + if ( make_reset_via_network_q = '1' ) then + -- synchronous reset by network + reset_counter <= (others => '0'); + next_reset <= '1'; + elsif( reset_counter = x"EEE" ) then + reset_counter <= x"EEE"; + next_reset <= '0'; + else + reset_counter <= reset_counter + 1; + next_reset <= '1'; + end if; + end if; +end process THE_RESET_COUNTER_PROC; + +-- Fast aysnchronous reset for SerDes +reset_i_q <= not pll_locked; + +gsr_n <= pll_locked; + +-- "normal" synchronous reset signal +reset_i <= next_reset; + +-- reset by TRBnet (port 0 and 3 are uplinks) +make_reset_via_network <= MED_STAT_OP(3*16+13) or MED_STAT_OP(0*16+13); + +THE_RESET_TRG_SYNC: signal_sync +generic map( + DEPTH => 2, + WIDTH => 1 ) +port map( + RESET => '0', + D_IN(0) => make_reset_via_network, + CLK0 => clk_100, + CLK1 => clk_100, + D_OUT(0) => make_reset_via_network_q +); + +--------------------------------------------------------------------- +-- Serdes +--------------------------------------------------------------------- + +-- Input synchronization +THE_SFP_LOS_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + buf_SFP_LOS <= SFP_LOS; + buf_SFP_MOD0 <= SFP_MOD0; + end if; +end process THE_SFP_LOS_PROC; + +--------------------------------------------------------------------- +-- one normal port (SFP18) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(1*16-1 downto 0*16), + MED_PACKET_NUM_IN => med_packet_num_out(1*3-1 downto 0*3), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(1*16-1 downto 0*16), + MED_PACKET_NUM_OUT => med_packet_num_in(1*3-1 downto 0*3), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(18), + SD_RXD_N_IN => SFP_RXN(18), + SD_TXD_P_OUT => SFP_TXP(18), + SD_TXD_N_OUT => SFP_TXN(18), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(18), + SD_LOS_IN => buf_SFP_LOS(18), + SD_TXDIS_OUT => SFP_DIS(18), + STAT_OP => med_stat_op(1*16-1 downto 0*16), + CTRL_OP => med_ctrl_op(1*16-1 downto 0*16), + STAT_DEBUG => med_stat_debug(1*64-1 downto 0*64), + CTRL_DEBUG => med_ctrl_debug(1*64-1 downto 0*64) +); + +--------------------------------------------------------------------- +-- one normal port (SFP19) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + EXT_CLOCK => c_YES, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(2*16-1 downto 1*16), + MED_PACKET_NUM_IN => med_packet_num_out(2*3-1 downto 1*3), + MED_DATAREADY_IN => med_dataready_out(1), + MED_READ_OUT => med_read_in(1), + MED_DATA_OUT => med_data_in(2*16-1 downto 1*16), + MED_PACKET_NUM_OUT => med_packet_num_in(2*3-1 downto 1*3), + MED_DATAREADY_OUT => med_dataready_in(1), + MED_READ_IN => med_read_out(1), + REFCLK2CORE_OUT => clk_in, + SD_RXD_P_IN => SFP_RXP(19), + SD_RXD_N_IN => SFP_RXN(19), + SD_TXD_P_OUT => SFP_TXP(19), + SD_TXD_N_OUT => SFP_TXN(19), + SD_REFCLK_P_IN => SFP_REFCLKP(19), + SD_REFCLK_N_IN => SFP_REFCLKN(19), + SD_PRSNT_N_IN => buf_SFP_MOD0(19), + SD_LOS_IN => buf_SFP_LOS(19), + SD_TXDIS_OUT => SFP_DIS(19), + STAT_OP => med_stat_op(2*16-1 downto 1*16), + CTRL_OP => med_ctrl_op(2*16-1 downto 1*16), + STAT_DEBUG => med_stat_debug(2*64-1 downto 1*64), + CTRL_DEBUG => med_ctrl_debug(2*64-1 downto 1*64) +); + +--------------------------------------------------------------------- +-- Connection between both FPGAs on HUB2 PCB +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC +port map( + CLK => clk_100, + CLK_EN => clk_en, + RESET => reset_i, + --Internal Connection + MED_DATA_IN => med_data_out(3*16-1 downto 2*16), + MED_PACKET_NUM_IN => med_packet_num_out(3*3-1 downto 2*3), + MED_DATAREADY_IN => med_dataready_out(2), + MED_READ_OUT => med_read_in(2), + MED_DATA_OUT => med_data_in(3*16-1 downto 2*16), + MED_PACKET_NUM_OUT => med_packet_num_in(3*3-1 downto 2*3), + MED_DATAREADY_OUT => med_dataready_in(2), + MED_READ_IN => med_read_out(2), + DATA_OUT => F2_TO_F1(31 downto 16), + DATA_VALID_OUT => F2_TO_F1(15), + DATA_CTRL_OUT => F2_TO_F1(14), + DATA_CLK_OUT => F2_TO_F1(1), + DATA_IN => F1_TO_F2(31 downto 16), + DATA_VALID_IN => F1_TO_F2(15), + DATA_CTRL_IN => F1_TO_F2(14), + DATA_CLK_IN => CLK_F1_TO_F2, + STAT_OP => med_stat_op(3*16-1 downto 2*16), + CTRL_OP => med_ctrl_op(3*16-1 downto 2*16), + STAT_DEBUG => med_stat_debug(3*64-1 downto 2*64) +); +--------------------------------------------------------------------- +-- Uplink port (SFP20) +--------------------------------------------------------------------- +THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 0, + USE_200_MHZ => USE_200_MHZ +) +port map( + CLK => clk_in, + SYSCLK => clk_100, + RESET => reset_i, + CLEAR => reset_i_q, + CLK_EN => clk_en, + MED_DATA_IN => med_data_out(4*16-1 downto 3*16), + MED_PACKET_NUM_IN => med_packet_num_out(4*3-1 downto 3*3), + MED_DATAREADY_IN => med_dataready_out(3), + MED_READ_OUT => med_read_in(3), + MED_DATA_OUT => med_data_in(4*16-1 downto 3*16), + MED_PACKET_NUM_OUT => med_packet_num_in(4*3-1 downto 3*3), + MED_DATAREADY_OUT => med_dataready_in(3), + MED_READ_IN => med_read_out(3), + REFCLK2CORE_OUT => open, + SD_RXD_P_IN => SFP_RXP(20), + SD_RXD_N_IN => SFP_RXN(20), + SD_TXD_P_OUT => SFP_TXP(20), + SD_TXD_N_OUT => SFP_TXN(20), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => buf_SFP_MOD0(20), + SD_LOS_IN => buf_SFP_LOS(20), + SD_TXDIS_OUT => SFP_DIS(20), + STAT_OP => med_stat_op(4*16-1 downto 3*16), + CTRL_OP => med_ctrl_op(4*16-1 downto 3*16), + STAT_DEBUG => med_stat_debug(4*64-1 downto 3*64), + CTRL_DEBUG => med_ctrl_debug(4*64-1 downto 3*64) +); + +med_ctrl_debug <= (others => '0'); + +--------------------------------------------------------------------- +-- The Hub +--------------------------------------------------------------------- +gen_normal_hub : if USE_ETHERNET = c_NO generate +THE_HUB: trb_net16_hub_base +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + MII_NUMBER => mii, + MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (others => 1), + INT_NUMBER => 0, + INT_CHANNELS => (0,1,3,3,3,3,3,3), + INIT_ENDPOINT_ID => x"0002", + USE_ONEWIRE => c_MONITOR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => CLK_EN, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + INT_INIT_READ_IN => (others => '0'), + INT_INIT_DATAREADY_IN => (others => '0'), + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_IN => (others => '0'), + INT_REPLY_DATAREADY_IN => (others => '0'), + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + --REGIO INTERFACE + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => buf_test +); + +TEST_2 <= (others => '0'); + +--REGISTER_IT_PROC: process( buf_test(31) ) +--begin +-- if rising_edge( buf_test(31) ) then +-- TEST_2(30 downto 0) <= buf_test(30 downto 0); +-- end if; +--end process REGISTER_IT_PROC; +-- +--TEST_2(31) <= buf_test(31); + +end generate; + +gen_ethernet_hub : if USE_ETHERNET = c_YES generate +THE_HUB: trb_net16_hub_streaming_port +generic map( + HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), + IBUF_SECURE_MODE => c_YES, + INIT_ADDRESS => x"affe", +-- MII_NUMBER => mii, +-- MII_IS_UPLINK => ((mii-1) => 1, others => 0), +-- MII_IS_DOWNLINK => ((mii-1) => 0, others => 1), +-- 4 = SFP17 (GbE) +-- 3 = SFP20 (TRBnet) +-- 2 = LVDS (TRBnet) +-- 1 = SFP19 (TRBnet) +-- 0 = SFP18 (TRBnet) + MII_NUMBER => mii, + MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1), + MII_IS_DOWNLINK => (others => 1), + USE_ONEWIRE => c_MONITOR, + HARDWARE_VERSION => x"62210000", -- gk 26.05.10 + INIT_ENDPOINT_ID => x"0002", + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) +) +port map( + CLK => clk_100, + RESET => reset_i, + CLK_EN => clk_en, + --Media interfacces + MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), + MED_DATA_OUT => med_data_out(mii*16-1 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0), + MED_READ_IN => med_read_in(mii-1 downto 0), + MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), + MED_DATA_IN => med_data_in(mii*16-1 downto 0), + MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), + MED_READ_OUT => med_read_out(mii-1 downto 0), + MED_STAT_OP => med_stat_op(mii*16-1 downto 0), + MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0), + --Event information coming from CTSCTS_READOUT_TYPE_OUT + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => open, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, + MY_ADDRESS_OUT => my_address, + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --Fixed status and control ports + MPLEX_CTRL => (others => '0'), + STAT_DEBUG => open, --buf_test, + CTRL_DEBUG => (others => '0') +); + +--------------------------------------------------------------------- +-- The GbE machine for blasting out data from TRBnet +--------------------------------------------------------------------- + +GBE: trb_net16_gbe_buf +generic map( + DO_SIMULATION => 0, + USE_125MHZ_EXTCLK => 1 +) +port map( + CLK => clk_100, + TEST_CLK => test_clk, + CLK_125_IN => '0', + RESET => reset_i, + GSR_N => gsr_n, + -- Debug + STAGE_STAT_REGS_OUT => stage_stat_regs, -- should be come STATUS or similar + STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE! + -- gk 22.04.10 not used any more, ip_configurator moved inside + -- configuration interface + IP_CFG_START_IN => stage_ctrl_regs(15), + IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8), + IP_CFG_DONE_OUT => open, + IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr, + IP_CFG_MEM_DATA_IN => ip_cfg_mem_data, + IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk, + MR_RESET_IN => stage_ctrl_regs(3), + MR_MODE_IN => stage_ctrl_regs(1), + MR_RESTART_IN => stage_ctrl_regs(0), + -- gk 29.03.10 + -- interface to ip_configurator memory + SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), + SLV_READ_IN => mb_ip_mem_read, + SLV_WRITE_IN => mb_ip_mem_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ip_mem_ack, + SLV_DATA_IN => mb_ip_mem_data_wr, + SLV_DATA_OUT => mb_ip_mem_data_rd, + -- gk 26.04.10 + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0), + BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs, + BUS_DATA_OUT => gbe_stp_reg_data_rd, + BUS_WRITE_EN_IN => gbe_stp_reg_write, + BUS_READ_EN_IN => gbe_stp_reg_read, + BUS_ACK_OUT => gbe_stp_reg_ack, + -- gk 23.04.10 + LED_PACKET_SENT_OUT => buf_SFP_LED_ORANGE(17), + LED_AN_DONE_N_OUT => buf_SFP_LED_GREEN(17), + -- CTS interface + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + -- Data payload interface + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + --SFP Connection + SFP_RXD_P_IN => SFP_RXP(17), + SFP_RXD_N_IN => SFP_RXN(17), + SFP_TXD_P_OUT => SFP_TXP(17), + SFP_TXD_N_OUT => SFP_TXN(17), + SFP_REFCLK_P_IN => SFP_REFCLKP(17), + SFP_REFCLK_N_IN => SFP_REFCLKN(17), + SFP_PRSNT_N_IN => buf_SFP_MOD0(17), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN => buf_SFP_LOS(17), -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT => SFP_DIS(17), -- SFP disable + ANALYZER_DEBUG_OUT => analyzer_debug --open +); + +--------------------------------------------------------------------- +-- LogicAnalyzer signals +--------------------------------------------------------------------- + +--buf_test(31 downto 0) <= (others => '0'); + +buf_test(15) <= clk_100; + +buf_test(4) <= fee_busy; +buf_test(3) <= fee_read; +buf_test(2) <= fee_dataready; +buf_test(1) <= cts_readout_finished; +buf_test(0) <= cts_start_readout; + +-- output to pads +--TEST_2 <= buf_test; +REGISTER_IT_PROC: process( buf_test(15) ) +begin + if rising_edge( buf_test(15) ) then + TEST_2(31 downto 16) <= buf_test(31 downto 16); + TEST_2(14 downto 0) <= buf_test(14 downto 0); + end if; +end process REGISTER_IT_PROC; + +TEST_2(15) <= buf_test(15); + +end generate; + +--------------------------------------------------------------------- +-- The Bus Handler for all Slow Control Activities +--------------------------------------------------------------------- +-- reserved address space C000 - FFFF +THE_BUS_HANDLER: trb_net16_regio_bus_handler +generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => ( 0 => x"8000", 1 => x"8200", 2 => x"8100", 3=> x"8300", others => x"0000" ), -- gk 22.04.10 + PORT_ADDR_MASK => ( 0 => 0, 1 => 0, 2 => 8, 3 => 8, others => 0) -- gk 22.04.10 +) +port map( + CLK => clk_100, + RESET => reset_i, + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + -- my registers + -- first one - control + BUS_ADDR_OUT(1*16-1 downto 0*16) => ctrl_reg_addr, + BUS_DATA_OUT(1*32-1 downto 0*32) => mb_ctrl_reg_data_wr, + BUS_READ_ENABLE_OUT(0) => mb_ctrl_reg_read, + BUS_WRITE_ENABLE_OUT(0) => mb_ctrl_reg_write, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(1*32-1 downto 0*32) => mb_ctrl_reg_data_rd, + BUS_DATAREADY_IN(0) => mb_ctrl_reg_ack, + BUS_WRITE_ACK_IN(0) => mb_ctrl_reg_ack, + BUS_NO_MORE_DATA_IN(0) => '0', + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- second one - status + BUS_ADDR_OUT(2*16-1 downto 1*16) => open, + BUS_DATA_OUT(2*32-1 downto 1*32) => mb_stat_reg_data_wr, + BUS_READ_ENABLE_OUT(1) => mb_stat_reg_read, + BUS_WRITE_ENABLE_OUT(1) => mb_stat_reg_write, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(2*32-1 downto 1*32) => mb_stat_reg_data_rd, + BUS_DATAREADY_IN(1) => mb_stat_reg_ack, + BUS_WRITE_ACK_IN(1) => mb_stat_reg_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + ---- + STAT_DEBUG => open +); + +--------------------------------------------------------------------- +-- MB CTRL REGISTER +--------------------------------------------------------------------- +MB_CTRL_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_ctrl_reg_read, + SLV_WRITE_IN => mb_ctrl_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_ctrl_reg_ack, + SLV_DATA_IN => mb_ctrl_reg_data_wr, + SLV_DATA_OUT => mb_ctrl_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_ctrl_regs, + REG_DATA_OUT => stage_ctrl_regs, + -- Status lines + STAT => open +); + +-- gk 26.04.10 +-- gk 22.04.10 register to manage gbe setup registers +-- GBE_SETUP_REGISTER : slv_register +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_READ_IN => gbe_stp_reg_read, +-- SLV_WRITE_IN => gbe_stp_reg_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => gbe_stp_reg_ack, +-- SLV_DATA_IN => gbe_stp_reg_data_wr, +-- SLV_DATA_OUT => gbe_stp_reg_data_rd, +-- -- I/O to the backend +-- REG_DATA_IN => gbe_stp_data, +-- REG_DATA_OUT => gbe_stp_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- MB STAT REGISTER +--------------------------------------------------------------------- +MB_STAT_REGISTER : slv_register +port map( + CLK_IN => clk_100, + RESET_IN => reset_i, + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => mb_stat_reg_read, + SLV_WRITE_IN => mb_stat_reg_write, + SLV_BUSY_OUT => open, + SLV_ACK_OUT => mb_stat_reg_ack, + SLV_DATA_IN => mb_stat_reg_data_wr, + SLV_DATA_OUT => mb_stat_reg_data_rd, + -- I/O to the backend + REG_DATA_IN => stage_stat_regs, + REG_DATA_OUT => open, + -- Status lines + STAT => open +); + +-- gk 29.03.10 component moved to gbe_buf +--------------------------------------------------------------------- +-- MB IP CONFIG MEMORY +--------------------------------------------------------------------- +-- MB_IP_CONFIG: slv_mac_memory +-- port map( +-- CLK => clk_100, +-- RESET => reset_i, +-- BUSY_IN => '0', +-- -- Slave bus +-- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0), +-- SLV_READ_IN => mb_ip_mem_read, +-- SLV_WRITE_IN => mb_ip_mem_write, +-- SLV_BUSY_OUT => open, +-- SLV_ACK_OUT => mb_ip_mem_ack, +-- SLV_DATA_IN => mb_ip_mem_data_wr, +-- SLV_DATA_OUT => mb_ip_mem_data_rd, +-- -- I/O to the backend +-- MEM_CLK_IN => ip_cfg_mem_clk, +-- MEM_ADDR_IN => ip_cfg_mem_addr, +-- MEM_DATA_OUT => ip_cfg_mem_data, +-- -- Status lines +-- STAT => open +-- ); + +--------------------------------------------------------------------- +-- Funny LEDs ;-) +--------------------------------------------------------------------- +buf_SFP_LED_ORANGE(18) <= not (med_stat_op(10) or med_stat_op(11)); +buf_SFP_LED_GREEN(18) <= not med_stat_op(9); + +buf_SFP_LED_ORANGE(19) <= not (med_stat_op(10+16) or med_stat_op(11+16)); +buf_SFP_LED_GREEN(19) <= not med_stat_op(9+16); + +buf_SFP_LED_ORANGE(20) <= not (med_stat_op(10+48) or med_stat_op(11+48)); +buf_SFP_LED_GREEN(20) <= not med_stat_op(9+48); + +-- gk 24.04.10 +--buf_SFP_LED_ORANGE(17) <= '0'; +--buf_SFP_LED_GREEN(17) <= '1'; + + +THE_LED_PROC: process( clk_100 ) +begin + if( rising_edge(clk_100) ) then + SFP_LED_GREEN <= buf_SFP_LED_GREEN; + SFP_LED_ORANGE <= buf_SFP_LED_ORANGE; + end if; +end process THE_LED_PROC; + +--------------------------------------------------------------------- +--Debugging +--------------------------------------------------------------------- + + +end architecture;>>>>>>> 1.20 diff --git a/hub2_fpga2_cvs.prj b/hub2_fpga2_cvs.prj new file mode 100644 index 0000000..b470259 --- /dev/null +++ b/hub2_fpga2_cvs.prj @@ -0,0 +1,344 @@ +#-- Lattice Semiconductor Corporation Ltd. + +#-- Synplify OEM project file i:/vhdl_pro/newhub3/hub2\work.hub2_fpga2.prj + +#-- Written on Wed Mar 03 12:12:16 2010 + + + +#device options + +set_option -technology LATTICE-ecp2m + +set_option -part LFE2M100E + +set_option -speed_grade -5 + + + +#compilation/mapping options + +set_option -default_enum_encoding default + +set_option -symbolic_fsm_compiler true + +set_option -resource_sharing true + + + +#use verilog 2001 standard option + +set_option -vlog_std v2001 + + + +#map options + +set_option -frequency 200 + +set_option -fanout_limit 100 + +set_option -auto_constrain_io true + +set_option -disable_io_insertion false + +set_option -retiming false + +set_option -pipe false + +set_option -force_gsr false + +set_option -compiler_compatible true + +set_option -dup false + + + +#simulation options + +set_option -write_verilog true + +set_option -write_vhdl true + + + +#timing analysis options + +set_option -num_critical_paths 3 + +set_option -num_startend_points 0 + + + +#automatic place and route (vendor) options + +set_option -write_apr_constraint 0 + + + +#synplifyPro options. + +set_option -fixgatedclocks 3 + + + +#synplifyPro options. + +set_option -fixgeneratedclocks 3 + + + +#-- add_file options + +# ECP2M library -- really needed? + +#add_file -vhdl -lib work "/usr/local/opt/synplify/8/isptools/cae_library/synthesis/vhdl/ecp2m.vhd" +add_file -vhdl -lib work "/opt/lattice/ispLEVER8.0/isptools/cae_library/synthesis/vhdl/ecp2m.vhd" + + +# GbE specific files + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/mb_mac_sim.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_ipu2gbe.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ip_configurator.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_buf.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/trb_net16_gbe_setup.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/slv_mac_memory.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/slv_register.vhd" + + + +# IPexpress files + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/ip_mem.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/mac_init_mem.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_4096x9.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_2048x8.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_64kx8.vhd" + +add_file -vhdl -lib work "../trbnet/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd" + + + +# TRBnet files + +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_hub_func.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" + +add_file -vhdl -lib work "../trbnet/basics/rom_16x16.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" + +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_api_ipu_streaming.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd" + +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" + +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" + +add_file -vhdl -lib work "../trbnet/basics/wide_adder_17x16.vhd" + +add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_hub_streaming_port.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" + +add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.vhd" + +add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.vhd" + +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" + +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net16_med_16_IC.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/pll_in200_out100.vhd" + +add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" + +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" + + + +# real "local" files + +add_file -vhdl -lib work "version.vhd" + +add_file -vhdl -lib work "hub2_fpga2.vhd" + + + +# implementation: "workdir" + +impl -add workdir -type fpga + + + +# device options + +set_option -technology LATTICE-ECP2M + +set_option -part LFE2M100E + +set_option -package F900C + +set_option -speed_grade -5 + + + +# compilation/mapping options + +set_option -default_enum_encoding sequential + +set_option -symbolic_fsm_compiler 1 + +set_option -top_module hub2_fpga2 + + + +# map options + +set_option -frequency 100 + +set_option -fanout_limit 100 + +set_option -disable_io_insertion 0 + +set_option -retiming 0 + +set_option -pipe 0 + +# set_option -force_gsr auto + +set_option -force_gsr false + +set_option -fixgatedclocks 3 + +set_option -fixgeneratedclocks 3 + + + +# simulation options + +set_option -write_verilog 0 + +set_option -write_vhdl 1 + + + +# automatic place and route (vendor) options + +set_option -write_apr_constraint 0 + + + +# set result format/file last + +project -result_format "edif" + +project -result_file "workdir/hub2_fpga2.edf" + + + +#-- error message log file + +project -log_file "workdir/hub2_fpga2.srr" + + + +#implementation attributes + +set_option -vlog_std v2001 + +set_option -project_relative_includes 1 + +impl -active "workdir" + + + +#-- run Synplify with 'arrange VHDL file' + +project -run hdl_info_gen -fileorder + +project -run + diff --git a/hub2_full.xcf b/hub2_full.xcf new file mode 100644 index 0000000..366c6e5 --- /dev/null +++ b/hub2_full.xcf @@ -0,0 +1,133 @@ + + + + + + JTAG + + 1 + NA + Generic JTAG Device + JTAG-NOP + All + JTAG-NOP + + 10 + 1111111111 + 1 + 0 + + Bypass + + + + 2 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /d/jspc22/trb/cvs/hub2/workdir/hub2_fpga1.bit + /root/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 4/13/2011 20:5:0 + Fast Program + + + + 3 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /d/jspc22/trb/cvs/hub2/workdir/hub2_fpga2.bit + /d/sugar/lattice/diamond/1.1/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 11/1/2010 15:35:44 + Fast Program + + + + 4 + Lattice + ispPAC Power Manager II + ispPAC-POWR1014A + 0x00145043 + 48-pin TQFP + ispPAC-POWR1014A-XXT48 + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + TMS LOW; + TCK LOW; + TDI LOW; + TDO LOW; + CableEN HIGH; + + + + EzUSB-0 + + diff --git a/hub2_single.xcf b/hub2_single.xcf new file mode 100644 index 0000000..df2981a --- /dev/null +++ b/hub2_single.xcf @@ -0,0 +1,111 @@ + + + + + + JTAG + + 1 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /d/jspc22/trb/cvs/hub2/workdir/hub2_fpga1.bit + /root/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 4/8/2011 14:28:42 + Fast Program + + + + 2 + Lattice + LatticeECP2M + LFE2M100E + 0x0127d043 + All + LFE2M100E + + 8 + 11111111 + 1 + 0 + + /local/trb/cvs/hub2/workdir/hub2_fpga2_06_28.bit + /u/hadaq/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk + 6/28/2010 13:50:15 + Fast Program + + + + 3 + Lattice + ispPAC Power Manager II + ispPAC-POWR1014A + 0x00145043 + 48-pin TQFP + ispPAC-POWR1014A-XXT48 + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + TMS LOW; + TCK LOW; + TDI LOW; + TDO LOW; + CableEN HIGH; + + + + EzUSB-0 + + diff --git a/version.vhd b/version.vhd new file mode 100644 index 0000000..a9ba145 --- /dev/null +++ b/version.vhd @@ -0,0 +1,13 @@ + +--## attention, automatically generated. Don't change by hand. +library ieee; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use ieee.numeric_std.all; + +package version is + + constant VERSION_NUMBER_TIME : integer := 1408355122; + +end package version; diff --git a/workdir/serdes_gbe_0.txt b/workdir/serdes_gbe_0.txt new file mode 120000 index 0000000..a7c68f9 --- /dev/null +++ b/workdir/serdes_gbe_0.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.txt \ No newline at end of file diff --git a/workdir/serdes_gbe_0_200.txt b/workdir/serdes_gbe_0_200.txt new file mode 120000 index 0000000..c5d7304 --- /dev/null +++ b/workdir/serdes_gbe_0_200.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200.txt \ No newline at end of file diff --git a/workdir/serdes_gbe_0_200_ext.txt b/workdir/serdes_gbe_0_200_ext.txt new file mode 120000 index 0000000..4dbc3ac --- /dev/null +++ b/workdir/serdes_gbe_0_200_ext.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_200_ext.txt \ No newline at end of file diff --git a/workdir/serdes_gbe_0_extclock.txt b/workdir/serdes_gbe_0_extclock.txt new file mode 120000 index 0000000..50a3f8e --- /dev/null +++ b/workdir/serdes_gbe_0_extclock.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0_extclock.txt \ No newline at end of file diff --git a/workdir/serdes_gbe_all.txt b/workdir/serdes_gbe_all.txt new file mode 120000 index 0000000..1b14d05 --- /dev/null +++ b/workdir/serdes_gbe_all.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_0.txt b/workdir/serdes_sfp_0.txt new file mode 120000 index 0000000..d1901e5 --- /dev/null +++ b/workdir/serdes_sfp_0.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_0.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_0_extclock.txt b/workdir/serdes_sfp_0_extclock.txt new file mode 120000 index 0000000..5962d57 --- /dev/null +++ b/workdir/serdes_sfp_0_extclock.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_1.txt b/workdir/serdes_sfp_1.txt new file mode 120000 index 0000000..62988a3 --- /dev/null +++ b/workdir/serdes_sfp_1.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_1.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_2.txt b/workdir/serdes_sfp_2.txt new file mode 120000 index 0000000..b7333f6 --- /dev/null +++ b/workdir/serdes_sfp_2.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_2.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_3.txt b/workdir/serdes_sfp_3.txt new file mode 120000 index 0000000..fef76c8 --- /dev/null +++ b/workdir/serdes_sfp_3.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_3.txt \ No newline at end of file diff --git a/workdir/serdes_sfp_full_quad.txt b/workdir/serdes_sfp_full_quad.txt new file mode 120000 index 0000000..74da57a --- /dev/null +++ b/workdir/serdes_sfp_full_quad.txt @@ -0,0 +1 @@ +../../trbnet/media_interfaces/ecp2m_sfp/serdes_sfp_full_quad.txt \ No newline at end of file -- 2.43.0