From 61fd5571777b865fe3186c49913f081407265c2d Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 22 Jul 2024 08:48:40 +0200 Subject: [PATCH 01/16] few updates during ADC development --- adc/config_compile_frankfurt.pl | 2 +- adc/par.p2t | 2 +- adc/source/adc_18bit_input.vhd | 108 +++++++++++++++++++++++++++++--- adc/source/adc_addon.vhd | 50 +++++++++++++-- adc/trb5sc_adc.prj | 4 ++ adc/trb5sc_adc.vhd | 8 +++ pinout/trb5sc_adc.lpf | 3 +- 7 files changed, 161 insertions(+), 16 deletions(-) diff --git a/adc/config_compile_frankfurt.pl b/adc/config_compile_frankfurt.pl index 35b89c8..1494d39 100644 --- a/adc/config_compile_frankfurt.pl +++ b/adc/config_compile_frankfurt.pl @@ -6,7 +6,7 @@ Speedgrade => '8', TOPNAME => "trb5sc_adc", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; -lm_license_file_for_par => "1702\@jspc29", +lm_license_file_for_par => "1710\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', diff --git a/adc/par.p2t b/adc/par.p2t index e168739..127bff4 100644 --- a/adc/par.p2t +++ b/adc/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 11 +-t 13 -c 2 -e 2 -i 10 diff --git a/adc/source/adc_18bit_input.vhd b/adc/source/adc_18bit_input.vhd index 3c0ad82..2567710 100644 --- a/adc/source/adc_18bit_input.vhd +++ b/adc/source/adc_18bit_input.vhd @@ -16,7 +16,8 @@ entity adc_18bit_input is CLK_ADCRAW : in std_logic; --200 MHz ADC_DATA : in std_logic_vector(1 downto 0); - SHIFT_ALIGN_IN : in std_logic; + CONF_ALIGN_EN : in std_logic; + CONF_DATA_SHIFTED : in std_logic; DEL_CFLAG : out std_logic; DEL_DIRECTION : in std_logic; DEL_LOADN : in std_logic; @@ -27,7 +28,7 @@ entity adc_18bit_input is DATA_OUT : out std_logic_vector(17 downto 0); DATA_VALID_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(63 downto 0) ); end entity; @@ -36,14 +37,23 @@ architecture arch of adc_18bit_input is signal data_in : std_logic_vector(3 downto 0); signal clock_enable : std_logic; +signal data_shifted : std_logic; +signal cycle_counter : integer range 0 to 30; +signal cycle_input : integer range 0 to 13; -signal cycle_counter : integer range 0 to 12; +signal data_reg : std_logic_vector(27 downto 0); +signal data_reg_save : std_logic_vector(27 downto 0); +signal clock_reg : std_logic_vector(27 downto 0); +signal clock_reg_save : std_logic_vector(27 downto 0); +constant TESTPATTERN : std_logic_vector(17 downto 0) := 18x"281FC"; + +signal start_timer : unsigned(23 downto 0) := (others => '0'); begin -THE_INPUT : adc_1ch_inp +THE_INPUT : entity work.adc_1ch_inp port map ( clkin => CLK_ADCRAW, data_cflag => DEL_CFLAG, @@ -55,15 +65,99 @@ THE_INPUT : adc_1ch_inp ); -THE_CLOCK_OUT : adc_1ch_clk +THE_CLOCK_OUT : entity work.adc_1ch_clk port map( refclk => CLK_ADCRAW, reset => '0', data => '0' & clock_enable, - dout => ADC_CLK_OUT + dout(0) => ADC_CLK_OUT ); + + +PROC_START : process begin + wait until rising_edge(CLK_ADCRAW); + if RESET_ADC = '1' then + start_timer <= (others => '0'); + elsif start_timer(start_timer'left) = '0' then + start_timer <= start_timer + 1; + end if; +end process; + +PROC_CONTROL : process begin + wait until rising_edge(CLK_ADCRAW); + + if start_timer(start_timer'left) = '1' then + if cycle_counter = 30 then + cycle_counter <= 0; + else + cycle_counter <= cycle_counter + 1; + end if; + + if cycle_counter = 10 then + clock_enable <= '1'; + elsif cycle_counter = 19 then + clock_enable <= '0'; + end if; + + if cycle_counter = 0 or cycle_counter = 1 then + ADC_CNV_OUT <= '1'; + else + ADC_CNV_OUT <= '0'; + end if; + end if; +end process; - +PROC_INPUT : process begin + wait until rising_edge(CLK_ADCRAW); + data_reg <= data_reg(25 downto 0) & data_in(1 downto 0); + clock_reg <= clock_reg(25 downto 0) & data_in(3 downto 2); + + + if cycle_input = 13 then + cycle_input <= 0; + else + cycle_input <= cycle_input + 1; + end if; + + + if CONF_ALIGN_EN = '1' and data_reg(17 downto 0) = TESTPATTERN then + cycle_input <= 1; + data_shifted <= CONF_data_shifted; + elsif CONF_ALIGN_EN = '1' and data_reg(18 downto 1) = TESTPATTERN then + cycle_input <= 1; + data_shifted <= not CONF_data_shifted; + end if; + + if data_in(3 downto 2) = "00" and cycle_input = 0 then + cycle_input <= 0; + end if; + + + if cycle_input = 10 then + data_reg_save <= data_reg; + clock_reg_save <= clock_reg; + + if data_shifted = '0' then + DATA_OUT <= data_reg(17 downto 0); + DATA_VALID_OUT <= '1'; + else + DATA_OUT <= data_reg(18 downto 1); + DATA_VALID_OUT <= '1'; + end if; + end if; + if cycle_input = 11 then + DATA_VALID_OUT <= '0'; + end if; + + + +end process; + +DEBUG_OUT(27 downto 0) <= data_reg_save; +DEBUG_OUT(28) <= data_shifted; +DEBUG_OUT(59 downto 32) <= clock_reg_save; + + end architecture; diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd index 12c59f9..656fed9 100644 --- a/adc/source/adc_addon.vhd +++ b/adc/source/adc_addon.vhd @@ -13,6 +13,7 @@ entity adc_addon is ); port( CLK : in std_logic; -- 100 MHz + CLK_ADCBRAW : in std_logic; -- 200 MHz CLK_ADCRAW : in std_logic; -- 350 MHz RESET : in std_logic; @@ -46,6 +47,10 @@ architecture arch of adc_addon is signal data_valid_a : std_logic; signal debug_a : std_logic_vector(31 downto 0); + signal data_in_b : std_logic_vector(17 downto 0); + signal data_valid_b : std_logic; + signal debug_b : std_logic_vector(63 downto 0); + type adc_data_arr is array(0 to 4) of std_logic_vector(17 downto 0); signal data_processor_in : adc_data_arr; signal data_processor_valid: std_logic_vector(4 downto 0); @@ -64,7 +69,10 @@ architecture arch of adc_addon is -- alias CONF_baseline_always_on : std_logic is basic_control(1); alias CONF_del_direction : std_logic is basic_control(2); alias CONF_del_loadn : std_logic is basic_control(3); - + alias CONF_alignen_b : std_logic is basic_control(16); + alias CONF_testpat_b : std_logic is basic_control(17); + alias CONF_data_shifted_b : std_logic is basic_control(18); + signal CONF_input_select : std_logic_vector(31 downto 0) := x"21043210"; type config_arr_t is array(0 to ACTIVE_CHANNELS-1) of cfg_t; @@ -114,6 +122,32 @@ THE_INPUT_A : entity work.adc_input DEBUG_OUT => debug_a ); +THE_INPUT_B : entity work.adc_18bit_input + port map( + CLK => CLK, + RESET => RESET, + RESET_ADC => STROBE_reset_b, + + CLK_ADCRAW => CLK_ADCBRAW, + ADC_DATA => DCO_B & DATA_B, + + CONF_ALIGN_EN => CONF_alignen_b, + CONF_DATA_SHIFTED => CONF_data_shifted_b, + DEL_CFLAG => open, + DEL_DIRECTION => CONF_del_direction, + DEL_LOADN => CONF_del_loadn, + DEL_MOVE => STROBE_del_move_b, + + + ADC_CLK_OUT => CLK_B, + ADC_CNV_OUT => CNV_B, + + DATA_OUT => data_in_b, + DATA_VALID_OUT => data_valid_b, + DEBUG_OUT => debug_b + ); + +TESTPAT_B <= CONF_testpat_b; ------------------------------------------------------------------------------- -- ADC Input Multiplexer @@ -130,7 +164,8 @@ gen_inputs : for i in 0 to ACTIVE_CHANNELS-1 generate data_processor_valid(i) <= data_valid_a; when x"3" => data_processor_in(i) <= x"0" & data_in_a((3+1)*14-1 downto 3*14); data_processor_valid(i) <= data_valid_a; - --case x"4" => data_processor_in <= data_in_b; + when x"4" => data_processor_in(i) <= data_in_b; + data_processor_valid(i) <= data_valid_b; end case; end process; @@ -157,9 +192,9 @@ gen_processors : for i in 0 to ACTIVE_CHANNELS-1 generate CONTROL => basic_control(15 downto 0), CONFIG => config(i), - PSA_DATA => psa_data, - PSA_ADDR => psa_addr, - PSA_WRITE => psa_write(i), + PSA_DATA => psa_data, + PSA_ADDR => psa_addr, + PSA_WRITE => psa_write(i), PROC_REG_ADDR => proc_reg_addr, PROC_REG_READ => proc_reg_read(i), @@ -285,7 +320,10 @@ begin when x"11" => BUS_TX.data(13 downto 0) <= data_in_a(27 downto 14); when x"12" => BUS_TX.data(13 downto 0) <= data_in_a(41 downto 28); when x"13" => BUS_TX.data(13 downto 0) <= data_in_a(55 downto 42); - when x"14" => BUS_TX.data <= debug_a; + when x"14" => BUS_TX.data(17 downto 0) <= data_in_b; + when x"18" => BUS_TX.data <= debug_a; + when x"19" => BUS_TX.data <= debug_b(31 downto 0); + when x"1a" => BUS_TX.data <= debug_b(63 downto 32); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr(11 downto 10) = "00" then --1,2,3 diff --git a/adc/trb5sc_adc.prj b/adc/trb5sc_adc.prj index 40df45b..88cb772 100644 --- a/adc/trb5sc_adc.prj +++ b/adc/trb5sc_adc.prj @@ -266,8 +266,12 @@ add_file -vhdl -lib work "./source/adc_package.vhd" add_file -vhdl -lib work "./cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd" add_file -vhdl -lib work "./cores/mulaccsub3/mulaccsub3.vhd" add_file -vhdl -lib work "./cores/adc_pll/adc_pll.vhd" +add_file -vhdl -lib work "./cores/adc_1ch_clk/adc_1ch_clk.vhd" +add_file -vhdl -lib work "./cores/adc_1ch/adc_1ch_edited.vhd" + add_file -vhdl -lib work "./cores/input_4ch/input_4ch_edited.vhd" add_file -vhdl -lib work "./source/adc_input.vhd" +add_file -vhdl -lib work "./source/adc_18bit_input.vhd" add_file -vhdl -lib work "./source/adc_processor.vhd" add_file -vhdl -lib work "./source/adc_addon.vhd" diff --git a/adc/trb5sc_adc.vhd b/adc/trb5sc_adc.vhd index 16f5b48..70d5e58 100644 --- a/adc/trb5sc_adc.vhd +++ b/adc/trb5sc_adc.vhd @@ -45,6 +45,7 @@ entity trb5sc_adc is TESTPAT_B : out std_logic; DCO_B : in std_logic; DATA_B : in std_logic; + CNV_B : out std_logic; LEMO_OUT : out std_logic_vector(1 downto 0); LEMO_OE : out std_logic_vector(1 downto 0); @@ -396,6 +397,7 @@ begin ) port map( CLK => clk_sys, + CLK_ADCBRAW => clk_full_osc, CLK_ADCRAW => clk_350, RESET => reset_i, @@ -403,6 +405,12 @@ begin DATA_A => DATA_A, DCO_A => DCO_A, + DCO_B => DCO_B, + DATA_B => DATA_B, + CLK_B => CLK_B, + CNV_B => CNV_B, + TESTPAT_B => TESTPAT_B, + TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), READOUT_RX => readout_rx, READOUT_TX => readout_tx, diff --git a/pinout/trb5sc_adc.lpf b/pinout/trb5sc_adc.lpf index 800f5a1..8604ad4 100644 --- a/pinout/trb5sc_adc.lpf +++ b/pinout/trb5sc_adc.lpf @@ -127,7 +127,7 @@ LOCATE COMP "DCO_A" SITE "B32" ; #"FE_DIFF[18]" LOCATE COMP "DATA_A_1" SITE "D30" ; #"FE_DIFF[19]" LOCATE COMP "DATA_A_3" SITE "F30" ; #"FE_DIFF[20]" LOCATE COMP "DATA_A_2" SITE "C32" ; #"FE_DIFF[21]" -# LOCATE COMP "" SITE "F31" ; #"FE_DIFF[22]" +# LOCATE COMP "CLK_A" SITE "F31" ; #"FE_DIFF[22]" # LOCATE COMP "" SITE "F32" ; #"FE_DIFF[23]" # LOCATE COMP "" SITE "H31" ; #"FE_DIFF[24]" # LOCATE COMP "" SITE "J30" ; #"FE_DIFF[25]" @@ -207,6 +207,7 @@ IOBUF PORT "DATA_A_1" IO_TYPE=LVDS DIFFRESISTOR=100 ; IOBUF PORT "DATA_A_2" IO_TYPE=LVDS DIFFRESISTOR=100 ; IOBUF PORT "DATA_A_3" IO_TYPE=LVDS DIFFRESISTOR=100 ; IOBUF PORT "DATA_B" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "DCO_B" IO_TYPE=LVDS DIFFRESISTOR=100 ; IOBUF PORT "CLK_A" IO_TYPE=LVDS ; IOBUF PORT "CLK_B" IO_TYPE=LVDS ; IOBUF PORT "CNV_B" IO_TYPE=LVDS ; -- 2.51.0 From e73e0cfe433f74975717de34ac11d353e67bc1e4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 22 Jul 2024 08:48:56 +0200 Subject: [PATCH 02/16] first files for CTS port --- cts/compile.pl | 1 + cts/config.vhd | 122 ++++++++++ cts/config_compile_frankfurt.pl | 25 ++ cts/par.p2t | 69 ++++++ cts/trb5sc_cts.lpf | 47 ++++ cts/trb5sc_cts.prj | 293 ++++++++++++++++++++++ cts/trb5sc_cts.vhd | 416 ++++++++++++++++++++++++++++++++ 7 files changed, 973 insertions(+) create mode 120000 cts/compile.pl create mode 100644 cts/config.vhd create mode 100644 cts/config_compile_frankfurt.pl create mode 100644 cts/par.p2t create mode 100644 cts/trb5sc_cts.lpf create mode 100644 cts/trb5sc_cts.prj create mode 100644 cts/trb5sc_cts.vhd diff --git a/cts/compile.pl b/cts/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/cts/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/cts/config.vhd b/cts/config.vhd new file mode 100644 index 0000000..9df133e --- /dev/null +++ b/cts/config.vhd @@ -0,0 +1,122 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_NO; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F586"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 16; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 16; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000200"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/cts/config_compile_frankfurt.pl b/cts/config_compile_frankfurt.pl new file mode 100644 index 0000000..1494d39 --- /dev/null +++ b/cts/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_adc", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_adc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/cts/par.p2t b/cts/par.p2t new file mode 100644 index 0000000..127bff4 --- /dev/null +++ b/cts/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 13 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/cts/trb5sc_cts.lpf b/cts/trb5sc_cts.lpf new file mode 100644 index 0000000..41e91a5 --- /dev/null +++ b/cts/trb5sc_cts.lpf @@ -0,0 +1,47 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + +FREQUENCY NET "THE_ADDON/THE_INPUT_A/clk_data" 175.000000 MHz ; +FREQUENCY NET "CLK_A_c" 350.000000 MHz ; + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK PATH FROM CELL "THE_ADDON/basic_control_strobe*"; +BLOCK PATH FROM CELL "THE_ADDON/config*"; +BLOCK PATH FROM CLKNET "clk_sys" TO CLKNET "THE_ADDON/THE_INPUT_A/clk_data"; +BLOCK PATH FROM CLKNET "THE_ADDON/THE_INPUT_A/clk_data" TO CLKNET "clk_sys"; + diff --git a/cts/trb5sc_cts.prj b/cts/trb5sc_cts.prj new file mode 100644 index 0000000..e3099ed --- /dev/null +++ b/cts/trb5sc_cts.prj @@ -0,0 +1,293 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_cts" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_cts.edf" +set_option log_file "workdir/trb5sc_cts.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" + + + +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + + + +add_file -vhdl -lib work "./trb5sc_cts.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/cts/trb5sc_cts.vhd b/cts/trb5sc_cts.vhd new file mode 100644 index 0000000..03fc609 --- /dev/null +++ b/cts/trb5sc_cts.vhd @@ -0,0 +1,416 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_cts is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of trb5sc_adc is + + constant ACTIVE_CHANNELS : integer := 5; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); + + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal gbe_status : std_logic_vector(15 downto 0); + signal adc_trigger_i : std_logic_vector(11 downto 0); + + signal clk_350, clk_50, clk_200bypass : std_logic; + + +begin + + trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + THE_ADC_PLL : entity work.adc_pll + port map( + CLKI => clk_full_osc, + CLKOP => clk_350, + CLKOS => clk_50, + CLKOS2 => open + ); + + CLK_A <= clk_50; + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + USE_NEW_ECP5_RESET => 1, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer, + STATUS_GBE_OUT=> gbe_status + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busadc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busadc_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + -- HEADER_IO(7) => HDR_IO(6), + -- HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS(11 downto 0) => adc_trigger_i, + MONITOR_INPUTS(15 downto 12) => x"0", + TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i, + TRIG_GEN_INPUTS(15 downto 12) => x"0", + + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + + SCLK_A <= spi_clk(0); + CSB_A <= spi_cs(0); + SDIO_A <= spi_mosi(0); + spi_miso(0) <= SDIO_A when rising_edge(clk_sys); + + +--------------------------------------------------------------------------- +-- ADC ADDON +--------------------------------------------------------------------------- + THE_ADDON : entity work.adc_addon + generic map( + ACTIVE_CHANNELS => ACTIVE_CHANNELS + ) + port map( + CLK => clk_sys, + CLK_ADCBRAW => clk_full_osc, + CLK_ADCRAW => clk_350, + RESET => reset_i, + + FCO_A => FCO_A, + DATA_A => DATA_A, + DCO_A => DCO_A, + + DCO_B => DCO_B, + DATA_B => DATA_B, + CLK_B => CLK_B, + CNV_B => CNV_B, + TESTPAT_B => TESTPAT_B, + + TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + BUS_RX => busadc_rx, + BUS_TX => busadc_tx + + ); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + + + + +end architecture; -- 2.51.0 From d0f8c78db390785ed2e1e29712ad6f7de8d14783 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 22 Jul 2024 08:49:08 +0200 Subject: [PATCH 03/16] correct Hardware ID in Mimosis --- mimosis/config.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mimosis/config.vhd b/mimosis/config.vhd index cd1c9d3..e52ba3a 100644 --- a/mimosis/config.vhd +++ b/mimosis/config.vhd @@ -71,7 +71,7 @@ package config is ------------------------------------------------------------------------------ type intlist_t is array(0 to 7) of integer; type hw_info_t is array(0 to 7) of unsigned(31 downto 0); - constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000100"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); -- 2.51.0 From ace46386d566b6e020783ab2459cc4b94876a2d0 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 22 Jul 2024 08:49:56 +0200 Subject: [PATCH 04/16] update template project --- template/config_compile_frankfurt.pl | 2 +- template/trb5sc_template.prj | 2 ++ template/trb5sc_template.vhd | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index 6c1aa49..c29ab11 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -8,7 +8,7 @@ TOPNAME => "trb5sc_template", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', -synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', +synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'trb5sc_tdc', diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj index ad43138..07b06ab 100644 --- a/template/trb5sc_template.prj +++ b/template/trb5sc_template.prj @@ -127,6 +127,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd index 9256c3f..5835109 100644 --- a/template/trb5sc_template.vhd +++ b/template/trb5sc_template.vhd @@ -67,7 +67,7 @@ entity trb5sc_template is --Other Connectors TEST : inout std_logic_vector(14 downto 1); - HDR_IO : inout std_logic_vector(15 downto 0) + HDR_IO : inout std_logic_vector(23 downto 0) ); @@ -130,7 +130,7 @@ architecture arch of trb5sc_template is signal link_stat_in_reg : std_logic; - + signal header_i : std_logic_vector(10 downto 1); begin @@ -175,7 +175,7 @@ THE_CAL_PLL : entity work.pll_in125_out50 THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync generic map( SERDES_NUM => 0, - USE_NEW_ECP5_RESET => 0, + USE_NEW_ECP5_RESET => 1, IS_SYNC_SLAVE => c_YES ) port map( @@ -386,7 +386,7 @@ THE_CAL_PLL : entity work.pll_in125_out50 assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error; - HDR_IO(15 downto 10) <= (others => '0'); + HDR_IO(23 downto 10) <= (others => '0'); TEST(13 downto 1) <= (others => '0'); TEST(14) <= flash_ncs_i; FLASH_NCS <= flash_ncs_i; -- 2.51.0 From 9545c34b2fe6eef0e98e1b11fa050f0a70227589 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Sun, 4 Aug 2024 15:13:56 +0200 Subject: [PATCH 05/16] code changes towards Trb5sc based CTS --- cts/config.vhd | 54 ++++- cts/trb5sc_cts.vhd | 561 +++++++++++++++++++++++++++++++++++---------- 2 files changed, 493 insertions(+), 122 deletions(-) diff --git a/cts/config.vhd b/cts/config.vhd index 9df133e..66fde17 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -37,7 +37,7 @@ package config is constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 - constant USE_GBE : integer := c_NO; + constant USE_GBE : integer := c_YES; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -62,15 +62,44 @@ package config is constant TRIG_GEN_OUTPUT_NUM : integer := 4; constant MONITOR_INPUT_NUM : integer := 16; + + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 1; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 0; + constant TRIGGER_ADDON_COUNT : integer := 2; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 12; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - type intlist_t is array(0 to 7) of integer; - type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant cts_rdo_additional_ports : integer := '1'; --for internal endpoint + + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000200"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); @@ -92,6 +121,23 @@ package body config is constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + + function generateIncludedFeatures return std_logic_vector is variable t : std_logic_vector(63 downto 0); begin @@ -104,7 +150,7 @@ function generateIncludedFeatures return std_logic_vector is -- t(15) := '1'; --TDC -- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); - t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(0,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/cts/trb5sc_cts.vhd b/cts/trb5sc_cts.vhd index 03fc609..c7e1b96 100644 --- a/cts/trb5sc_cts.vhd +++ b/cts/trb5sc_cts.vhd @@ -23,7 +23,32 @@ entity trb5sc_cts is SFP_LOS : in std_logic; SFP_MOD_0 : in std_logic; - + --ADC AddOn + GPIO : inout std_logic_vector(5 downto 0); + + ADDON_LED : out std_logic_vector(7 downto 1); + ADDON_LED_RJ : out std_logic_vector(1 downto 0); + + SCLK_A : out std_logic; + CSB_A : out std_logic; + SDIO_A : inout std_logic; + FCO_A : in std_logic; + DATA_A : in std_logic_vector(3 downto 0); + DCO_A : in std_logic; + CLK_A : out std_logic; + + CLK_B : out std_logic; + TESTPAT_B : out std_logic; + DCO_B : in std_logic; + DATA_B : in std_logic; + CNV_B : out std_logic; + + LEMO_OUT : out std_logic_vector(1 downto 0); + LEMO_OE : out std_logic_vector(1 downto 0); + LEMO_TTL : in std_logic_vector(1 downto 0); + LEMO_NIM : in std_logic_vector(1 downto 0); + ADDON_RJ : in std_logic_vector(3 downto 0); + --ADC ADC_SCLK : out std_logic; ADC_NCS : out std_logic; @@ -65,7 +90,7 @@ entity trb5sc_cts is end entity; -architecture arch of trb5sc_adc is +architecture arch of trb5sc_cts is constant ACTIVE_CHANNELS : integer := 5; @@ -95,8 +120,8 @@ architecture arch of trb5sc_adc is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX; - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, buscts_rx, bustc_tx, busgbeip_rx, busgbereg_rx, bus_master_in, busadc_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_tx, bustc_rx, busgbeip_tx, busgbereg_tx, bus_master_out, busadc_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -105,6 +130,8 @@ architecture arch of trb5sc_adc is signal clock_select : std_logic; signal bus_master_active : std_logic; signal flash_ncs_i : std_logic; + signal rdack, wrack : std_logic; + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); signal header_io_i : std_logic_vector(10 downto 1); @@ -117,10 +144,75 @@ architecture arch of trb5sc_adc is signal clk_350, clk_50, clk_200bypass : std_logic; - + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + signal cts_monitor_out : std_logic_vector(1 downto 0); + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + -- signal cts_ext_trigger : std_logic; + -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + -- signal cts_ext_control : std_logic_vector(31 downto 0); + -- signal cts_ext_debug : std_logic_vector(31 downto 0); + -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0); + + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + begin - trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); --------------------------------------------------------------------------- -- Clock & Reset Handling @@ -128,8 +220,8 @@ begin THE_CLOCK_RESET : entity work.clock_reset_handler port map( CLOCK_IN => CLK_200, - RESET_FROM_NET => med2int(0).stat_op(13), - SEND_RESET_IN => med2int(0).stat_op(15), + RESET_FROM_NET => '0',--med2int(0).stat_op(13), + SEND_RESET_IN => '0', --med2int(0).stat_op(15), BUS_RX => bustc_rx, BUS_TX => bustc_tx, @@ -144,6 +236,9 @@ begin DEBUG_OUT => debug_clock_reset ); + + + THE_ADC_PLL : entity work.adc_pll port map( @@ -152,123 +247,339 @@ begin CLKOS => clk_50, CLKOS2 => open ); - - CLK_A <= clk_50; - + + CLK_A <= clk_50; --------------------------------------------------------------------------- --- TrbNet Uplink +-- GbE --------------------------------------------------------------------------- - - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + GBE : entity work.gbe_wrapper generic map( - SERDES_NUM => 0, - USE_NEW_ECP5_RESET => 1, - IS_SYNC_SLAVE => c_YES + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + -- LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" ) + port map( - CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_SUPPL_PCLK, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + STATUS_OUT => status, --open, + DEBUG_OUT => open ); - gen_sfp_con : if SERDES_NUM = 1 generate - sfp_los_i <= SFP_LOS; - sfp_prsnt_i <= SFP_MOD_0; - SFP_TX_DIS <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; - - --------------------------------------------------------------------------- --- Endpoint +-- Hub --------------------------------------------------------------------------- - THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => BROADCAST_BITMASK, - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_USE_1WIRE_INTERFACE => c_I2C, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS, - DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16, - USE_GBE => USE_GBE + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_YES, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_125 => CLK_125, - CLEAR_N => GSR_N, - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => open, + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_IN => open, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, BUS_MASTER_IN => bus_master_in, BUS_MASTER_OUT => bus_master_out, BUS_MASTER_ACTIVE => bus_master_active, - - ONEWIRE_INOUT => open, - I2C_SCL => I2C_SCL, - I2C_SDA => I2C_SDA, - --Timing registers - TIMERS_OUT => timer, - STATUS_GBE_OUT=> gbe_status + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') ); + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 6, --TRB5sc + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (12, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => '0', + EXT_STATUS_IN => (others => '0'), + EXT_CONTROL_OUT => open, + EXT_HEADER_BITS_IN => (others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + cts_addon_triggers_in(12 downto 4) <= HDR_IO(23 downto 16); + cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 11, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -282,10 +593,17 @@ begin BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busadc_rx, + BUS_RX(4) => busgbeip_rx, + BUS_RX(5) => busgbereg_rx, + BUS_RX(6) => buscts_rx, + BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busadc_tx, + BUS_TX(4) => busgbeip_tx, + BUS_TX(5) => busgbereg_tx, + BUS_TX(6) => buscts_tx, STAT_DEBUG => open ); @@ -310,7 +628,7 @@ begin FLASH_IN => FLASH_MISO, FLASH_OUT => FLASH_MOSI, PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), + REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe, --SPI SPI_CS_OUT => spi_cs, SPI_MOSI_OUT => spi_mosi, @@ -332,8 +650,8 @@ begin TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i, TRIG_GEN_INPUTS(15 downto 12) => x"0", - TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), - TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i, + --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -357,10 +675,12 @@ begin SDIO_A <= spi_mosi(0); spi_miso(0) <= SDIO_A when rising_edge(clk_sys); - + + + --------------------------------------------------------------------------- -- ADC ADDON ---------------------------------------------------------------------------- +--------------------------------------------------------------------------- THE_ADDON : entity work.adc_addon generic map( ACTIVE_CHANNELS => ACTIVE_CHANNELS @@ -370,24 +690,24 @@ begin CLK_ADCBRAW => clk_full_osc, CLK_ADCRAW => clk_350, RESET => reset_i, - + FCO_A => FCO_A, DATA_A => DATA_A, DCO_A => DCO_A, - - DCO_B => DCO_B, - DATA_B => DATA_B, - CLK_B => CLK_B, - CNV_B => CNV_B, + + DCO_B => DCO_B, + DATA_B => DATA_B, + CLK_B => CLK_B, + CNV_B => CNV_B, TESTPAT_B => TESTPAT_B, - + TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), READOUT_RX => readout_rx, READOUT_TX => readout_tx, - + BUS_RX => busadc_rx, BUS_TX => busadc_tx - + ); @@ -410,7 +730,12 @@ begin FLASH_NCS <= flash_ncs_i; - +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +readout_tx(0).data_finished <= '1'; +readout_tx(0).data_write <= '0'; +readout_tx(0).busy_release <= '1'; end architecture; -- 2.51.0 From cfba441ebfd28f7e463354b039280159b5104db3 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 6 Aug 2024 13:27:38 +0200 Subject: [PATCH 06/16] first working standalone ADC design --- {cts => adc_standalone}/compile.pl | 0 {cts => adc_standalone}/config.vhd | 16 +- .../config_compile_frankfurt.pl | 6 +- {cts => adc_standalone}/par.p2t | 0 {cts => adc_standalone}/trb5sc_cts.lpf | 3 + {cts => adc_standalone}/trb5sc_cts.prj | 28 +++- {cts => adc_standalone}/trb5sc_cts.vhd | 156 ++++++++++-------- 7 files changed, 122 insertions(+), 87 deletions(-) rename {cts => adc_standalone}/compile.pl (100%) rename {cts => adc_standalone}/config.vhd (93%) rename {cts => adc_standalone}/config_compile_frankfurt.pl (79%) rename {cts => adc_standalone}/par.p2t (100%) rename {cts => adc_standalone}/trb5sc_cts.lpf (97%) rename {cts => adc_standalone}/trb5sc_cts.prj (91%) rename {cts => adc_standalone}/trb5sc_cts.vhd (87%) diff --git a/cts/compile.pl b/adc_standalone/compile.pl similarity index 100% rename from cts/compile.pl rename to adc_standalone/compile.pl diff --git a/cts/config.vhd b/adc_standalone/config.vhd similarity index 93% rename from cts/config.vhd rename to adc_standalone/config.vhd index 66fde17..f6137bb 100644 --- a/cts/config.vhd +++ b/adc_standalone/config.vhd @@ -2,6 +2,7 @@ library ieee; USE IEEE.std_logic_1164.ALL; use ieee.numeric_std.all; use work.trb_net_std.all; +use work.trb_net16_hub_func.all; package config is @@ -87,16 +88,21 @@ package config is --End of design configuration ------------------------------------------------------------------------------ - constant INTERFACE_NUM : integer; - constant IS_UPLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); - constant IS_DOWNLINK : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); - constant IS_UPLINK_ONLY : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + type hub_ct is array(0 to 16) of integer; + type intlist_t is array(0 to 7) of integer; + + + constant INTERFACE_NUM : integer := 1; + constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - constant cts_rdo_additional_ports : integer := '1'; --for internal endpoint + constant ADC_ACTIVE_CHANNELS : integer := 5; + constant cts_rdo_additional_ports : integer := ADC_ACTIVE_CHANNELS; --for internal endpoint diff --git a/cts/config_compile_frankfurt.pl b/adc_standalone/config_compile_frankfurt.pl similarity index 79% rename from cts/config_compile_frankfurt.pl rename to adc_standalone/config_compile_frankfurt.pl index 1494d39..eae6895 100644 --- a/cts/config_compile_frankfurt.pl +++ b/adc_standalone/config_compile_frankfurt.pl @@ -4,11 +4,11 @@ Package => 'CABGA756', Speedgrade => '8', -TOPNAME => "trb5sc_adc", +TOPNAME => "trb5sc_cts", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1710\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', -synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/', +synplify_path => '/d/jspc29/lattice/synplify/V-2023.09-SP1/',#T-2022.09-SP2/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'trb5sc_adc', @@ -17,7 +17,7 @@ par_options => '../par.p2t', #Include only necessary lpf files include_TDC => 0, -include_GBE => 0, +include_GBE => 1, #Report settings firefox_open => 0, diff --git a/cts/par.p2t b/adc_standalone/par.p2t similarity index 100% rename from cts/par.p2t rename to adc_standalone/par.p2t diff --git a/cts/trb5sc_cts.lpf b/adc_standalone/trb5sc_cts.lpf similarity index 97% rename from cts/trb5sc_cts.lpf rename to adc_standalone/trb5sc_cts.lpf index 41e91a5..fb85d6f 100644 --- a/cts/trb5sc_cts.lpf +++ b/adc_standalone/trb5sc_cts.lpf @@ -23,6 +23,9 @@ BLOCK PATH TO PORT "TEMP_LINE"; BLOCK PATH FROM PORT "TEMP_LINE"; BLOCK PATH TO PORT "TEST_LINE*"; +MULTICYCLE FROM CELL "THE_HUB/THE_HUB/reset_i" 15 ns; + + #MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; #MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; #MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; diff --git a/cts/trb5sc_cts.prj b/adc_standalone/trb5sc_cts.prj similarity index 91% rename from cts/trb5sc_cts.prj rename to adc_standalone/trb5sc_cts.prj index e3099ed..81fd75c 100644 --- a/cts/trb5sc_cts.prj +++ b/adc_standalone/trb5sc_cts.prj @@ -98,6 +98,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16 add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" #Flash & Reload, Tools @@ -132,8 +133,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" -# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" # add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" @@ -208,13 +209,12 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" #Hub -add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" @@ -232,7 +232,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_contro add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" @@ -241,7 +242,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.v add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" @@ -272,7 +274,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vh add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" - +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" @@ -284,6 +286,18 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" +add_file -vhdl -lib work "../adc/source/adc_package.vhd" +add_file -vhdl -lib work "../adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd" +add_file -vhdl -lib work "../adc/cores/mulaccsub3/mulaccsub3.vhd" +add_file -vhdl -lib work "../adc/cores/adc_pll/adc_pll.vhd" +add_file -vhdl -lib work "../adc/cores/adc_1ch_clk/adc_1ch_clk.vhd" +add_file -vhdl -lib work "../adc/cores/adc_1ch/adc_1ch_edited.vhd" +add_file -vhdl -lib work "../adc/cores/input_4ch/input_4ch_edited.vhd" +add_file -vhdl -lib work "../adc/source/adc_input.vhd" +add_file -vhdl -lib work "../adc/source/adc_18bit_input.vhd" +add_file -vhdl -lib work "../adc/source/adc_processor.vhd" +add_file -vhdl -lib work "../adc/source/adc_addon.vhd" + add_file -vhdl -lib work "./trb5sc_cts.vhd" diff --git a/cts/trb5sc_cts.vhd b/adc_standalone/trb5sc_cts.vhd similarity index 87% rename from cts/trb5sc_cts.vhd rename to adc_standalone/trb5sc_cts.vhd index c7e1b96..4712e1a 100644 --- a/cts/trb5sc_cts.vhd +++ b/adc_standalone/trb5sc_cts.vhd @@ -8,7 +8,11 @@ use work.config.all; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.med_sync_define.all; +-- use work.med_sync_define.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.cts_pkg.all; + entity trb5sc_cts is port( @@ -92,7 +96,7 @@ end entity; architecture arch of trb5sc_cts is - constant ACTIVE_CHANNELS : integer := 5; + -- constant ACTIVE_CHANNELS : integer := ADC_ACTIVE_CHANNELS; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -115,13 +119,14 @@ architecture arch of trb5sc_cts is signal int2med : int2med_array_t(0 to 0); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + signal reboot_from_gbe : std_logic; + signal reset_via_gbe : std_logic; + -- signal readout_rx : READOUT_RX; + -- signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1); - - signal ctrlbus_tx, bustools_tx, buscts_rx, bustc_tx, busgbeip_rx, busgbereg_rx, bus_master_in, busadc_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustools_rx, buscts_tx, bustc_rx, busgbeip_tx, busgbereg_tx, bus_master_out, busadc_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busadc_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busadc_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -148,7 +153,6 @@ architecture arch of trb5sc_cts is signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); signal trigger_busy_i : std_logic; signal cts_trigger_out : std_logic; - signal cts_monitor_out : std_logic_vector(1 downto 0); signal gbe_cts_number : std_logic_vector(15 downto 0); signal gbe_cts_code : std_logic_vector(7 downto 0); @@ -220,7 +224,7 @@ begin THE_CLOCK_RESET : entity work.clock_reset_handler port map( CLOCK_IN => CLK_200, - RESET_FROM_NET => '0',--med2int(0).stat_op(13), + RESET_FROM_NET => reset_via_gbe,--med2int(0).stat_op(13), SEND_RESET_IN => '0', --med2int(0).stat_op(15), BUS_RX => bustc_rx, @@ -274,20 +278,20 @@ begin LINK_HAS_READOUT => "0001", LINK_HAS_SLOWCTRL => "0001", LINK_HAS_DHCP => "0001", - -- LINK_HAS_ARP => "0001", + LINK_HAS_ARP => "0001", LINK_HAS_PING => "0001", LINK_HAS_FWD => "0000" ) port map( CLK_SYS_IN => clk_sys, - CLK_125_IN => CLK_SUPPL_PCLK, + CLK_125_IN => CLK_125, RESET => reset_i, GSR_N => GSR_N, TRIGGER_IN => cts_rdo_rx.data_valid, - SD_PRSNT_N_IN(0) => SFP_MOD0, + SD_PRSNT_N_IN(0) => SFP_MOD_0, SD_LOS_IN(0) => SFP_LOS, SD_TXDIS_OUT(0) => SFP_TX_DIS, @@ -330,7 +334,7 @@ begin BUS_REG_TX => busgbereg_tx, MAKE_RESET_OUT => reset_via_gbe, - STATUS_OUT => status, --open, + STATUS_OUT => gbe_status, --open, DEBUG_OUT => open ); @@ -349,7 +353,7 @@ begin INIT_ENDPOINT_ID => x"0001", BROADCAST_BITMASK => x"7E", CLOCK_FREQUENCY => 100, - USE_ONEWIRE => c_YES, + USE_ONEWIRE => c_I2C, BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, @@ -361,7 +365,7 @@ begin CLK => clk_sys, RESET => reset_i, CLK_EN => '1', - + -- Media interfacces --------------------------------------------------------------- MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, @@ -371,9 +375,10 @@ begin MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, - MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => open, - MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => (others => '0'), - + MED_STAT_OP(2 downto 0) => ERROR_NC, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 3) => (others => '0'), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => open, + -- Gbe Read-out Path --------------------------------------------------------------- --Event information coming from CTS for GbE GBE_CTS_NUMBER_OUT => gbe_cts_number, @@ -390,7 +395,7 @@ begin GBE_FEE_READ_IN => gbe_fee_read, GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, GBE_FEE_BUSY_OUT => gbe_fee_busy, - + -- CTS Request Sending ------------------------------------------------------------- --LVL1 trigger CTS_TRG_SEND_IN => cts_trg_send, @@ -409,7 +414,7 @@ begin -- Receiver port CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, CTS_IPU_BUSY_OUT => cts_ipu_busy, - + -- CTS Data Readout ---------------------------------------------------------------- --Trigger to CTS out RDO_TRIGGER_IN => cts_trigger_out, @@ -421,7 +426,7 @@ begin RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, - + --Data from CTS in RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, RDO_DATA_IN => cts_rdo_data, @@ -432,12 +437,14 @@ begin RDO_ADDITIONAL_DATA => cts_rdo_additional_data, RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, - + -- Slow Control -------------------------------------------------------------------- COMMON_STAT_REGS => open, COMMON_CTRL_REGS => common_ctrl_reg, - ONEWIRE => TEMPSENS, + ONEWIRE => open, ONEWIRE_MONITOR_IN => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, MY_ADDRESS_OUT => timer.network_address, UNIQUE_ID_OUT => timer.uid, BUS_MASTER_IN => bus_master_in, @@ -447,7 +454,7 @@ begin TIMER_TICKS_OUT(1) => timer.tick_ms, TEMPERATURE_OUT => timer.temperature, EXTERNAL_SEND_RESET => reset_via_gbe, - + REGIO_ADDR_OUT => ctrlbus_rx.addr, REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, @@ -458,7 +465,7 @@ begin REGIO_WRITE_ACK_IN => wrack, REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, - + --Gbe Sctrl Input GSC_INIT_DATAREADY_IN => gsc_init_dataready, GSC_INIT_DATA_IN => gsc_init_data, @@ -469,7 +476,7 @@ begin GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, GSC_REPLY_READ_IN => gsc_reply_read, GSC_BUSY_OUT => gsc_busy, - + --status and control ports HUB_STAT_CHANNEL => open, HUB_STAT_GEN => open, @@ -477,26 +484,26 @@ begin MPLEX_STAT => open, STAT_REGS => open, STAT_CTRL_REGS => open, - + --Fixed status and control ports STAT_DEBUG => open, CTRL_DEBUG => (others => '0') ); - - + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; - + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; - + end generate; - - + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; - + --------------------------------------------------------------------------- -- CTS @@ -504,32 +511,32 @@ begin THE_CTS : CTS generic map ( EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic - PLATTFORM => 6, --TRB5sc + PLATTFORM => 5, --TRB5sc OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, ADDON_GROUPS => 1, - ADDON_GROUP_UPPER => (12, others => 0) + ADDON_GROUP_UPPER => (11, others => 0) ) port map ( CLK => clk_sys, RESET => reset_i, - + TRIGGER_BUSY_OUT => trigger_busy_i, TIME_REFERENCE_OUT => cts_trigger_out, - + ADDON_TRIGGERS_IN => cts_addon_triggers_in, ADDON_GROUP_ACTIVITY_OUT => open, ADDON_GROUP_SELECTED_OUT => open, - + EXT_TRIGGER_IN => '0', EXT_STATUS_IN => (others => '0'), EXT_CONTROL_OUT => open, EXT_HEADER_BITS_IN => (others => '0'), EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), - + PERIPH_TRIGGER_IN => (others => '0'), - + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, - + CTS_TRG_SEND_OUT => cts_trg_send, CTS_TRG_TYPE_OUT => cts_trg_type, CTS_TRG_NUMBER_OUT => cts_trg_number, @@ -537,7 +544,7 @@ begin CTS_TRG_RND_CODE_OUT => cts_trg_code, CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, CTS_TRG_BUSY_IN => cts_trg_busy, - + CTS_IPU_SEND_OUT => cts_ipu_send, CTS_IPU_TYPE_OUT => cts_ipu_type, CTS_IPU_NUMBER_OUT => cts_ipu_number, @@ -545,7 +552,7 @@ begin CTS_IPU_RND_CODE_OUT => cts_ipu_code, CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, CTS_IPU_BUSY_IN => cts_ipu_busy, - + CTS_REGIO_ADDR_IN => buscts_rx.addr, CTS_REGIO_DATA_IN => buscts_rx.data, CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, @@ -554,21 +561,21 @@ begin CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, - + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, - + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, FEE_DATA_OUT => cts_rdo_data, FEE_DATA_WRITE_OUT => cts_rdo_write, FEE_DATA_FINISHED_OUT => cts_rdo_finished ); - - cts_addon_triggers_in(12 downto 4) <= HDR_IO(23 downto 16); + + cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16); cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; - + buscts_tx.nack <= '0'; buscts_tx.ack <= '0'; @@ -577,33 +584,33 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"a000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 11, others => 0), + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, others => 0), PORT_MASK_ENABLE => 1 ) port map( CLK => clk_sys, RESET => reset_i, - + REGIO_RX => ctrlbus_rx, REGIO_TX => ctrlbus_tx, - + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED - BUS_RX(1) => bussci_rx, --SCI Serdes + -- BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(1) => buscts_rx, BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busadc_rx, BUS_RX(4) => busgbeip_rx, BUS_RX(5) => busgbereg_rx, - BUS_RX(6) => buscts_rx, - + BUS_TX(0) => bustools_tx, - BUS_TX(1) => bussci_tx, + -- BUS_TX(1) => bussci_tx, + BUS_TX(1) => buscts_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busadc_tx, BUS_TX(4) => busgbeip_tx, BUS_TX(5) => busgbereg_tx, - BUS_TX(6) => buscts_tx, STAT_DEBUG => open ); @@ -616,7 +623,9 @@ begin ADC_CMD_2 => x"1d5cb", ADC_CMD_3 => x"1e3cb", ADC_CMD_4 => x"2f5cb", - ADC_CMD_T => x"1F393" + ADC_CMD_T => x"1F393", + NUM_COINCIDENCES => 4, + NUM_MULTIPLICITIES => 1 ) port map( CLK => clk_sys, @@ -683,7 +692,7 @@ begin --------------------------------------------------------------------------- THE_ADDON : entity work.adc_addon generic map( - ACTIVE_CHANNELS => ACTIVE_CHANNELS + ACTIVE_CHANNELS => ADC_ACTIVE_CHANNELS ) port map( CLK => clk_sys, @@ -701,9 +710,9 @@ begin CNV_B => CNV_B, TESTPAT_B => TESTPAT_B, - TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0), - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, + TRIGGER_OUT => adc_trigger_i(ADC_ACTIVE_CHANNELS-1 downto 0), + READOUT_RX => cts_rdo_rx, + READOUT_TX => cts_rdo_additional(0 to ADC_ACTIVE_CHANNELS-1), BUS_RX => busadc_rx, BUS_TX => busadc_tx @@ -714,15 +723,18 @@ begin --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- + LED_SFP_GREEN <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0'; + LED_SFP_YELLOW <= gbe_status(8); + LED_SFP_RED <= not (gbe_status(3) or gbe_status(4)); --'0'; - LED_SFP_GREEN <= not med2int(0).stat_op(9); - LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); - LED_SFP_YELLOW <= not med2int(0).stat_op(8); + -- LED_SFP_GREEN <= not med2int(0).stat_op(9); + -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); LED <= x"FF"; LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used - LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used - LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_RJ_RED(0) <= '1'; --on if backplane is used (next to SFP) LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used TEST(13 downto 1) <= (others => '0'); @@ -733,9 +745,9 @@ begin ------------------------------------------------------------------------------- -- No trigger/data endpoint included ------------------------------------------------------------------------------- -readout_tx(0).data_finished <= '1'; -readout_tx(0).data_write <= '0'; -readout_tx(0).busy_release <= '1'; +-- cts_rdo_additional(0).data_finished <= '1'; +-- cts_rdo_additional(0).data_write <= '0'; +-- cts_rdo_additional(0).busy_release <= '1'; end architecture; -- 2.51.0 From 8abfab09165d8a9e600eab413e9c5c7d29393e29 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 7 Aug 2024 16:21:04 +0200 Subject: [PATCH 07/16] few updates to ADC design, incl block memory --- adc/source/adc_addon.vhd | 5 +++- adc/source/adc_processor.vhd | 43 +++++++++++++++++++++++------------ adc_standalone/config.vhd | 6 +++++ adc_standalone/trb5sc_cts.prj | 1 + adc_standalone/trb5sc_cts.vhd | 19 +++++++++++++++- 5 files changed, 57 insertions(+), 17 deletions(-) diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd index 656fed9..9acd029 100644 --- a/adc/source/adc_addon.vhd +++ b/adc/source/adc_addon.vhd @@ -40,6 +40,7 @@ end entity; architecture arch of adc_addon is + attribute syn_ramstyle : string; @@ -82,7 +83,9 @@ architecture arch of adc_addon is signal baseline_reset_value : brv_arr_t := (others => (others => (others => '0'))); type config_mem_t is array(0 to 1023) of std_logic_vector(31 downto 0); - signal config_mem : config_mem_t; + signal config_mem : config_mem_t; + attribute syn_ramstyle of config_mem : signal is "block_ram"; + signal read_mem : std_logic; signal config_mem_out : std_logic_vector(31 downto 0); diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd index 44aab61..8e9aa53 100644 --- a/adc/source/adc_processor.vhd +++ b/adc/source/adc_processor.vhd @@ -51,11 +51,11 @@ attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_hier of arch : architecture is "hard"; -type ram_t is array (0 to 1023) of unsigned(23 downto 0); +type ram_t is array (0 to 1023) of std_logic_vector(23 downto 0); signal ram_write : std_logic := '0'; signal ram_read : std_logic := '0'; signal ram_data_in : unsigned(23 downto 0); -signal ram_data_out : unsigned(23 downto 0); +signal ram_data_out : std_logic_vector(23 downto 0); signal reg_ram_data_out : unsigned(23 downto 0); signal baseline : unsigned(19 downto 0); @@ -66,7 +66,7 @@ signal ram_rd_move_value : unsigned( 9 downto 0) := (others => '0'); signal ram_wr_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_rd_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_count : unsigned( 9 downto 0) := (others => '0'); -signal ram_clear : std_logic; +signal ram_clear : std_logic := '0'; signal last_ramread : std_logic; signal ram_valid : std_logic; signal ram_rd_move : std_logic; @@ -77,9 +77,7 @@ signal reg2_ram_remove : std_logic; signal trigger_gen : std_logic; signal stop_writing : std_logic; -signal ram : ram_t := (others => (others => '0')); -attribute syn_ramstyle of ram : signal is "block_ram"; - +-- signal ram : ram_t := (others => (others => '0')); signal after_trg_cnt : unsigned(11 downto 0) := (others => '1'); signal stop_writing_rdo : std_logic := '0'; @@ -115,6 +113,7 @@ signal psa_data_i : std_logic_vector(8 downto 0); signal psa_ram_out_t : std_logic_vector(8 downto 0); signal psa_ram_out : std_logic_vector(8 downto 0); signal psa_ram : psa_ram_t; +attribute syn_ramstyle of psa_ram : signal is "block_ram"; type psa_state_t is (PSA_IDLE, PSA_START_CHANNEL, PSA_WAIT_RAM, PSA_WAIT_RAM2, PSA_CALC, PSA_WAITWRITE, PSA_WAITWRITE2, PSA_DOWRITE, PSA_FINISH, PSA_WAIT_AFTER); type rdo_state_t is (RDO_IDLE, READ_CHANNEL, NEXT_BLOCK, RDO_DONE, RDO_FINISH, RDO_WAIT_AFTER); @@ -257,16 +256,30 @@ end process; end process; - + THE_RAM: entity work.ram_36x1k_oreg + port map ( + WrAddress => std_logic_vector(ram_wr_pointer), + RdAddress => std_logic_vector(ram_rd_pointer), + Data(23 downto 0) => std_logic_vector(ram_data_in), + WE => ram_write, + RdClock => CLK, + RdClockEn => '1', + Reset => '0', + WrClock => CLK, + WrClockEn => '1', + Q(23 downto 0) => ram_data_out + ); - PROC_RAM : process begin - wait until rising_edge(CLK); - if ram_write = '1' then - ram(to_integer(ram_wr_pointer)) <= ram_data_in; - end if; - ram_data_out <= ram(to_integer(ram_rd_pointer)); - reg_ram_data_out <= ram_data_out; - end process; + reg_ram_data_out <= unsigned(ram_data_out); + + -- PROC_RAM : process begin + -- wait until rising_edge(CLK); + -- if ram_write = '1' then + -- ram(to_integer(ram_wr_pointer)) <= std_logic_vector(ram_data_in); + -- end if; + -- ram_data_out <= unsigned(ram(to_integer(ram_rd_pointer))); + -- reg_ram_data_out <= ram_data_out; + -- end process; proc_buffer_write : process begin wait until rising_edge(CLK); diff --git a/adc_standalone/config.vhd b/adc_standalone/config.vhd index f6137bb..9c2ad45 100644 --- a/adc_standalone/config.vhd +++ b/adc_standalone/config.vhd @@ -96,6 +96,12 @@ package config is constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + -- constant INTERFACE_NUM : integer := 0; + -- constant IS_UPLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + -- constant IS_DOWNLINK : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + -- constant IS_UPLINK_ONLY : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + ------------------------------------------------------------------------------ diff --git a/adc_standalone/trb5sc_cts.prj b/adc_standalone/trb5sc_cts.prj index 81fd75c..a02061f 100644 --- a/adc_standalone/trb5sc_cts.prj +++ b/adc_standalone/trb5sc_cts.prj @@ -286,6 +286,7 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/ram_36x1k_oreg/ram_36x1k_oreg.vhd" add_file -vhdl -lib work "../adc/source/adc_package.vhd" add_file -vhdl -lib work "../adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd" add_file -vhdl -lib work "../adc/cores/mulaccsub3/mulaccsub3.vhd" diff --git a/adc_standalone/trb5sc_cts.vhd b/adc_standalone/trb5sc_cts.vhd index 4712e1a..fcd6f6c 100644 --- a/adc_standalone/trb5sc_cts.vhd +++ b/adc_standalone/trb5sc_cts.vhd @@ -213,6 +213,8 @@ architecture arch of trb5sc_cts is signal cts_ipu_status_bits : std_logic_vector(31 downto 0); signal cts_ipu_busy : std_logic; + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + begin @@ -224,7 +226,7 @@ begin THE_CLOCK_RESET : entity work.clock_reset_handler port map( CLOCK_IN => CLK_200, - RESET_FROM_NET => reset_via_gbe,--med2int(0).stat_op(13), + RESET_FROM_NET => make_reset,--med2int(0).stat_op(13), SEND_RESET_IN => '0', --med2int(0).stat_op(15), BUS_RX => bustc_rx, @@ -254,6 +256,21 @@ begin CLK_A <= clk_50; + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + --------------------------------------------------------------------------- -- GbE --------------------------------------------------------------------------- -- 2.51.0 From bb8e88c85810b83e33714b8ba54a77ede8081bfb Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 9 Aug 2024 14:20:13 +0200 Subject: [PATCH 08/16] copy of the mimosis project as standalone version --- mimosis_standalone/compile.pl | 1 + mimosis_standalone/config.vhd | 171 ++++ .../config_compile_frankfurt.pl | 25 + mimosis_standalone/par.p2t | 69 ++ mimosis_standalone/trb5sc_mimosis.lpf | 53 ++ mimosis_standalone/trb5sc_mimosis.prj | 302 ++++++ mimosis_standalone/trb5sc_mimosis.vhd | 875 ++++++++++++++++++ 7 files changed, 1496 insertions(+) create mode 120000 mimosis_standalone/compile.pl create mode 100644 mimosis_standalone/config.vhd create mode 100644 mimosis_standalone/config_compile_frankfurt.pl create mode 100644 mimosis_standalone/par.p2t create mode 100644 mimosis_standalone/trb5sc_mimosis.lpf create mode 100644 mimosis_standalone/trb5sc_mimosis.prj create mode 100644 mimosis_standalone/trb5sc_mimosis.vhd diff --git a/mimosis_standalone/compile.pl b/mimosis_standalone/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/mimosis_standalone/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/mimosis_standalone/config.vhd b/mimosis_standalone/config.vhd new file mode 100644 index 0000000..ea83682 --- /dev/null +++ b/mimosis_standalone/config.vhd @@ -0,0 +1,171 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_YES; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F586"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 16; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 16; + + + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 0; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 0; + constant TRIGGER_ADDON_COUNT : integer := 1; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type hub_ct is array(0 to 16) of integer; + type intlist_t is array(0 to 7) of integer; + + + constant INTERFACE_NUM : integer := 1; + constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + + constant cts_rdo_additional_ports : integer := 1; --for internal endpoint + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000100"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(0,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/mimosis_standalone/config_compile_frankfurt.pl b/mimosis_standalone/config_compile_frankfurt.pl new file mode 100644 index 0000000..d941a92 --- /dev/null +++ b/mimosis_standalone/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_mimosis", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/V-2023.09-SP1/',#T-2022.09-SP2/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_hdmi', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 1, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/mimosis_standalone/par.p2t b/mimosis_standalone/par.p2t new file mode 100644 index 0000000..682a299 --- /dev/null +++ b/mimosis_standalone/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 14 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/mimosis_standalone/trb5sc_mimosis.lpf b/mimosis_standalone/trb5sc_mimosis.lpf new file mode 100644 index 0000000..9d59a07 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.lpf @@ -0,0 +1,53 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +# FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +MULTICYCLE FROM CELL "THE_HUB/THE_HUB/reset_i" 15 ns; + + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; +BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; + +BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; +BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; + diff --git a/mimosis_standalone/trb5sc_mimosis.prj b/mimosis_standalone/trb5sc_mimosis.prj new file mode 100644 index 0000000..34ed411 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.prj @@ -0,0 +1,302 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_mimosis.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd" + + +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + +add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd" +add_file -vhdl -lib work "../mimosis/cores/testout.vhd" +add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd" +add_file -vhdl -lib work "../mimosis/code/InputStage.vhd" +add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd" +add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd" + + + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/mimosis_standalone/trb5sc_mimosis.vhd b/mimosis_standalone/trb5sc_mimosis.vhd new file mode 100644 index 0000000..a7d2d58 --- /dev/null +++ b/mimosis_standalone/trb5sc_mimosis.vhd @@ -0,0 +1,875 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +-- use work.med_sync_define.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.cts_pkg.all; + + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --HDMI AddOn + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(3 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of trb5sc_mimosis is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal clk_40, clk_80, clk_160, clk_320 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + signal reboot_from_gbe : std_logic; + signal reset_via_gbe : std_logic; + + + + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + signal rdack, wrack : std_logic; + + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal gbe_status : std_logic_vector(15 downto 0); + + signal clk_350, clk_50, clk_200bypass : std_logic; + + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + -- signal cts_ext_trigger : std_logic; + -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + -- signal cts_ext_control : std_logic_vector(31 downto 0); + -- signal cts_ext_debug : std_logic_vector(31 downto 0); + -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0); + + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + + + signal inp_i : std_logic_vector( 7 downto 0); + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + +begin + + -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => make_reset,--med2int(0).stat_op(13), + SEND_RESET_IN => '0', --med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40, + CLKOS3=> clk_80 + ); + + H3(3) <= clk_320; + + -- For IPHC Proxy + -- RJ(0) <= clk_40; + -- For IKF Proxy + H1(4) <= clk_40; + + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- + GBE : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" + ) + + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_125, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD_0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + STATUS_OUT => gbe_status, --open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_I2C, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_STAT_OP(2 downto 0) => ERROR_NC, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 3) => (others => '0'), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => open, + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 5, --TRB5sc + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (0, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => '0', + EXT_STATUS_IN => (others => '0'), + EXT_CONTROL_OUT => open, + EXT_HEADER_BITS_IN => (others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + -- cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16); + -- cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + -- BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(1) => buscts_rx, + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busgbeip_rx, + BUS_RX(5) => busgbereg_rx, + BUS_RX(6) => busi2c_rx, + + BUS_TX(0) => bustools_tx, + -- BUS_TX(1) => bussci_tx, + BUS_TX(1) => buscts_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busgbeip_tx, + BUS_TX(5) => busgbereg_tx, + BUS_TX(6) => busi2c_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393", + NUM_COINCIDENCES => 4, + NUM_MULTIPLICITIES => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + -- HEADER_IO(7) => HDR_IO(6), + -- HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS(11 downto 0) => x"000", + MONITOR_INPUTS(15 downto 12) => x"0", + TRIG_GEN_INPUTS(11 downto 0) => x"000", + TRIG_GEN_INPUTS(15 downto 12) => x"0", + + TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i, + + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- + THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) + ); + +-- I2C signal open collector driver +-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC + PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START + PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + + PROC_I2C_REGS : process + begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; + end if; + end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_SFP_GREEN <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0'; + LED_SFP_YELLOW <= gbe_status(8); + LED_SFP_RED <= not (gbe_status(3) or gbe_status(4)); --'0'; + + -- LED_SFP_GREEN <= not med2int(0).stat_op(9); + -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- cts_rdo_additional(0).data_finished <= '1'; +-- cts_rdo_additional(0).data_write <= '0'; +-- cts_rdo_additional(0).busy_release <= '1'; + + +end architecture; -- 2.51.0 From fdfdea2d37d85bca2e3fa3ad755f025727586af1 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 9 Aug 2024 14:30:47 +0200 Subject: [PATCH 09/16] write pinout file for RJ45 AddOn --- pinout/trb5sc_rj45.lpf | 217 +++++++++++++++++++++++++---------------- 1 file changed, 132 insertions(+), 85 deletions(-) diff --git a/pinout/trb5sc_rj45.lpf b/pinout/trb5sc_rj45.lpf index fe11101..d6c1b4c 100644 --- a/pinout/trb5sc_rj45.lpf +++ b/pinout/trb5sc_rj45.lpf @@ -62,102 +62,130 @@ LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0" LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1" LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2" LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3" -LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4" -LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5" -LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6" -LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7" DEFINE PORT GROUP "MISO_group" "MISO*" ; IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33; DEFINE PORT GROUP "CS_group" "CS*" ; IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25; -LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8" -LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9" -LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10" -LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11" -IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; -IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ; -IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ; -IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ; - -# DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; -# IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; - - LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1" LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2" IOBUF PORT "SCK" IO_TYPE=LVDS ; IOBUF PORT "MOSI" IO_TYPE=LVDS ; -# DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; -# IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; - -#LOCATE COMP "FE_DIFF[0]" SITE "R29"; #"FE_DIFF[0]" -#LOCATE COMP "FE_DIFF[1]" SITE "T29"; #"FE_DIFF[1]" -#LOCATE COMP "FE_DIFF[2]" SITE "P31"; #"FE_DIFF[2]" -#LOCATE COMP "FE_DIFF[3]" SITE "R30"; #"FE_DIFF[3]" -#LOCATE COMP "FE_DIFF[4]" SITE "N32"; #"FE_DIFF[4]" -#LOCATE COMP "FE_DIFF[5]" SITE "U31"; #"FE_DIFF[5]" -#LOCATE COMP "FE_DIFF[6]" SITE "R32"; #"FE_DIFF[6]" -#LOCATE COMP "FE_DIFF[7]" SITE "W30"; #"FE_DIFF[7]" -#LOCATE COMP "FE_DIFF[8]" SITE "T32"; #"FE_DIFF[8]" -#LOCATE COMP "FE_DIFF[9]" SITE "V32"; #"FE_DIFF[9]" -#LOCATE COMP "FE_DIFF[10]" SITE "Y26"; #"FE_DIFF[10]" -#LOCATE COMP "FE_DIFF[11]" SITE "Y28"; #"FE_DIFF[11]" -#LOCATE COMP "FE_DIFF[12]" SITE "Y29"; #"FE_DIFF[12]" -#LOCATE COMP "FE_DIFF[13]" SITE "AB26"; #"FE_DIFF[13]" -#LOCATE COMP "FE_DIFF[14]" SITE "AB28"; #"FE_DIFF[14]" -#LOCATE COMP "FE_DIFF[15]" SITE "AC26"; #"FE_DIFF[15]" -#LOCATE COMP "FE_DIFF[16]" SITE "D29"; #"FE_DIFF[16]" -#LOCATE COMP "FE_DIFF[17]" SITE "F29"; #"FE_DIFF[17]" -#LOCATE COMP "FE_DIFF[18]" SITE "B32"; #"FE_DIFF[18]" -#LOCATE COMP "FE_DIFF[19]" SITE "D30"; #"FE_DIFF[19]" -#LOCATE COMP "FE_DIFF[20]" SITE "F30"; #"FE_DIFF[20]" -#LOCATE COMP "FE_DIFF[21]" SITE "C32"; #"FE_DIFF[21]" -#LOCATE COMP "FE_DIFF[22]" SITE "F31"; #"FE_DIFF[22]" -#LOCATE COMP "FE_DIFF[23]" SITE "F32"; #"FE_DIFF[23]" -#LOCATE COMP "FE_DIFF[24]" SITE "H31"; #"FE_DIFF[24]" -#LOCATE COMP "FE_DIFF[25]" SITE "J30"; #"FE_DIFF[25]" -#LOCATE COMP "FE_DIFF[26]" SITE "K31"; #"FE_DIFF[26]" -#LOCATE COMP "FE_DIFF[27]" SITE "K32"; #"FE_DIFF[27]" -#LOCATE COMP "FE_DIFF[28]" SITE "L31"; #"FE_DIFF[28]" -#LOCATE COMP "FE_DIFF[29]" SITE "J29"; #"FE_DIFF[29]" -#LOCATE COMP "FE_DIFF[30]" SITE "H27"; #"FE_DIFF[30]" -#LOCATE COMP "FE_DIFF[31]" SITE "K27"; #"FE_DIFF[31]" -#LOCATE COMP "FE_DIFF[32]" SITE "D4"; #"FE_DIFF[32]" -#LOCATE COMP "FE_DIFF[33]" SITE "F4"; #"FE_DIFF[33]" -#LOCATE COMP "FE_DIFF[34]" SITE "B1"; #"FE_DIFF[34]" -#LOCATE COMP "FE_DIFF[35]" SITE "D3"; #"FE_DIFF[35]" -#LOCATE COMP "FE_DIFF[36]" SITE "F3"; #"FE_DIFF[36]" -#LOCATE COMP "FE_DIFF[37]" SITE "C1"; #"FE_DIFF[37]" -#LOCATE COMP "FE_DIFF[38]" SITE "F2"; #"FE_DIFF[38]" -#LOCATE COMP "FE_DIFF[39]" SITE "F1"; #"FE_DIFF[39]" -#LOCATE COMP "FE_DIFF[40]" SITE "H2"; #"FE_DIFF[40]" -#LOCATE COMP "FE_DIFF[41]" SITE "J3"; #"FE_DIFF[41]" -#LOCATE COMP "FE_DIFF[42]" SITE "K2"; #"FE_DIFF[42]" -#LOCATE COMP "FE_DIFF[43]" SITE "K1"; #"FE_DIFF[43]" -#LOCATE COMP "FE_DIFF[44]" SITE "L2"; #"FE_DIFF[44]" -#LOCATE COMP "FE_DIFF[45]" SITE "J4"; #"FE_DIFF[45]" -#LOCATE COMP "FE_DIFF[46]" SITE "H6"; #"FE_DIFF[46]" -#LOCATE COMP "FE_DIFF[47]" SITE "K6"; #"FE_DIFF[47]" -#LOCATE COMP "FE_DIFF[48]" SITE "R4"; #"FE_DIFF[48]" -#LOCATE COMP "FE_DIFF[49]" SITE "T4"; #"FE_DIFF[49]" -#LOCATE COMP "FE_DIFF[50]" SITE "P2"; #"FE_DIFF[50]" -#LOCATE COMP "FE_DIFF[51]" SITE "R3"; #"FE_DIFF[51]" -#LOCATE COMP "FE_DIFF[52]" SITE "N1"; #"FE_DIFF[52]" -#LOCATE COMP "FE_DIFF[53]" SITE "U2"; #"FE_DIFF[53]" -#LOCATE COMP "FE_DIFF[54]" SITE "R1"; #"FE_DIFF[54]" -#LOCATE COMP "FE_DIFF[55]" SITE "W3"; #"FE_DIFF[55]" -#LOCATE COMP "FE_DIFF[56]" SITE "T1"; #"FE_DIFF[56]" -#LOCATE COMP "FE_DIFF[57]" SITE "V1"; #"FE_DIFF[57]" -#LOCATE COMP "FE_DIFF[58]" SITE "Y7"; #"FE_DIFF[58]" -#LOCATE COMP "FE_DIFF[59]" SITE "Y5"; #"FE_DIFF[59]" -#LOCATE COMP "FE_DIFF[60]" SITE "Y4"; #"FE_DIFF[60]" -#LOCATE COMP "FE_DIFF[61]" SITE "AB7"; #"FE_DIFF[61]" -#LOCATE COMP "FE_DIFF[62]" SITE "AB5"; #"FE_DIFF[62]" -#LOCATE COMP "FE_DIFF[63]" SITE "AC7"; #"FE_DIFF[63]" + +################################################################# +# Inputs ordered by connectors (use either this set, or...) +################################################################# +LOCATE COMP "RJ_A[0]" SITE "D4"; #"FE_DIFF[32]" +LOCATE COMP "RJ_A[1]" SITE "B1"; #"FE_DIFF[34]" +LOCATE COMP "RJ_A[2]" SITE "D3"; #"FE_DIFF[35]" +LOCATE COMP "RJ_A[3]" SITE "C1"; #"FE_DIFF[37]" +LOCATE COMP "RJ_B[0]" SITE "F2"; #"FE_DIFF[38]" +LOCATE COMP "RJ_B[1]" SITE "F3"; #"FE_DIFF[36]" +LOCATE COMP "RJ_B[2]" SITE "F1"; #"FE_DIFF[39]" +LOCATE COMP "RJ_B[3]" SITE "F4"; #"FE_DIFF[33]" +LOCATE COMP "RJ_C[0]" SITE "H2"; #"FE_DIFF[40]" +LOCATE COMP "RJ_C[1]" SITE "K2"; #"FE_DIFF[42]" +LOCATE COMP "RJ_C[2]" SITE "K6"; #"FE_DIFF[47]" +LOCATE COMP "RJ_C[3]" SITE "J4"; #"FE_DIFF[45]" +LOCATE COMP "RJ_D[0]" SITE "H6"; #"FE_DIFF[46]" +LOCATE COMP "RJ_D[1]" SITE "L2"; #"FE_DIFF[44]" +LOCATE COMP "RJ_D[2]" SITE "K1"; #"FE_DIFF[43]" +LOCATE COMP "RJ_D[3]" SITE "J3"; #"FE_DIFF[41]" +LOCATE COMP "RJ_E[0]" SITE "D29"; #"FE_DIFF[16]" +LOCATE COMP "RJ_E[1]" SITE "B32"; #"FE_DIFF[18]" +LOCATE COMP "RJ_E[2]" SITE "D30"; #"FE_DIFF[19]" +LOCATE COMP "RJ_E[3]" SITE "F32"; #"FE_DIFF[23]" +LOCATE COMP "RJ_F[0]" SITE "F31"; #"FE_DIFF[22]" +LOCATE COMP "RJ_F[1]" SITE "F30"; #"FE_DIFF[20]" +LOCATE COMP "RJ_F[2]" SITE "C32"; #"FE_DIFF[21]" +LOCATE COMP "RJ_F[3]" SITE "F29"; #"FE_DIFF[17]" +LOCATE COMP "RJ_G[0]" SITE "H31"; #"FE_DIFF[24]" +LOCATE COMP "RJ_G[1]" SITE "K31"; #"FE_DIFF[26]" +LOCATE COMP "RJ_G[2]" SITE "K32"; #"FE_DIFF[27]" +LOCATE COMP "RJ_G[3]" SITE "J29"; #"FE_DIFF[29]" +LOCATE COMP "RJ_H[0]" SITE "H27"; #"FE_DIFF[30]" +LOCATE COMP "RJ_H[1]" SITE "L31"; #"FE_DIFF[28]" +LOCATE COMP "RJ_H[2]" SITE "K27"; #"FE_DIFF[31]" +LOCATE COMP "RJ_H[3]" SITE "J30"; #"FE_DIFF[25]" +LOCATE COMP "RJ_I[0]" SITE "R4"; #"FE_DIFF[48]" +LOCATE COMP "RJ_I[1]" SITE "P2"; #"FE_DIFF[50]" +LOCATE COMP "RJ_I[2]" SITE "W3"; #"FE_DIFF[55]" +LOCATE COMP "RJ_I[3]" SITE "U2"; #"FE_DIFF[53]" +LOCATE COMP "RJ_J[0]" SITE "R1"; #"FE_DIFF[54]" +LOCATE COMP "RJ_J[1]" SITE "N1"; #"FE_DIFF[52]" +LOCATE COMP "RJ_J[2]" SITE "R3"; #"FE_DIFF[51]" +LOCATE COMP "RJ_J[3]" SITE "T4"; #"FE_DIFF[49]" +LOCATE COMP "RJ_K[0]" SITE "T1"; #"FE_DIFF[56]" +LOCATE COMP "RJ_K[1]" SITE "Y7"; #"FE_DIFF[58]" +LOCATE COMP "RJ_K[2]" SITE "V1"; #"FE_DIFF[57]" +LOCATE COMP "RJ_K[3]" SITE "AB7"; #"FE_DIFF[61]" +LOCATE COMP "RJ_L[0]" SITE "AB5"; #"FE_DIFF[62]" +LOCATE COMP "RJ_L[1]" SITE "Y4"; #"FE_DIFF[60]" +LOCATE COMP "RJ_L[2]" SITE "AC7"; #"FE_DIFF[63]" +LOCATE COMP "RJ_L[3]" SITE "Y5"; #"FE_DIFF[59]" + + +################################################################# +# Inputs in numerical order from A0 to L3 (... or use this set ...) +################################################################# +LOCATE COMP "RJ[0]" SITE "D4"; #"FE_DIFF[32]" +LOCATE COMP "RJ[1]" SITE "B1"; #"FE_DIFF[34]" +LOCATE COMP "RJ[2]" SITE "D3"; #"FE_DIFF[35]" +LOCATE COMP "RJ[3]" SITE "C1"; #"FE_DIFF[37]" +LOCATE COMP "RJ[4]" SITE "F2"; #"FE_DIFF[38]" +LOCATE COMP "RJ[5]" SITE "F3"; #"FE_DIFF[36]" +LOCATE COMP "RJ[6]" SITE "F1"; #"FE_DIFF[39]" +LOCATE COMP "RJ[7]" SITE "F4"; #"FE_DIFF[33]" +LOCATE COMP "RJ[8]" SITE "H2"; #"FE_DIFF[40]" +LOCATE COMP "RJ[9]" SITE "K2"; #"FE_DIFF[42]" +LOCATE COMP "RJ[10]" SITE "K6"; #"FE_DIFF[47]" +LOCATE COMP "RJ[11]" SITE "J4"; #"FE_DIFF[45]" +LOCATE COMP "RJ[12]" SITE "H6"; #"FE_DIFF[46]" +LOCATE COMP "RJ[13]" SITE "L2"; #"FE_DIFF[44]" +LOCATE COMP "RJ[14]" SITE "K1"; #"FE_DIFF[43]" +LOCATE COMP "RJ[15]" SITE "J3"; #"FE_DIFF[41]" +LOCATE COMP "RJ[16]" SITE "D29"; #"FE_DIFF[16]" +LOCATE COMP "RJ[17]" SITE "B32"; #"FE_DIFF[18]" +LOCATE COMP "RJ[18]" SITE "D30"; #"FE_DIFF[19]" +LOCATE COMP "RJ[19]" SITE "F32"; #"FE_DIFF[23]" +LOCATE COMP "RJ[20]" SITE "F31"; #"FE_DIFF[22]" +LOCATE COMP "RJ[21]" SITE "F30"; #"FE_DIFF[20]" +LOCATE COMP "RJ[22]" SITE "C32"; #"FE_DIFF[21]" +LOCATE COMP "RJ[23]" SITE "F29"; #"FE_DIFF[17]" +LOCATE COMP "RJ[24]" SITE "H31"; #"FE_DIFF[24]" +LOCATE COMP "RJ[25]" SITE "K31"; #"FE_DIFF[26]" +LOCATE COMP "RJ[26]" SITE "K32"; #"FE_DIFF[27]" +LOCATE COMP "RJ[27]" SITE "J29"; #"FE_DIFF[29]" +LOCATE COMP "RJ[28]" SITE "H27"; #"FE_DIFF[30]" +LOCATE COMP "RJ[29]" SITE "L31"; #"FE_DIFF[28]" +LOCATE COMP "RJ[30]" SITE "K27"; #"FE_DIFF[31]" +LOCATE COMP "RJ[31]" SITE "J30"; #"FE_DIFF[25]" +LOCATE COMP "RJ[32]" SITE "R4"; #"FE_DIFF[48]" +LOCATE COMP "RJ[33]" SITE "P2"; #"FE_DIFF[50]" +LOCATE COMP "RJ[34]" SITE "W3"; #"FE_DIFF[55]" +LOCATE COMP "RJ[35]" SITE "U2"; #"FE_DIFF[53]" +LOCATE COMP "RJ[36]" SITE "R1"; #"FE_DIFF[54]" +LOCATE COMP "RJ[37]" SITE "N1"; #"FE_DIFF[52]" +LOCATE COMP "RJ[38]" SITE "R3"; #"FE_DIFF[51]" +LOCATE COMP "RJ[39]" SITE "T4"; #"FE_DIFF[49]" +LOCATE COMP "RJ[40]" SITE "T1"; #"FE_DIFF[56]" +LOCATE COMP "RJ[41]" SITE "Y7"; #"FE_DIFF[58]" +LOCATE COMP "RJ[42]" SITE "V1"; #"FE_DIFF[57]" +LOCATE COMP "RJ[43]" SITE "AB7"; #"FE_DIFF[61]" +LOCATE COMP "RJ[44]" SITE "AB5"; #"FE_DIFF[62]" +LOCATE COMP "RJ[45]" SITE "Y4"; #"FE_DIFF[60]" +LOCATE COMP "RJ[46]" SITE "AC7"; #"FE_DIFF[63]" +LOCATE COMP "RJ[47]" SITE "Y5"; #"FE_DIFF[59]" + +DEFINE PORT GROUP "RJ_group" "RJ*" ; +IOBUF GROUP "RJ_group" IO_TYPE=LVDS DIFFRESISTOR=100; + +################################################################# +# Just first line from every input (... or use this set) +################################################################# LOCATE COMP "FE_DIFF_IN[0]" SITE "F31"; #"FE_DIFF[22]" LOCATE COMP "FE_DIFF_IN[1]" SITE "H27"; #"FE_DIFF[30]" LOCATE COMP "FE_DIFF_IN[2]" SITE "F2"; #"FE_DIFF[38]" @@ -174,7 +202,9 @@ LOCATE COMP "FE_DIFF_IN[11]" SITE "T1"; #"FE_DIFF[56]" DEFINE PORT GROUP "FE_DIFF_IN_group" "FE_DIFF_IN*" ; IOBUF GROUP "FE_DIFF_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100; - +################################################################# +# Outputs on both black RJ connectors +################################################################# LOCATE COMP "FE_DIFF_OUT[0]" SITE "R29"; #"FE_DIFF[0]" - J11 LOCATE COMP "FE_DIFF_OUT[1]" SITE "P31"; #"FE_DIFF[2]" - J11 LOCATE COMP "FE_DIFF_OUT[2]" SITE "N32"; #"FE_DIFF[4]" - J11 @@ -188,6 +218,23 @@ DEFINE PORT GROUP "FE_DIFF_OUT_group" "FE_DIFF_OUT*"; IOBUF GROUP "FE_DIFF_OUT_group" IO_TYPE=LVDS; + + + + + + + + + + + + + + + + + ################################################################# # Temperature, Flash & ID ################################################################# -- 2.51.0 From c8bc52eac5feda30d947ebe4284c662d77d4b830 Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Fri, 30 Aug 2024 11:03:25 +0200 Subject: [PATCH 10/16] better vldb core --- vldb/code/gbt_core.vhd | 178 ++++++++++++++++++++-------------------- vldb/par.p2t | 2 +- vldb/trb5sc_mimosis.vhd | 48 ++--------- 3 files changed, 96 insertions(+), 132 deletions(-) diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 85f268a..46cffb4 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -27,42 +27,45 @@ end entity; architecture arch of gbt_core is -- Clock & reset - signal gbtsc_tx_clk_en : std_logic := '0'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - signal gbtsc_rx_clk_en : std_logic := '0'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled + signal gbtsc_tx_clk_en : std_logic := '0'; + signal gbtsc_rx_clk_en : std_logic := '0'; -- SCA control - signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs - signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs - signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs - signal gbtsc_start_command_i : std_logic := '0'; --! Send the command set in input to the enabled SCAs + signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs + signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs + signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs + signal gbtsc_start_command_i : std_logic := '0'; --! Send the command in input to the enabled SCAs signal gbtsc_start_reset_cmd_raw :std_logic := '0'; signal gbtsc_start_connect_cmd_raw :std_logic := '0'; signal gbtsc_start_command_raw :std_logic := '0'; signal gbtsc_reset_go : std_logic := '0'; signal gbtsc_connect_go : std_logic := '0'; signal gbtsc_go : std_logic := '0'; + -- SCA command - signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; --! Command: address field (According to the SCA manual) - signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; --! Command: transaction ID field (According to the SCA manual) - signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; --! Command: channel field (According to the SCA manual) - signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; --! Command: command field (According to the SCA manual) - signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; --! Command: data field (According to the SCA manual) - - signal gbtsc_rx_received_o : std_logic := '0'; --! Reply received flag (pulse) - signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual) - signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual) - signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual) - signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual) - signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual) - signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual) - signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual) - signal sync_reg : std_logic_vector(79 downto 0); -- register for syncing + signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; + signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; + signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; + signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; + signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; + + signal gbtsc_rx_received_o : std_logic := '0'; + signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); + signal sync_reg : std_logic_vector(79 downto 0); signal sync_reg_done_100 : std_logic := '0'; signal sync_reg_done_40 : std_logic := '0'; -- EC line - signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (TX) Array of bits to be mapped to the TX GBT-Frame - signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (RX) Array of bits to be mapped to the RX GBT-Frame + signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; + signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; + + signal hdlc_des : std_logic_vector(3 downto 0); signal test_out : std_logic_vector(7 downto 0) := (others => '0'); signal counter : unsigned(23 downto 0); @@ -74,44 +77,41 @@ begin THE_GBTSC_TOP : entity work.gbtsc_top generic map( - -- IC configuration - g_IC_FIFO_DEPTH => 20, --! Defines the depth of the FIFO used to handle the Internal control (Max. number of words/bytes can be read/write from/to a GBTx) - - -- EC configuration - g_SCA_COUNT => 1 --! Defines the maximum number of SCA that can be connected to this module + g_IC_FIFO_DEPTH => 20, + g_SCA_COUNT => 1 ) port map( -- Clock & reset - tx_clk_i => CLK, -- gbtsc_tx_clk_i, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - tx_clk_en => gbtsc_tx_clk_en, --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - tx_reset_i => RESET, -- gbtsc_tx_reset_i, --! Reset TX datapath + tx_clk_i => CLK, + tx_clk_en => gbtsc_tx_clk_en, + tx_reset_i => RESET, - rx_clk_i => CLK, -- gbtsc_rx_clk_i, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - rx_clk_en => gbtsc_rx_clk_en, --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled - rx_reset_i => RESET, -- gbtsc_rx_reset_i, --! Reset RX datapath + rx_clk_i => CLK, + rx_clk_en => gbtsc_rx_clk_en, + rx_reset_i => RESET, -- IC control - tx_start_write_i => '0', -- gbtsc_tx_start_write_i, --! Request a write config. to the GBTx (IC) - tx_start_read_i => '0', -- gbtsc_tx_start_read_i, --! Request a read config. to the GBTx (IC) + tx_start_write_i => '0', + tx_start_read_i => '0', -- IC configuration - tx_GBTx_address_i => (others => '0'), -- gbtsc_tx_GBTx_address_i, --! I2C address of the GBTx - tx_register_addr_i => (others => '0'), -- gbtsc_tx_register_addr_i, --! Address of the first register to be accessed - tx_nb_to_be_read_i => (others => '0'), -- gbtsc_tx_nb_to_be_read_i, --! Number of words/bytes to be read (only for read transactions) + tx_GBTx_address_i => (others => '0'), + tx_register_addr_i => (others => '0'), + tx_nb_to_be_read_i => (others => '0'), -- IC FIFO control - wr_clk_i => CLK, --! Fifo's writing clock - tx_wr_i => '0', -- gbtsc_tx_wr_i, --! Request a write operation into the internal FIFO (Data to GBTx) - tx_data_to_gbtx_i => (others => '0'), -- gbtsc_tx_data_to_gbtx_i, --! Data to be written into the internal FIFO + wr_clk_i => CLK, + tx_wr_i => '0', + tx_data_to_gbtx_i => (others => '0'), rd_clk_i => CLK, - rx_rd_i => '0', -- gbtsc_rx_rd_i, --! Request a read operation of the internal FIFO (GBTx reply) - rx_data_from_gbtx_o => open, -- gbtsc_rx_data_from_gbtx_o, --! Data from the FIFO + rx_rd_i => '0', + rx_data_from_gbtx_o => open, -- IC Status - tx_ready_o => open, -- gbtsc_tx_ready_o, --! IC core ready for a transaction - rx_empty_o => open, -- gbtsc_rx_empty_o, --! Rx FIFO is empty (no reply from GBTx) + tx_ready_o => open, + rx_empty_o => open, -- SCA control sca_enable_i(0) => gbtsc_sca_enable_i, --! Enable flag to select SCAs @@ -121,28 +121,28 @@ begin inject_crc_error => '0', --! Emulate a CRC error -- SCA command - tx_address_i => gbtsc_tx_address_i, --! Command: address field (According to the SCA manual) - tx_transID_i => gbtsc_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) - tx_channel_i => gbtsc_tx_channel_i, --! Command: channel field (According to the SCA manual) - tx_command_i => gbtsc_tx_command_i, --! Command: command field (According to the SCA manual) - tx_data_i => gbtsc_tx_data_i, --! Command: data field (According to the SCA manual) - - rx_received_o(0) => gbtsc_rx_received_o, --! Reply: received flag (pulse) - rx_address_o(0) => gbtsc_rx_address_o, --! Reply: address field (According to the SCA manual) - rx_control_o(0) => gbtsc_rx_control_o, --! Reply: control field (According to the SCA manual) - rx_transID_o(0) => gbtsc_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) - rx_channel_o(0) => gbtsc_rx_channel_o, --! Reply: channel field (According to the SCA manual) - rx_len_o(0) => gbtsc_rx_len_o, --! Reply: len field (According to the SCA manual) - rx_error_o(0) => gbtsc_rx_error_o, --! Reply: error field (According to the SCA manual) - rx_data_o(0) => gbtsc_rx_data_o, --! Reply: data field (According to the SCA manual) + tx_address_i => gbtsc_tx_address_i, --! Address field (According to the SCA manual) + tx_transID_i => gbtsc_tx_transID_i, --! Transaction ID field (According to the SCA manual) + tx_channel_i => gbtsc_tx_channel_i, --! Channel field (According to the SCA manual) + tx_command_i => gbtsc_tx_command_i, --! Command field (According to the SCA manual) + tx_data_i => gbtsc_tx_data_i, --! Data field (According to the SCA manual) + + rx_received_o(0) => gbtsc_rx_received_o, --! Received flag (pulse) + rx_address_o(0) => gbtsc_rx_address_o, --! Address field (According to the SCA manual) + rx_control_o(0) => gbtsc_rx_control_o, --! Control field (According to the SCA manual) + rx_transID_o(0) => gbtsc_rx_transID_o, --! Transaction ID field (According to the SCA manual) + rx_channel_o(0) => gbtsc_rx_channel_o, --! Channel field (According to the SCA manual) + rx_len_o(0) => gbtsc_rx_len_o, --! Len field (According to the SCA manual) + rx_error_o(0) => gbtsc_rx_error_o, --! Error field (According to the SCA manual) + rx_data_o(0) => gbtsc_rx_data_o, --! Data field (According to the SCA manual) -- EC line - ec_data_o(0) => hdlc_from_gbtsc, --! (TX) Array of bits to be mapped to the TX GBT-Frame - ec_data_i(0) => hdlc_to_gbtsc, --! (RX) Array of bits to be mapped to the RX GBT-Frame + ec_data_o(0) => hdlc_from_gbtsc, + ec_data_i(0) => hdlc_to_gbtsc, -- IC lines - ic_data_o => open, --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) - ic_data_i => "00" --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) + ic_data_o => open, + ic_data_i => "00" ); @@ -188,28 +188,27 @@ begin -- HDLC serializer hdlcser_proc: process(CLK_80) + variable bitflip : std_logic := '0'; begin if rising_edge(CLK_80) then - if CLK = '1' then + if bitflip = '1' then ELINK_TX <= hdlc_from_gbtsc(1); else ELINK_TX <= hdlc_from_gbtsc(0); end if; + bitflip := not bitflip; + hdlc_des <= hdlc_des(2 downto 0) & ELINK_RX; end if; end process; - -- HDLC deserializer - hdlcdes_proc: process(CLK_80) - variable hdlc_des: std_logic_vector(1 downto 0); + + elink_input_proc: process(CLK) begin - if rising_edge(CLK_80) then - hdlc_des := hdlc_des(0) & ELINK_RX; - if CLK = '1' then - hdlc_to_gbtsc <= hdlc_des; - end if; + if rising_edge(CLK) then + hdlc_to_gbtsc <= hdlc_des(3) & hdlc_des(2); end if; end process; - + PROC_GBTSCA_REG_CMDS : process begin @@ -228,17 +227,17 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(3 downto 0) = x"0" then - gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); -- hdlc Address + gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); elsif BUS_RX.addr(3 downto 0) = x"1" then - gbtsc_reset_go <= BUS_RX.data(0); -- gbtsca RESET - gbtsc_connect_go <= BUS_RX.data(1); -- gbtsca CONNECT - gbtsc_go <= BUS_RX.data(2); -- gbtsca Start Command + gbtsc_reset_go <= BUS_RX.data(0); + gbtsc_connect_go <= BUS_RX.data(1); + gbtsc_go <= BUS_RX.data(2); elsif BUS_RX.addr(3 downto 0) = x"2" then - gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); -- gbtsca TransID - gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); -- gbtsca Channel - gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); -- gbtsca Command + gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); + gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); + gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); elsif BUS_RX.addr(3 downto 0) = x"3" then - gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); -- gbtsca Data + gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; @@ -248,15 +247,15 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(3 downto 0) = x"a" then - BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); -- hdlc Address - BUS_TX.data(15 downto 8) <= sync_reg(71 downto 64); -- hdlc Control + BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); + BUS_TX.data(15 downto 8) <= sync_reg(71 downto 64); elsif BUS_RX.addr(3 downto 0) = x"b" then - BUS_TX.data( 7 downto 0 ) <= sync_reg(63 downto 56); -- gbtsca TransID - BUS_TX.data(15 downto 8 ) <= sync_reg(55 downto 48); -- gbtsca Channel - BUS_TX.data(23 downto 16) <= sync_reg(47 downto 40); -- gbtsca Error - BUS_TX.data(31 downto 24) <= sync_reg(39 downto 32); -- gbtsca Length + BUS_TX.data( 7 downto 0 ) <= sync_reg(63 downto 56); + BUS_TX.data(15 downto 8 ) <= sync_reg(55 downto 48); + BUS_TX.data(23 downto 16) <= sync_reg(47 downto 40); + BUS_TX.data(31 downto 24) <= sync_reg(39 downto 32); elsif BUS_RX.addr(3 downto 0) = x"c" then - BUS_TX.data(31 downto 0) <= sync_reg(31 downto 0); -- gbtsca Data + BUS_TX.data(31 downto 0) <= sync_reg(31 downto 0); sync_reg_done_100 <= '1'; else BUS_TX.ack <= '0'; @@ -307,5 +306,4 @@ begin PULSE_B_OUT => sync_reg_done_40 ); - end architecture; diff --git a/vldb/par.p2t b/vldb/par.p2t index 90538cf..9c0aff1 100644 --- a/vldb/par.p2t +++ b/vldb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 48 +-t 25 -c 2 -e 2 -i 10 diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd index 0c45747..8cba1dc 100644 --- a/vldb/trb5sc_mimosis.vhd +++ b/vldb/trb5sc_mimosis.vhd @@ -10,6 +10,7 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.med_sync_define.all; + entity trb5sc_mimosis is port( CLK_200 : in std_logic; @@ -148,9 +149,9 @@ architecture arch of trb5sc_mimosis is signal i2c_reg_2 : std_logic_vector(31 downto 0); signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); signal mimosis_scl_drv, mimosis_sda_drv : std_logic; - signal i2c_go_100, i2c_go : std_logic; - signal i2c_reg_5_40 : std_logic_vector(31 downto 0); - signal counter : unsigned(23 downto 0); + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); --signal fwd_dst_mac : std_logic_vector(47 downto 0); --signal fwd_dst_ip : std_logic_vector(31 downto 0); @@ -212,7 +213,7 @@ begin THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync generic map( SERDES_NUM => SERDES_NUM, - USE_NEW_ECP5_RESET => 0, + USE_NEW_ECP5_RESET => 1, IS_SYNC_SLAVE => c_YES ) port map( @@ -551,6 +552,7 @@ begin LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); LED_ADDON_SFP_ORANGE(1) <= '0'; + ----------------------------------------------------------------------------- ---- GbE ----------------------------------------------------------------------------- @@ -687,43 +689,6 @@ begin --end process; ---------------------------------------------------------------------------- --- Output stage ---------------------------------------------------------------------------- - THE_OUT : entity work.testout - port map( - clkout => open, - refclk => clk_160, - reset => reset_i, - data => out_data, - data_cflag => open, - data_direction => (others => '0'), - data_loadn => (others => '1'), - data_move => (others => '0'), - dout => out_i - ); - - PROC_OUT : process - variable cnt : integer range 0 to 7; - begin - wait until rising_edge(clk_160); - cnt := cnt + 1; - case cnt is - when 0 => out_data <= x"ffff"; - when 1 => out_data <= x"ffff"; - when 2 => out_data <= x"ffff"; - when 3 => out_data <= x"0000"; - when 4 => out_data <= x"5555"; - when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555"; - when 7 => out_data <= x"5555"; - end case; - end process; - - -- H3(3 downto 0) <= out_i(3 downto 0); - -- H4(3 downto 0) <= out_i(7 downto 4); - - --------------------------------------------------------------------------- -- GBT Core --------------------------------------------------------------------------- @@ -739,6 +704,7 @@ begin TESTOUT => LED, + -- ELINK_RX => H3(2), ELINK_RX => H3_2, ELINK_TX => H3(0) ); -- 2.51.0 From 08c297cc23fef44d00884650770524f5aaf0a1c4 Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Fri, 30 Aug 2024 11:08:54 +0200 Subject: [PATCH 11/16] commit for push/pull --- mimosis/par.p2t | 2 +- mimosis/trb5sc_mimosis.vhd | 43 +++----------------------------------- pinout/trb5sc_hdmi.lpf | 11 ++++++++-- 3 files changed, 13 insertions(+), 43 deletions(-) diff --git a/mimosis/par.p2t b/mimosis/par.p2t index 2ce0381..5a046a0 100644 --- a/mimosis/par.p2t +++ b/mimosis/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 10 +-t 34 -c 2 -e 2 -i 10 diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index 9814b66..a8c2792 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -10,6 +10,7 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.med_sync_define.all; + entity trb5sc_mimosis is port( CLK_200 : in std_logic; @@ -203,9 +204,9 @@ begin H3(3) <= clk_320; -- For IPHC Proxy - -- RJ(0) <= clk_40; + RJ(0) <= clk_40; -- For IKF Proxy - H1(4) <= clk_40; + -- H1(4) <= clk_40; --------------------------------------------------------------------------- -- TrbNet Uplink @@ -558,7 +559,6 @@ begin LED_ADDON_SFP_ORANGE(1) <= '0'; - ----------------------------------------------------------------------------- ---- GbE ----------------------------------------------------------------------------- @@ -695,43 +695,6 @@ begin --end process; ---------------------------------------------------------------------------- --- Output stage ---------------------------------------------------------------------------- - -- THE_OUT : entity work.testout - -- port map( - -- clkout => open, - -- refclk => clk_160, - -- reset => reset_i, - -- data => out_data, - -- data_cflag => open, - -- data_direction => (others => '0'), - -- data_loadn => (others => '1'), - -- data_move => (others => '0'), - -- dout => out_i - -- ); - - -- PROC_OUT : process - -- variable cnt : integer range 0 to 7; - -- begin - -- wait until rising_edge(clk_160); - -- cnt := cnt + 1; - -- case cnt is - -- when 0 => out_data <= x"ffff"; - -- when 1 => out_data <= x"ffff"; - -- when 2 => out_data <= x"ffff"; - -- when 3 => out_data <= x"0000"; - -- when 4 => out_data <= x"5555"; - -- when 5 => out_data <= x"5555"; - -- when 6 => out_data <= x"5555"; - -- when 7 => out_data <= x"5555"; - -- end case; - -- end process; - - -- H3(3 downto 0) <= out_i(3 downto 0); - -- H4(3 downto 0) <= out_i(7 downto 4); - - --------------------------------------------------------------------------- -- Input stage --------------------------------------------------------------------------- diff --git a/pinout/trb5sc_hdmi.lpf b/pinout/trb5sc_hdmi.lpf index 6c89d07..ace0ab9 100644 --- a/pinout/trb5sc_hdmi.lpf +++ b/pinout/trb5sc_hdmi.lpf @@ -88,8 +88,10 @@ LOCATE COMP "H5[3]" SITE "R32" ; #was "FE_DIFF[6]" LOCATE COMP "H7[3]" SITE "W30" ; #was "FE_DIFF[7]" #LOCATE COMP "H5[4]" SITE "T32" ; #was "FE_DIFF[8]" +# H5 # LOCATE COMP "MIMOSIS_SCL" SITE "U32" ; #was "FE_DIFF[8]" # LOCATE COMP "MIMOSIS_SDA" SITE "T32" ; #was "FE_DIFF[8]" +# H3 LOCATE COMP "MIMOSIS_SCL" SITE "C2" ; #was "FE_DIFF[8]" LOCATE COMP "MIMOSIS_SDA" SITE "B1" ; #was "FE_DIFF[8]" IOBUF PORT "MIMOSIS_SCL" IO_TYPE=LVCMOS25 ; @@ -120,8 +122,8 @@ LOCATE COMP "H2[0]" SITE "H27" ; #was "FE_DIFF[30]" # LOCATE COMP "FE_DIFF[31]" SITE "K27" ; #was "FE_DIFF[31]" LOCATE COMP "H3[3]" SITE "D4" ; #was "FE_DIFF[32]" LOCATE COMP "H3[4]" SITE "B1" ; #was "FE_DIFF[34]" -# LOCATE COMP "H3[2]" SITE "F3" ; #was "FE_DIFF[36]" -LOCATE COMP "H3_2" SITE "F3" ; #was "FE_DIFF[36]" +LOCATE COMP "H3[2]" SITE "F3" ; #was "FE_DIFF[36]" +# LOCATE COMP "H3_2" SITE "F3" ; #was "FE_DIFF[36]" LOCATE COMP "H3[1]" SITE "F2" ; #was "FE_DIFF[38]" LOCATE COMP "H3[0]" SITE "H2" ; #was "FE_DIFF[40]" # LOCATE COMP "FE_DIFF[41]" SITE "J3" ; #was "FE_DIFF[41]" @@ -153,6 +155,11 @@ DEFINE PORT GROUP "H2_group" "H2*" ; IOBUF GROUP "H2_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; DEFINE PORT GROUP "H3_group" "H3*" ; IOBUF GROUP "H3_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; + +# IOBUF PORT "H3_0" IO_TYPE=LVDS DIFFRESISTOR=100; +# IOBUF PORT "H3_2" IO_TYPE=LVDS DIFFRESISTOR=100; +# IOBUF PORT "H3_3" IO_TYPE=LVDS DIFFRESISTOR=100; + DEFINE PORT GROUP "H4_group" "H4*" ; IOBUF GROUP "H4_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; DEFINE PORT GROUP "H5_group" "H5*" ; -- 2.51.0 From c1ba04aef48e4eb9db2f891c1a07003f1566e834 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 Jan 2025 12:31:10 +0100 Subject: [PATCH 12/16] update Baseline calculation, invert input delay reset bit --- adc/source/adc_18bit_input.vhd | 54 ++++++++++++++-------------------- adc/source/adc_addon.vhd | 8 ++--- adc/source/adc_input.vhd | 8 ++--- adc/source/adc_processor.vhd | 10 +++++-- 4 files changed, 37 insertions(+), 43 deletions(-) diff --git a/adc/source/adc_18bit_input.vhd b/adc/source/adc_18bit_input.vhd index 2567710..0e7041d 100644 --- a/adc/source/adc_18bit_input.vhd +++ b/adc/source/adc_18bit_input.vhd @@ -46,9 +46,7 @@ signal data_reg_save : std_logic_vector(27 downto 0); signal clock_reg : std_logic_vector(27 downto 0); signal clock_reg_save : std_logic_vector(27 downto 0); -constant TESTPATTERN : std_logic_vector(17 downto 0) := 18x"281FC"; - -signal start_timer : unsigned(23 downto 0) := (others => '0'); +constant TESTPATTERN : std_logic_vector(17 downto 0) := 18x"281FC"; begin @@ -73,38 +71,30 @@ THE_CLOCK_OUT : entity work.adc_1ch_clk dout(0) => ADC_CLK_OUT ); - -PROC_START : process begin - wait until rising_edge(CLK_ADCRAW); - if RESET_ADC = '1' then - start_timer <= (others => '0'); - elsif start_timer(start_timer'left) = '0' then - start_timer <= start_timer + 1; - end if; -end process; + PROC_CONTROL : process begin wait until rising_edge(CLK_ADCRAW); - if start_timer(start_timer'left) = '1' then - if cycle_counter = 30 then - cycle_counter <= 0; - else - cycle_counter <= cycle_counter + 1; - end if; - if cycle_counter = 10 then - clock_enable <= '1'; - elsif cycle_counter = 19 then - clock_enable <= '0'; - end if; + if cycle_counter = 30 then + cycle_counter <= 0; + else + cycle_counter <= cycle_counter + 1; + end if; - if cycle_counter = 0 or cycle_counter = 1 then - ADC_CNV_OUT <= '1'; - else - ADC_CNV_OUT <= '0'; - end if; + if cycle_counter <= 8 then + clock_enable <= '1'; + else + clock_enable <= '0'; end if; + + if cycle_counter = 13 or cycle_counter = 14 then + ADC_CNV_OUT <= '1'; + else + ADC_CNV_OUT <= '0'; + end if; + end process; PROC_INPUT : process begin @@ -122,18 +112,18 @@ PROC_INPUT : process begin if CONF_ALIGN_EN = '1' and data_reg(17 downto 0) = TESTPATTERN then cycle_input <= 1; - data_shifted <= CONF_data_shifted; + data_shifted <= '0'; elsif CONF_ALIGN_EN = '1' and data_reg(18 downto 1) = TESTPATTERN then cycle_input <= 1; - data_shifted <= not CONF_data_shifted; + data_shifted <= '1'; end if; - if data_in(3 downto 2) = "00" and cycle_input = 0 then + if data_in(3 downto 2) = "00" then cycle_input <= 0; end if; - if cycle_input = 10 then + if cycle_input = 9 then data_reg_save <= data_reg; clock_reg_save <= clock_reg; diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd index 9acd029..9d95724 100644 --- a/adc/source/adc_addon.vhd +++ b/adc/source/adc_addon.vhd @@ -65,11 +65,11 @@ architecture arch of adc_addon is alias STROBE_shift_align_b : std_logic is basic_control_strobes(9); alias STROBE_del_move_b : std_logic is basic_control_strobes(11); - signal basic_control : std_logic_vector(31 downto 0); + signal basic_control : std_logic_vector(31 downto 0) := (others => '0'); alias CONF_adc_stop : std_logic is basic_control(0); -- alias CONF_baseline_always_on : std_logic is basic_control(1); alias CONF_del_direction : std_logic is basic_control(2); - alias CONF_del_loadn : std_logic is basic_control(3); + alias CONF_del_load : std_logic is basic_control(3); alias CONF_alignen_b : std_logic is basic_control(16); alias CONF_testpat_b : std_logic is basic_control(17); alias CONF_data_shifted_b : std_logic is basic_control(18); @@ -117,7 +117,7 @@ THE_INPUT_A : entity work.adc_input DEL_CFLAG => open, DEL_DIRECTION => CONF_del_direction, - DEL_LOADN => CONF_del_loadn, + DEL_LOADN => not CONF_del_load, DEL_MOVE => STROBE_del_move, DATA_OUT => data_in_a, @@ -138,7 +138,7 @@ THE_INPUT_B : entity work.adc_18bit_input CONF_DATA_SHIFTED => CONF_data_shifted_b, DEL_CFLAG => open, DEL_DIRECTION => CONF_del_direction, - DEL_LOADN => CONF_del_loadn, + DEL_LOADN => not CONF_del_load, DEL_MOVE => STROBE_del_move_b, diff --git a/adc/source/adc_input.vhd b/adc/source/adc_input.vhd index 5360c57..f041fff 100644 --- a/adc/source/adc_input.vhd +++ b/adc/source/adc_input.vhd @@ -63,10 +63,10 @@ THE_INPUT : entity work.input_4ch alignwd => SHIFT_ALIGN_IN, clkin => CLK_ADCRAW, sclk => clk_data, - data_cflag => del_cflag, - data_direction => del_direction, - data_loadn => del_loadn, - data_move => del_move, + data_cflag => DEL_CFLAG, + data_direction => DEL_DIRECTION, + data_loadn => DEL_LOADN, + data_move => DEL_MOVE, datain => ADC_DATA, q => data_in diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd index 8e9aa53..45aa855 100644 --- a/adc/source/adc_processor.vhd +++ b/adc/source/adc_processor.vhd @@ -334,13 +334,17 @@ end process; ------------------------------------------------------------------------------- proc_baseline_calc : process begin wait until rising_edge(CLK); - if CONTROL_baseline_reset = '1' or reg_CONFIG.baseline_fix = '1' then - baseline_averages <= x"000" & reg_CONFIG.baseline_fix_value; + if reg_CONFIG.baseline_fix = '1' then + baseline_averages <= (others => '0'); + baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_CONFIG.baseline_fix_value; + elsif CONTROL_baseline_reset = '1' then + baseline_averages <= (others => '0'); + baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_CONFIG.baseline_fix_value; last_CONTROL_baseline_reset <= CONTROL_baseline_reset; elsif last_CONTROL_baseline_reset = '1' and reg2_ram_remove = '1' then last_CONTROL_baseline_reset <= '0'; baseline_averages <= (others => '0'); - baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= resize(reg_ram_data_out(19 downto 0),20); + baseline_averages(to_integer(reg_CONFIG.averaging)+19 downto to_integer(reg_CONFIG.averaging)) <= reg_ram_data_out(19 downto 0); elsif reg2_ram_remove = '1' and (reg_ram_data_out(23) = '0' or reg_CONFIG.baseline_always_on = '1') then baseline_averages <= baseline_averages + resize(reg_ram_data_out(19 downto 0),32) -- 2.51.0 From 76482dc88614cb2632fdd115c333307f9dc29833 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 Jan 2025 12:35:23 +0100 Subject: [PATCH 13/16] update mimosis standalone design: add missing I2C port, reduce buffer size --- mimosis/code/MimosisInput.vhd | 4 ++-- mimosis/trb5sc_mimosis.vhd | 4 ++-- mimosis_standalone/config.vhd | 11 ++++++----- mimosis_standalone/trb5sc_mimosis.vhd | 22 ++++++++++++++-------- 4 files changed, 24 insertions(+), 17 deletions(-) diff --git a/mimosis/code/MimosisInput.vhd b/mimosis/code/MimosisInput.vhd index 5935f82..33c8f05 100644 --- a/mimosis/code/MimosisInput.vhd +++ b/mimosis/code/MimosisInput.vhd @@ -25,7 +25,7 @@ end entity; architecture arch of MimosisInput is constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; - constant WORD_LIMIT : integer := 8500; + constant WORD_LIMIT : integer := 4000; signal input_active_i : std_logic; signal data_i : std_logic_vector(15 downto 0); signal inp_i : std_logic_vector(7 downto 0); @@ -205,7 +205,7 @@ THE_FIFO : entity work.fifo_36x8k_oreg WrEn => buffer_write, RdEn => buffer_read, Reset => RESET, - AmFullThresh => "1000000000000", + AmFullThresh => "0010000000000", Q(31 downto 0) => buffer_dout, WCNT => buffer_fill, Empty => buffer_empty, diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index a8c2792..e842da2 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -455,8 +455,8 @@ begin PIN(4) <= MIMOSIS_SDA; PIN(3) <= MIMOSIS_SCL; - MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; - MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START diff --git a/mimosis_standalone/config.vhd b/mimosis_standalone/config.vhd index ea83682..c8cf18c 100644 --- a/mimosis_standalone/config.vhd +++ b/mimosis_standalone/config.vhd @@ -36,8 +36,8 @@ package config is -- -- 14: Debug - single fine time and the ROM addresses for the two transitions -- -- 15: Debug - complete carry chain dump - constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N - constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4095; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 constant USE_GBE : integer := c_YES; --Runs with 120 MHz instead of 100 MHz @@ -47,13 +47,13 @@ package config is constant USE_RXCLOCK : integer := c_NO; --Address settings - constant INIT_ADDRESS : std_logic_vector := x"F586"; - constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + constant INIT_ADDRESS : std_logic_vector := x"F575"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82"; constant INCLUDE_UART : integer := c_NO; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_ADC : integer := c_YES; - constant INCLUDE_I2C : integer := c_NO; + constant INCLUDE_I2C : integer := c_YES; constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic @@ -74,6 +74,7 @@ package config is constant PERIPH_TRIGGER_COUNT : integer := 0; constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; + constant CTS_NOREADOUT : integer := 1; --no data in readout from CTS --TODO: -- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; --Which external trigger module (ETM) to use? diff --git a/mimosis_standalone/trb5sc_mimosis.vhd b/mimosis_standalone/trb5sc_mimosis.vhd index a7d2d58..ac0c67b 100644 --- a/mimosis_standalone/trb5sc_mimosis.vhd +++ b/mimosis_standalone/trb5sc_mimosis.vhd @@ -43,7 +43,7 @@ entity trb5sc_mimosis is H6 : inout std_logic_vector(4 downto 0); H7 : inout std_logic_vector(4 downto 0); - PIN : out std_logic_vector(8 downto 1); + PIN : inout std_logic_vector(8 downto 1); MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; @@ -294,6 +294,7 @@ begin UP_DOWN_MODE => 0, UP_DOWN_LIMIT => 100, FIXED_DELAY => 100, + SLOWCTRL_BUFFER_SIZE => 1, NUMBER_OF_GBE_LINKS => 1, LINKS_ACTIVE => "0001", @@ -382,7 +383,8 @@ begin RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, RDO_HEADER_BUFFER_DEPTH => 9, - RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16, + RDO_SKIP_FIRST_BUFFER => CTS_NOREADOUT ) port map ( CLK => clk_sys, @@ -670,8 +672,8 @@ begin SPI_CLK_OUT => spi_clk, --Header --HEADER_IO => open, - -- HEADER_IO(7) => HDR_IO(6), - -- HEADER_IO(8) => HDR_IO(7), + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), ADDITIONAL_REG => add_reg, --ADC ADC_CS => ADC_NCS, @@ -739,11 +741,15 @@ begin -- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; -- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; - PIN(4) <= MIMOSIS_SDA; - PIN(3) <= MIMOSIS_SCL; - MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; - MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + -- PIN(4) <= MIMOSIS_SDA; + -- PIN(3) <= MIMOSIS_SCL; + -- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; + -- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; + + H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET -- 2.51.0 From 9e0138c0dff401e94ae60f390a3c7b61a37b8dc7 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 20 Feb 2026 17:04:32 +0100 Subject: [PATCH 14/16] fix I2C ouputs, add operation with 1,2,4 links --- mimosis/code/WordAlign.vhd | 66 ++++++++++++++++--- .../config_compile_frankfurt.pl | 6 +- mimosis_standalone/nodelist_frankfurt.txt | 7 ++ mimosis_standalone/trb5sc_mimosis.vhd | 14 ++-- 4 files changed, 73 insertions(+), 20 deletions(-) create mode 100644 mimosis_standalone/nodelist_frankfurt.txt diff --git a/mimosis/code/WordAlign.vhd b/mimosis/code/WordAlign.vhd index 2502428..e9a2fe0 100644 --- a/mimosis/code/WordAlign.vhd +++ b/mimosis/code/WordAlign.vhd @@ -41,14 +41,17 @@ architecture arch of WordAlign is alias CONF_fixalign : std_logic is control_reg(8); alias CONF_writeall : std_logic is control_reg(9); alias CONF_ignoreactive : std_logic is control_reg(10); + alias CONF_inactivelinks : std_logic_vector is control_reg(17 downto 16); signal bittime : integer range 0 to 31 := 0; signal word_update : std_logic_vector(7 downto 0); signal found_idle : std_logic_vector(7 downto 0) := (others => '0'); signal last_word_update, next_last_word_update : std_logic; - signal copycnt : integer range 0 to 4; - + signal copycnt : integer range 0 to 6; + signal fullsetcnt : integer range 0 to 7; + signal is_full_hdr : std_logic; + begin bittime <= bittime + 1 when rising_edge(CLK); @@ -91,27 +94,70 @@ end generate; next_last_word_update <= word_update(0) when rising_edge(CLK); last_word_update <= next_last_word_update when rising_edge(CLK); +is_full_hdr <= '1' when data_reg(0)(15 downto 8) = x"FE" and + data_reg(1)(15 downto 8) = x"FE" and + data_reg(2)(15 downto 8) = x"FE" and + data_reg(3)(15 downto 8) = x"FE" and + data_reg(4)(15 downto 8) = x"FE" and + data_reg(5)(15 downto 8) = x"FE" and + data_reg(6)(15 downto 8) = x"FE" and + data_reg(7)(15 downto 8) = x"FE" + else '0'; + + + PROC_COPY_MUX : process begin wait until rising_edge(CLK); doubleword_valid <= '0'; copycnt <= copycnt + 1; if last_word_update = '1' then - data_reg <= words; - copycnt <= 0; - elsif copycnt = 0 then + if CONF_inactivelinks = "00" then + data_reg <= words; + copycnt <= 3; + elsif CONF_inactivelinks = "01" then + data_reg(0 to 6) <= data_reg(1 to 7); + data_reg(1) <= words(0); + data_reg(3) <= words(2); + data_reg(5) <= words(4); + data_reg(7) <= words(6); + copycnt <= 1; + elsif CONF_inactivelinks = "10" then + data_reg(0 to 6) <= data_reg(1 to 7); + data_reg(3) <= words(0); + data_reg(7) <= words(4); + copycnt <= 1; + else + data_reg(0 to 6) <= data_reg(1 to 7); + data_reg(7) <= words(0); + copycnt <= 1; + end if; + elsif copycnt = 1 then + null; + elsif copycnt = 2 then + if is_full_hdr = '1' or fullsetcnt = 0 then + fullsetcnt <= 1 when CONF_inactivelinks = "01" + else 3 when CONF_inactivelinks = "10" + else 7; + else + fullsetcnt <= fullsetcnt - 1; + copycnt <= 0; + end if; + + elsif copycnt = 3 then doubleword <= data_reg(0)(15 downto 0) & data_reg(1)(15 downto 0); doubleword_valid <= '1'; - elsif copycnt = 1 then + elsif copycnt = 4 then doubleword <= data_reg(2)(15 downto 0) & data_reg(3)(15 downto 0); doubleword_valid <= '1'; - elsif copycnt = 2 then + elsif copycnt = 5 then doubleword <= data_reg(4)(15 downto 0) & data_reg(5)(15 downto 0); doubleword_valid <= '1'; - elsif copycnt = 3 then + elsif copycnt = 6 then doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0); doubleword_valid <= '1'; - elsif copycnt = 4 then - copycnt <= copycnt; + else + copycnt <= 0; + end if; end process; diff --git a/mimosis_standalone/config_compile_frankfurt.pl b/mimosis_standalone/config_compile_frankfurt.pl index d941a92..ad1bdd0 100644 --- a/mimosis_standalone/config_compile_frankfurt.pl +++ b/mimosis_standalone/config_compile_frankfurt.pl @@ -7,10 +7,10 @@ Speedgrade => '8', TOPNAME => "trb5sc_mimosis", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1710\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.12', -synplify_path => '/d/jspc29/lattice/synplify/V-2023.09-SP1/',#T-2022.09-SP2/', +lattice_path => '/d/jspc29/lattice/diamond/3.14', +synplify_path => '/d/jspc29/lattice/synplify/W-2024.09/',#T-2022.09-SP2/', -nodelist_file => '../nodelist_frankfurt.txt', +nodelist_file => 'nodelist_frankfurt.txt', pinout_file => 'trb5sc_hdmi', par_options => '../par.p2t', diff --git a/mimosis_standalone/nodelist_frankfurt.txt b/mimosis_standalone/nodelist_frankfurt.txt new file mode 100644 index 0000000..83f9f51 --- /dev/null +++ b/mimosis_standalone/nodelist_frankfurt.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[jspc85] +SYSTEM = linux +CORENUM = 8 +ENV = /d/jspc29/lattice/314_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/mimosis_standalone/workdir diff --git a/mimosis_standalone/trb5sc_mimosis.vhd b/mimosis_standalone/trb5sc_mimosis.vhd index ac0c67b..84c7ef7 100644 --- a/mimosis_standalone/trb5sc_mimosis.vhd +++ b/mimosis_standalone/trb5sc_mimosis.vhd @@ -43,7 +43,7 @@ entity trb5sc_mimosis is H6 : inout std_logic_vector(4 downto 0); H7 : inout std_logic_vector(4 downto 0); - PIN : inout std_logic_vector(8 downto 1); + PIN : out std_logic_vector(8 downto 1); MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; @@ -741,13 +741,13 @@ begin -- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; -- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; - -- PIN(4) <= MIMOSIS_SDA; - -- PIN(3) <= MIMOSIS_SCL; - -- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; - -- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; -PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; -PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +-- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC -- 2.51.0 From 6755c9d21bfad34086e0000d83ff6c4128f3f797 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 2 Mar 2026 12:06:24 +0100 Subject: [PATCH 15/16] add files for Mimosis FEB readout --- .gitignore | 1 + mimosis_feb/compile.pl | 1 + mimosis_feb/config.vhd | 172 +++++ mimosis_feb/config_compile_frankfurt.pl | 25 + mimosis_feb/nodelist_frankfurt.txt | 7 + mimosis_feb/par.p2t | 69 ++ mimosis_feb/trb5sc_mimosis.lpf | 53 ++ mimosis_feb/trb5sc_mimosis.prj | 302 ++++++++ mimosis_feb/trb5sc_mimosis.vhd | 881 ++++++++++++++++++++++++ pinout/trb5sc_mimosisfeb.lpf | 365 ++++++++++ 10 files changed, 1876 insertions(+) create mode 120000 mimosis_feb/compile.pl create mode 100644 mimosis_feb/config.vhd create mode 100644 mimosis_feb/config_compile_frankfurt.pl create mode 100644 mimosis_feb/nodelist_frankfurt.txt create mode 100644 mimosis_feb/par.p2t create mode 100644 mimosis_feb/trb5sc_mimosis.lpf create mode 100644 mimosis_feb/trb5sc_mimosis.prj create mode 100644 mimosis_feb/trb5sc_mimosis.vhd create mode 100644 pinout/trb5sc_mimosisfeb.lpf diff --git a/.gitignore b/.gitignore index b269753..81cc209 100644 --- a/.gitignore +++ b/.gitignore @@ -39,3 +39,4 @@ archv _math_real.vhd transcript */testbench/*.vstf +stdout* diff --git a/mimosis_feb/compile.pl b/mimosis_feb/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/mimosis_feb/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/mimosis_feb/config.vhd b/mimosis_feb/config.vhd new file mode 100644 index 0000000..c8cf18c --- /dev/null +++ b/mimosis_feb/config.vhd @@ -0,0 +1,172 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4095; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_YES; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F575"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 16; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 16; + + + + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 0; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 0; + constant TRIGGER_ADDON_COUNT : integer := 1; + constant PERIPH_TRIGGER_COUNT : integer := 0; + constant ADDON_LINE_COUNT : integer := 1; --36 with Padiwa, 22 with RJ-adapter + constant CTS_OUTPUT_MULTIPLEXERS : integer := 0; + constant CTS_NOREADOUT : integer := 1; --no data in readout from CTS +--TODO: +-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); + + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type hub_ct is array(0 to 16) of integer; + type intlist_t is array(0 to 7) of integer; + + + constant INTERFACE_NUM : integer := 1; + constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + + constant cts_rdo_additional_ports : integer := 1; --for internal endpoint + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000100"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(0,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/mimosis_feb/config_compile_frankfurt.pl b/mimosis_feb/config_compile_frankfurt.pl new file mode 100644 index 0000000..3f1a988 --- /dev/null +++ b/mimosis_feb/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_mimosis", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.14', +synplify_path => '/d/jspc29/lattice/synplify/W-2024.09/',#T-2022.09-SP2/', + +nodelist_file => 'nodelist_frankfurt.txt', +pinout_file => 'trb5sc_mimosisfeb', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 1, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/mimosis_feb/nodelist_frankfurt.txt b/mimosis_feb/nodelist_frankfurt.txt new file mode 100644 index 0000000..a8f55a5 --- /dev/null +++ b/mimosis_feb/nodelist_frankfurt.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[jspc85] +SYSTEM = linux +CORENUM = 8 +ENV = /d/jspc29/lattice/314_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/mimosis_feb/workdir diff --git a/mimosis_feb/par.p2t b/mimosis_feb/par.p2t new file mode 100644 index 0000000..acca99b --- /dev/null +++ b/mimosis_feb/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 20 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/mimosis_feb/trb5sc_mimosis.lpf b/mimosis_feb/trb5sc_mimosis.lpf new file mode 100644 index 0000000..9d59a07 --- /dev/null +++ b/mimosis_feb/trb5sc_mimosis.lpf @@ -0,0 +1,53 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +# FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +MULTICYCLE FROM CELL "THE_HUB/THE_HUB/reset_i" 15 ns; + + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +# MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; +BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; + +BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; +BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; + diff --git a/mimosis_feb/trb5sc_mimosis.prj b/mimosis_feb/trb5sc_mimosis.prj new file mode 100644 index 0000000..34ed411 --- /dev/null +++ b/mimosis_feb/trb5sc_mimosis.prj @@ -0,0 +1,302 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_mimosis.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ram_dp_true_2kx9.vhd" + + +add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" +add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" + +add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd" +add_file -vhdl -lib work "../mimosis/cores/testout.vhd" +add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd" +add_file -vhdl -lib work "../mimosis/code/InputStage.vhd" +add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd" +add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd" + + + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/mimosis_feb/trb5sc_mimosis.vhd b/mimosis_feb/trb5sc_mimosis.vhd new file mode 100644 index 0000000..84c7ef7 --- /dev/null +++ b/mimosis_feb/trb5sc_mimosis.vhd @@ -0,0 +1,881 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +-- use work.med_sync_define.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.cts_pkg.all; + + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --HDMI AddOn + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(3 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of trb5sc_mimosis is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal clk_40, clk_80, clk_160, clk_320 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + signal reboot_from_gbe : std_logic; + signal reset_via_gbe : std_logic; + + + + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + signal rdack, wrack : std_logic; + + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal gbe_status : std_logic_vector(15 downto 0); + + signal clk_350, clk_50, clk_200bypass : std_logic; + + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); + signal trigger_busy_i : std_logic; + signal cts_trigger_out : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + -- signal cts_ext_trigger : std_logic; + -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + -- signal cts_ext_control : std_logic_vector(31 downto 0); + -- signal cts_ext_debug : std_logic_vector(31 downto 0); + -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00"; + + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); + + signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); + signal cts_rdo_rx : READOUT_RX; + + + signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); + signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0); + + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + + + signal inp_i : std_logic_vector( 7 downto 0); + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + +begin + + -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => make_reset,--med2int(0).stat_op(13), + SEND_RESET_IN => '0', --med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40, + CLKOS3=> clk_80 + ); + + H3(3) <= clk_320; + + -- For IPHC Proxy + -- RJ(0) <= clk_40; + -- For IKF Proxy + H1(4) <= clk_40; + + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- + GBE : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + SLOWCTRL_BUFFER_SIZE => 1, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" + ) + + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_125, + RESET => reset_i, + GSR_N => GSR_N, + + TRIGGER_IN => cts_rdo_rx.data_valid, + + SD_PRSNT_N_IN(0) => SFP_MOD_0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, + + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + + MAKE_RESET_OUT => reset_via_gbe, + STATUS_OUT => gbe_status, --open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- + THE_HUB : trb_net16_hub_streaming_port_sctrl_cts + generic map( + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + BROADCAST_BITMASK => x"7E", + CLOCK_FREQUENCY => 100, + USE_ONEWIRE => c_I2C, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + RDO_HEADER_BUFFER_DEPTH => 9, + RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16, + RDO_SKIP_FIRST_BUFFER => CTS_NOREADOUT + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media interfacces --------------------------------------------------------------- + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open, + MED_STAT_OP(2 downto 0) => ERROR_NC, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 3) => (others => '0'), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => open, + + -- Gbe Read-out Path --------------------------------------------------------------- + --Event information coming from CTS for GbE + GBE_CTS_NUMBER_OUT => gbe_cts_number, + GBE_CTS_CODE_OUT => gbe_cts_code, + GBE_CTS_INFORMATION_OUT => gbe_cts_information, + GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, + --Information sent to CTS + GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, + -- Data from Frontends + GBE_FEE_DATA_OUT => gbe_fee_data, + GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, + GBE_FEE_READ_IN => gbe_fee_read, + GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + GBE_FEE_BUSY_OUT => gbe_fee_busy, + + -- CTS Request Sending ------------------------------------------------------------- + --LVL1 trigger + CTS_TRG_SEND_IN => cts_trg_send, + CTS_TRG_TYPE_IN => cts_trg_type, + CTS_TRG_NUMBER_IN => cts_trg_number, + CTS_TRG_INFORMATION_IN => cts_trg_information, + CTS_TRG_RND_CODE_IN => cts_trg_code, + CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits, + CTS_TRG_BUSY_OUT => cts_trg_busy, + --IPU Channel + CTS_IPU_SEND_IN => cts_ipu_send, + CTS_IPU_TYPE_IN => cts_ipu_type, + CTS_IPU_NUMBER_IN => cts_ipu_number, + CTS_IPU_INFORMATION_IN => cts_ipu_information, + CTS_IPU_RND_CODE_IN => cts_ipu_code, + -- Receiver port + CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits, + CTS_IPU_BUSY_OUT => cts_ipu_busy, + + -- CTS Data Readout ---------------------------------------------------------------- + --Trigger to CTS out + RDO_TRIGGER_IN => cts_trigger_out, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, + + --Data from CTS in + RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, + RDO_DATA_IN => cts_rdo_data, + RDO_DATA_WRITE_IN => cts_rdo_write, + RDO_DATA_FINISHED_IN => cts_rdo_finished, + --Data from additional modules + RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional, + RDO_ADDITIONAL_DATA => cts_rdo_additional_data, + RDO_ADDITIONAL_WRITE => cts_rdo_additional_write, + RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished, + + -- Slow Control -------------------------------------------------------------------- + COMMON_STAT_REGS => open, + COMMON_CTRL_REGS => common_ctrl_reg, + ONEWIRE => open, + ONEWIRE_MONITOR_IN => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, + EXTERNAL_SEND_RESET => reset_via_gbe, + + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + + gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate + cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; + cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; + + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; + + end generate; + + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + +--------------------------------------------------------------------------- +-- CTS +--------------------------------------------------------------------------- + THE_CTS : CTS + generic map ( + EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic + PLATTFORM => 5, --TRB5sc + OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, + ADDON_GROUPS => 1, + ADDON_GROUP_UPPER => (0, others => 0) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + + TRIGGER_BUSY_OUT => trigger_busy_i, + TIME_REFERENCE_OUT => cts_trigger_out, + + ADDON_TRIGGERS_IN => cts_addon_triggers_in, + ADDON_GROUP_ACTIVITY_OUT => open, + ADDON_GROUP_SELECTED_OUT => open, + + EXT_TRIGGER_IN => '0', + EXT_STATUS_IN => (others => '0'), + EXT_CONTROL_OUT => open, + EXT_HEADER_BITS_IN => (others => '0'), + EXT_FORCE_TRIGGER_INFO_IN => (others => '0'), + + PERIPH_TRIGGER_IN => (others => '0'), + + OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out, + + CTS_TRG_SEND_OUT => cts_trg_send, + CTS_TRG_TYPE_OUT => cts_trg_type, + CTS_TRG_NUMBER_OUT => cts_trg_number, + CTS_TRG_INFORMATION_OUT => cts_trg_information, + CTS_TRG_RND_CODE_OUT => cts_trg_code, + CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits, + CTS_TRG_BUSY_IN => cts_trg_busy, + + CTS_IPU_SEND_OUT => cts_ipu_send, + CTS_IPU_TYPE_OUT => cts_ipu_type, + CTS_IPU_NUMBER_OUT => cts_ipu_number, + CTS_IPU_INFORMATION_OUT => cts_ipu_information, + CTS_IPU_RND_CODE_OUT => cts_ipu_code, + CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits, + CTS_IPU_BUSY_IN => cts_ipu_busy, + + CTS_REGIO_ADDR_IN => buscts_rx.addr, + CTS_REGIO_DATA_IN => buscts_rx.data, + CTS_REGIO_READ_ENABLE_IN => buscts_rx.read, + CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write, + CTS_REGIO_DATA_OUT => buscts_tx.data, + CTS_REGIO_DATAREADY_OUT => buscts_tx.rack, + CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, + CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, + + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, + + FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, + FEE_DATA_OUT => cts_rdo_data, + FEE_DATA_WRITE_OUT => cts_rdo_write, + FEE_DATA_FINISHED_OUT => cts_rdo_finished + ); + + -- cts_addon_triggers_in(11 downto 4) <= HDR_IO(23 downto 16); + -- cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i; + + buscts_tx.nack <= '0'; + buscts_tx.ack <= '0'; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + -- BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(1) => buscts_rx, + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busgbeip_rx, + BUS_RX(5) => busgbereg_rx, + BUS_RX(6) => busi2c_rx, + + BUS_TX(0) => bustools_tx, + -- BUS_TX(1) => bussci_tx, + BUS_TX(1) => buscts_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busgbeip_tx, + BUS_TX(5) => busgbereg_tx, + BUS_TX(6) => busi2c_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393", + NUM_COINCIDENCES => 4, + NUM_MULTIPLICITIES => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS(11 downto 0) => x"000", + MONITOR_INPUTS(15 downto 12) => x"0", + TRIG_GEN_INPUTS(11 downto 0) => x"000", + TRIG_GEN_INPUTS(15 downto 12) => x"0", + + TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i, + + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- + THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) + ); + +-- I2C signal open collector driver +-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; + + PIN(4) <= MIMOSIS_SDA; + PIN(3) <= MIMOSIS_SCL; + MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; + MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; + +-- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; + + + H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC + PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START + PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + + PROC_I2C_REGS : process + begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; + end if; + end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_SFP_GREEN <= not (gbe_status(0) and gbe_status(1) and gbe_status(2)); --'0'; + LED_SFP_YELLOW <= gbe_status(8); + LED_SFP_RED <= not (gbe_status(3) or gbe_status(4)); --'0'; + + -- LED_SFP_GREEN <= not med2int(0).stat_op(9); + -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- cts_rdo_additional(0).data_finished <= '1'; +-- cts_rdo_additional(0).data_write <= '0'; +-- cts_rdo_additional(0).busy_release <= '1'; + + +end architecture; diff --git a/pinout/trb5sc_mimosisfeb.lpf b/pinout/trb5sc_mimosisfeb.lpf new file mode 100644 index 0000000..f6912b2 --- /dev/null +++ b/pinout/trb5sc_mimosisfeb.lpf @@ -0,0 +1,365 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ;#BACKGROUND_RECONFIG=ON +BANK 0 VCCIO 2.5 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 4 VCCIO 3.3 V; +BANK 6 VCCIO 2.5 V; +BANK 7 VCCIO 2.5 V; +BANK 8 VCCIO 3.3 V; +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_125" SITE "AD1" ;#was "OSC_CORE_125" +LOCATE COMP "CLK_200" SITE "AD32" ;#was "OSC_CORE_200" +LOCATE COMP "CLK_EXT" SITE "C28" ;#was "EXT_CLOCK" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +# LOCATE COMP "ENPIRION_CLOCK" SITE "AM31"; +# IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33; +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3" ; +LOCATE COMP "TRIG_IN_RJ45" SITE "AC2" ; +DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ; +IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +LOCATE COMP "SPARE[0]" SITE "AC3" ; +LOCATE COMP "SPARE[1]" SITE "AB1" ; +DEFINE PORT GROUP "SPARE_group" "SPARE*" ; +IOBUF GROUP "SPARE_group" IO_TYPE=LVDS ; +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_TX_DIS" SITE "AH28" ; +LOCATE COMP "SFP_LOS" SITE "AK29" ; +LOCATE COMP "SFP_MOD_0" SITE "AG28" ; +IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# LOCATE COMP "SFP_RATE_SEL" SITE "AG30"; +# LOCATE COMP "SFP_TX_FAULT" SITE "AH30"; +# LOCATE COMP "SFP_MOD_1" SITE "AG29"; +# LOCATE COMP "SFP_MOD_2" SITE "AJ28"; +################################################################# +# Frontend +################################################################# + +LOCATE COMP "SCA2_RST_B" SITE "D18" ; +LOCATE COMP "SCA_RST_B" SITE "F18" ; +IOBUF PORT "SCA_RST_B" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +IOBUF PORT "SCA2_RST_B" IO_TYPE=LVCMOS25 PULLMODE=NONE ; + + +#LOCATE COMP "FE_GPIO[0]" SITE "A18" ; +#LOCATE COMP "FE_GPIO[1]" SITE "C18" ; +#LOCATE COMP "FE_GPIO[4]" SITE "A19" ; +#LOCATE COMP "FE_GPIO[5]" SITE "B19" ; +#LOCATE COMP "FE_GPIO[6]" SITE "C19" ; +#LOCATE COMP "FE_GPIO[7]" SITE "D19" ; +#LOCATE COMP "FE_GPIO[8]" SITE "E19" ; +#LOCATE COMP "FE_GPIO[9]" SITE "F19" ; +#LOCATE COMP "FE_GPIO[10]" SITE "A20" ; +#LOCATE COMP "FE_GPIO[11]" SITE "C20" ; +#DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; +#IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +LOCATE COMP "FE_CLK[1]" SITE "C5" ; +LOCATE COMP "FE_CLK[2]" SITE "P5" ; +DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; +IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +# LOCATE COMP "FE_CLK_2_N" SITE "P4"; +# LOCATE COMP "FE_CLK_1_N" SITE "D5"; +# LOCATE COMP "FE_DIFF_0_N" SITE "T28"; +# LOCATE COMP "FE_DIFF_1_N" SITE "U28"; +# LOCATE COMP "FE_DIFF_2_N" SITE "P30"; +# LOCATE COMP "FE_DIFF_3_N" SITE "T30"; +# LOCATE COMP "FE_DIFF_4_N" SITE "P32"; +# LOCATE COMP "FE_DIFF_5_N" SITE "U30"; +# LOCATE COMP "FE_DIFF_6_N" SITE "T31"; +# LOCATE COMP "FE_DIFF_7_N" SITE "Y30"; +# LOCATE COMP "FE_DIFF_8_N" SITE "U32"; +# LOCATE COMP "FE_DIFF_9_N" SITE "W32"; +# LOCATE COMP "FE_DIFF_10_N" SITE "Y27"; +# LOCATE COMP "FE_DIFF_11_N" SITE "W28"; +# LOCATE COMP "FE_DIFF_12_N" SITE "W29"; +# LOCATE COMP "FE_DIFF_13_N" SITE "AC27"; +# LOCATE COMP "FE_DIFF_14_N" SITE "AB27"; +# LOCATE COMP "FE_DIFF_15_N" SITE "AD26"; +# LOCATE COMP "FE_DIFF_16_N" SITE "E29"; +# LOCATE COMP "FE_DIFF_17_N" SITE "F28"; +# LOCATE COMP "FE_DIFF_18_N" SITE "C31"; +# LOCATE COMP "FE_DIFF_19_N" SITE "D31"; +# LOCATE COMP "FE_DIFF_20_N" SITE "E30"; +# LOCATE COMP "FE_DIFF_21_N" SITE "D32"; +# LOCATE COMP "FE_DIFF_22_N" SITE "E32"; +# LOCATE COMP "FE_DIFF_23_N" SITE "H32"; +# LOCATE COMP "FE_DIFF_24_N" SITE "H30"; +# LOCATE COMP "FE_DIFF_25_N" SITE "K30"; +# LOCATE COMP "FE_DIFF_26_N" SITE "J32"; +# LOCATE COMP "FE_DIFF_27_N" SITE "L32"; +# LOCATE COMP "FE_DIFF_28_N" SITE "L30"; +# LOCATE COMP "FE_DIFF_29_N" SITE "K29"; +# LOCATE COMP "FE_DIFF_30_N" SITE "H28"; +# LOCATE COMP "FE_DIFF_31_N" SITE "K26"; +# LOCATE COMP "FE_DIFF_32_N" SITE "E4"; +# LOCATE COMP "FE_DIFF_33_N" SITE "F5"; +# LOCATE COMP "FE_DIFF_34_N" SITE "C2"; +# LOCATE COMP "FE_DIFF_35_N" SITE "D2"; +# LOCATE COMP "FE_DIFF_36_N" SITE "E3"; +# LOCATE COMP "FE_DIFF_37_N" SITE "D1"; +# LOCATE COMP "FE_DIFF_38_N" SITE "E1"; +# LOCATE COMP "FE_DIFF_39_N" SITE "H1"; +# LOCATE COMP "FE_DIFF_40_N" SITE "H3"; +# LOCATE COMP "FE_DIFF_41_N" SITE "K3"; +# LOCATE COMP "FE_DIFF_42_N" SITE "J1"; +# LOCATE COMP "FE_DIFF_43_N" SITE "L1"; +# LOCATE COMP "FE_DIFF_44_N" SITE "L3"; +# LOCATE COMP "FE_DIFF_45_N" SITE "K4"; +# LOCATE COMP "FE_DIFF_46_N" SITE "H5"; +# LOCATE COMP "FE_DIFF_47_N" SITE "K7"; +# LOCATE COMP "FE_DIFF_48_N" SITE "T5"; +# LOCATE COMP "FE_DIFF_49_N" SITE "U5"; +# LOCATE COMP "FE_DIFF_50_N" SITE "P3"; +# LOCATE COMP "FE_DIFF_51_N" SITE "T3"; +# LOCATE COMP "FE_DIFF_52_N" SITE "P1"; +# LOCATE COMP "FE_DIFF_53_N" SITE "U3"; +# LOCATE COMP "FE_DIFF_54_N" SITE "T2"; +# LOCATE COMP "FE_DIFF_55_N" SITE "Y3"; +# LOCATE COMP "FE_DIFF_56_N" SITE "U1"; +# LOCATE COMP "FE_DIFF_57_N" SITE "W1"; +# LOCATE COMP "FE_DIFF_58_N" SITE "Y6"; +# LOCATE COMP "FE_DIFF_59_N" SITE "W5"; +# LOCATE COMP "FE_DIFF_60_N" SITE "W4"; +# LOCATE COMP "FE_DIFF_61_N" SITE "AC6"; +# LOCATE COMP "FE_DIFF_62_N" SITE "AB6"; +# LOCATE COMP "FE_DIFF_63_N" SITE "AD7"; +LOCATE COMP "H01_D7" SITE "R29" ; #"FE_DIFF[0]" +LOCATE COMP "H01_D3" SITE "T29" ; #"FE_DIFF[1]" +LOCATE COMP "H00_D1" SITE "P31" ; #"FE_DIFF[2]" +LOCATE COMP "H11_D1" SITE "R30" ; #"FE_DIFF[3]" +LOCATE COMP "H00_D3" SITE "N32" ; #"FE_DIFF[4]" +LOCATE COMP "H00_D5" SITE "U31" ; #"FE_DIFF[5]" +LOCATE COMP "H11_D3" SITE "R32" ; #"FE_DIFF[6]" +LOCATE COMP "H01_D1" SITE "W30" ; #"FE_DIFF[7]" +LOCATE COMP "H01_D5" SITE "T32" ; #"FE_DIFF[8]" +LOCATE COMP "H01_D6" SITE "V32" ; #"FE_DIFF[9]" +LOCATE COMP "H00_D7" SITE "Y26" ; #"FE_DIFF[10]" +LOCATE COMP "H01_D2" SITE "Y28" ; #"FE_DIFF[11]" +LOCATE COMP "H00_D0" SITE "Y29" ; #"FE_DIFF[12]" +LOCATE COMP "H11_D0" SITE "AB26" ; #"FE_DIFF[13]" +LOCATE COMP "H10_D7" SITE "AB28" ; #"FE_DIFF[14]" +LOCATE COMP "H00_D2" SITE "AC26" ; #"FE_DIFF[15]" +LOCATE COMP "H10_D5" SITE "D29" ; #"FE_DIFF[16]" +LOCATE COMP "H00_D4" SITE "F29" ; #"FE_DIFF[17]" +LOCATE COMP "H11_D2" SITE "B32" ; #"FE_DIFF[18]" +LOCATE COMP "H01_D0" SITE "D30" ; #"FE_DIFF[19]" +LOCATE COMP "H10_D1" SITE "F30" ; #"FE_DIFF[20]" +LOCATE COMP "H01_D4" SITE "C32" ; #"FE_DIFF[21]" +LOCATE COMP "H10_D3" SITE "F31" ; #"FE_DIFF[22]" +LOCATE COMP "H00_D6" SITE "F32" ; #"FE_DIFF[23]" +LOCATE COMP "H10_D6" SITE "H31" ; #"FE_DIFF[24]" +LOCATE COMP "H11_D7" SITE "J30" ; #"FE_DIFF[25]" +LOCATE COMP "H10_D4" SITE "K31" ; #"FE_DIFF[26]" +LOCATE COMP "H11_D5" SITE "K32" ; #"FE_DIFF[27]" +LOCATE COMP "H11_D6" SITE "L31" ; #"FE_DIFF[28]" +LOCATE COMP "H10_D0" SITE "J29" ; #"FE_DIFF[29]" +LOCATE COMP "H11_D4" SITE "H27" ; #"FE_DIFF[30]" +LOCATE COMP "H10_D2" SITE "K27" ; #"FE_DIFF[31]" +LOCATE COMP "FE_CLK[3]" SITE "D4" ; #"FE_DIFF[32]" +LOCATE COMP "V10_D7" SITE "F4" ; #"FE_DIFF[33]" +LOCATE COMP "SCA2_RX" SITE "B1" ; #"FE_DIFF[34]" +LOCATE COMP "SCA2_TX" SITE "D3" ; #"FE_DIFF[35]" +LOCATE COMP "SCA2_CLK" SITE "F3" ; #"FE_DIFF[36]" +LOCATE COMP "V10_D5" SITE "C1" ; #"FE_DIFF[37]" +#LOCATE COMP "V_D" SITE "F2" ; #"FE_DIFF[38]" +LOCATE COMP "V10_D1" SITE "F1" ; #"FE_DIFF[39]" +LOCATE COMP "V01_D6" SITE "H2" ; #"FE_DIFF[40]" +LOCATE COMP "V00_D3" SITE "J3" ; #"FE_DIFF[41]" +LOCATE COMP "V10_D3" SITE "K2" ; #"FE_DIFF[42]" +LOCATE COMP "V10_D4" SITE "K1" ; #"FE_DIFF[43]" +LOCATE COMP "SCA_RX" SITE "L2" ; #"FE_DIFF[44]" +LOCATE COMP "V10_D6" SITE "J4" ; #"FE_DIFF[45]" +LOCATE COMP "SCA_CLK" SITE "H6" ; #"FE_DIFF[46]" +LOCATE COMP "V00_D7" SITE "K6" ; #"FE_DIFF[47]" +LOCATE COMP "V01_D2" SITE "R4" ; #"FE_DIFF[48]" +LOCATE COMP "SCA_TX" SITE "T4" ; #"FE_DIFF[49]" +LOCATE COMP "V00_D5" SITE "P2" ; #"FE_DIFF[50]" +LOCATE COMP "V00_D1" SITE "R3" ; #"FE_DIFF[51]" +LOCATE COMP "V11_D6" SITE "N1" ; #"FE_DIFF[52]" +LOCATE COMP "V01_D4" SITE "U2" ; #"FE_DIFF[53]" +LOCATE COMP "V11_D2" SITE "R1" ; #"FE_DIFF[54]" +LOCATE COMP "V10_D0" SITE "W3" ; #"FE_DIFF[55]" +LOCATE COMP "V00_D2" SITE "T1" ; #"FE_DIFF[56]" +LOCATE COMP "V00_D0" SITE "V1" ; #"FE_DIFF[57]" +LOCATE COMP "V01_D0" SITE "Y7" ; #"FE_DIFF[58]" +LOCATE COMP "V10_D2" SITE "Y5" ; #"FE_DIFF[59]" +LOCATE COMP "V00_D6" SITE "Y4" ; #"FE_DIFF[60]" +LOCATE COMP "V00_D4" SITE "AB7" ; #"FE_DIFF[61]" +LOCATE COMP "V11_D4" SITE "AB5" ; #"FE_DIFF[62]" +LOCATE COMP "V11_D0" SITE "AC7" ; #"FE_DIFF[63]" + +DEFINE PORT GROUP "H0_group" "H0*" ; +DEFINE PORT GROUP "H1_group" "H1*" ; +DEFINE PORT GROUP "V0_group" "V0*" ; +DEFINE PORT GROUP "V1_group" "V1*" ; + + +IOBUF GROUP "H0_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF GROUP "H1_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF GROUP "V0_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF GROUP "V1_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "SCA_TX" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "SCA2_TX" IO_TYPE=LVDS DIFFRESISTOR=100 ; +IOBUF PORT "SCA_RX" IO_TYPE=LVDS ; +IOBUF PORT "SCA2_RX" IO_TYPE=LVDS ; +IOBUF PORT "SCA_CLK" IO_TYPE=LVDS ; +IOBUF PORT "SCA2_CLK" IO_TYPE=LVDS ; + + +################################################################# +# Temperature, Flash & ID +################################################################# +LOCATE COMP "I2C_SDA" SITE "A11" ; +LOCATE COMP "I2C_SCL" SITE "B11" ; +LOCATE COMP "TMP_ALERT" SITE "C11" ; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ; +LOCATE COMP "PROGRAMN" SITE "AH1" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 DRIVE=8 ; +LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16" ; +IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ; +LOCATE COMP "FLASH_HOLD" SITE "AL1" ; +LOCATE COMP "FLASH_MISO" SITE "AJ2" ; +LOCATE COMP "FLASH_MOSI" SITE "AK2" ; +LOCATE COMP "FLASH_NCS" SITE "AJ3" ; +LOCATE COMP "FLASH_SCLK" SITE "AJ1" ; +LOCATE COMP "FLASH_WP" SITE "AM2" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "ADC_MISO" SITE "AK3" ; +LOCATE COMP "ADC_MOSI" SITE "AL3" ; +LOCATE COMP "ADC_NCS" SITE "AH3" ; +LOCATE COMP "ADC_SCLK" SITE "AG3" ; +IOBUF PORT "ADC_SCLK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "ADC_NCS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MOSI" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MISO" IO_TYPE=LVTTL33 PULLMODE=UP ; +################################################################# +# LED +################################################################# +LOCATE COMP "LED_SFP_YELLOW" SITE "AG32" ; +LOCATE COMP "LED_SFP_GREEN" SITE "AK30" ; +LOCATE COMP "LED_SFP_RED" SITE "AH32" ; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; +LOCATE COMP "LED[1]" SITE "A26" ; +LOCATE COMP "LED[2]" SITE "B26" ; +LOCATE COMP "LED[3]" SITE "A28" ; +LOCATE COMP "LED[4]" SITE "A29" ; +LOCATE COMP "LED[5]" SITE "A30" ; +LOCATE COMP "LED[6]" SITE "A31" ; +LOCATE COMP "LED[7]" SITE "B29" ; +LOCATE COMP "LED[8]" SITE "B30" ; +IOBUF PORT "LED[1]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[2]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[3]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[4]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[5]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[6]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[7]" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED[8]" IO_TYPE=LVCMOS25 ; +LOCATE COMP "LED_RJ_GREEN[0]" SITE "AK32" ; +LOCATE COMP "LED_RJ_RED[0]" SITE "AJ32" ; +LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30" ; +LOCATE COMP "LED_RJ_GREEN[1]" SITE "AM30" ; +LOCATE COMP "LED_RJ_RED[1]" SITE "AL30" ; +IOBUF PORT "LED_RJ_GREEN[0]" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED[0]" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_GREEN[1]" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED[1]" IO_TYPE=LVTTL33 ; + +################################################################# +# Test & Other IO (v2) +################################################################# + #connector pin on v1 +LOCATE COMP "HDR_IO_0" SITE "A23"; #on HDR_0 +LOCATE COMP "HDR_IO_1" SITE "A22"; #on HDR_1 +LOCATE COMP "HDR_IO_2" SITE "C22"; #on HDR_6 +LOCATE COMP "HDR_IO_3" SITE "A24"; #on HDR_3 +LOCATE COMP "HDR_IO_4" SITE "B23"; #on HDR_5 +LOCATE COMP "HDR_IO_5" SITE "A25"; #n/a +LOCATE COMP "HDR_IO_6" SITE "B22"; #on HDR_2 +LOCATE COMP "HDR_IO_7" SITE "D24"; #on HDR_9 +LOCATE COMP "HDR_IO_8" SITE "C23"; #on HDR_4 +LOCATE COMP "HDR_IO_9" SITE "C24"; #on HDR_7 +LOCATE COMP "HDR_IO_10" SITE "D25"; #n/a +LOCATE COMP "HDR_IO_11" SITE "D26"; #n/a +LOCATE COMP "HDR_IO_12" SITE "B25"; #n/a +LOCATE COMP "HDR_IO_13" SITE "C25"; #n/a +LOCATE COMP "HDR_IO_14" SITE "E25"; #n/a +LOCATE COMP "HDR_IO_15" SITE "F24"; #n/a +LOCATE COMP "HDR_IO_16" SITE "F23"; #on HDR_12 +LOCATE COMP "HDR_IO_17" SITE "D23"; #on HDR_8 +LOCATE COMP "HDR_IO_18" SITE "E23"; #on HDR_10 +LOCATE COMP "HDR_IO_19" SITE "E22"; #on HDR_13 +LOCATE COMP "HDR_IO_20" SITE "D22"; #on HDR_11 +LOCATE COMP "HDR_IO_21" SITE "F25"; #n/a +LOCATE COMP "HDR_IO_22" SITE "F22"; #on HDR_15 +LOCATE COMP "HDR_IO_23" SITE "F20"; #on HDR_14 + +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +################################################################# +# Test & Other IO - from version 1 boards (TEST pins have not been reassigned) +################################################################# +LOCATE COMP "TEST_1" SITE "A7"; +LOCATE COMP "TEST_2" SITE "A5"; +LOCATE COMP "TEST_3" SITE "A4"; +LOCATE COMP "TEST_4" SITE "A3"; +LOCATE COMP "TEST_5" SITE "A2"; +LOCATE COMP "TEST_6" SITE "B3"; +LOCATE COMP "TEST_7" SITE "B4"; +LOCATE COMP "TEST_8" SITE "B7"; +LOCATE COMP "TEST_9" SITE "C7"; +LOCATE COMP "TEST_10" SITE "C8"; +LOCATE COMP "TEST_11" SITE "D7"; +LOCATE COMP "TEST_12" SITE "D8"; +LOCATE COMP "TEST_13" SITE "E8"; +LOCATE COMP "TEST_14" SITE "F8"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8; + + +#LOCATE COMP "HDR_IO_0" SITE "A23"; +#LOCATE COMP "HDR_IO_1" SITE "A22"; +#LOCATE COMP "HDR_IO_2" SITE "B22"; +#LOCATE COMP "HDR_IO_3" SITE "A24"; +#LOCATE COMP "HDR_IO_4" SITE "C23"; +#LOCATE COMP "HDR_IO_5" SITE "B23"; +#LOCATE COMP "HDR_IO_6" SITE "C22"; +#LOCATE COMP "HDR_IO_7" SITE "C24"; +#LOCATE COMP "HDR_IO_8" SITE "D23"; +#LOCATE COMP "HDR_IO_9" SITE "D24"; +#LOCATE COMP "HDR_IO_10" SITE "E23"; +#LOCATE COMP "HDR_IO_11" SITE "D22"; +#LOCATE COMP "HDR_IO_12" SITE "F23"; +#LOCATE COMP "HDR_IO_13" SITE "E22"; +#LOCATE COMP "HDR_IO_14" SITE "F20"; +#LOCATE COMP "HDR_IO_15" SITE "F22"; +#DEFINE PORT GROUP "HDR_group" "HDR*" ; +#IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +LOCATE COMP "BACK_GPIO[0]" SITE "P28" ; +LOCATE COMP "BACK_GPIO[1]" SITE "P29" ; +LOCATE COMP "BACK_GPIO[2]" SITE "R27" ; +LOCATE COMP "BACK_GPIO[3]" SITE "T27" ; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "FE_CLK[1]" IO_TYPE=LVDS ; -- 2.51.0 From fa4c9078c75328d3ebdd5cf1fa7a7331b11dd206 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 31 Mar 2026 13:09:09 +0200 Subject: [PATCH 16/16] add Mimosis readout for FEB --- mimosis/code/InputStageMulti.vhd | 246 ++++++++++++++++++++ mimosis/code/MimosisInputMulti.vhd | 356 +++++++++++++++++++++++++++++ mimosis_feb/par.p2t | 2 +- mimosis_feb/trb5sc_mimosis.prj | 20 +- mimosis_feb/trb5sc_mimosis.vhd | 312 +++++++++++++------------ pinout/trb5sc_mimosisfeb.lpf | 112 ++++----- vldb/code/gbt_core.vhd | 37 ++- 7 files changed, 873 insertions(+), 212 deletions(-) create mode 100644 mimosis/code/InputStageMulti.vhd create mode 100644 mimosis/code/MimosisInputMulti.vhd diff --git a/mimosis/code/InputStageMulti.vhd b/mimosis/code/InputStageMulti.vhd new file mode 100644 index 0000000..f3a5123 --- /dev/null +++ b/mimosis/code/InputStageMulti.vhd @@ -0,0 +1,246 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity InputStageMulti is + generic( + INPUT_NUMBER : integer := 8 + ); + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + DIN : in std_logic_vector_array_8(0 to 7); + DOUT : out std_logic_vector(15 downto 0); + + ACTIVE : out std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of InputStageMulti is + + signal clk_rx : std_logic; + signal reset_i : std_logic; + signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0'); + + signal data_i : std_logic_vector(15 downto 0); + signal add_reg : std_logic_vector(31 downto 0); + + type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT); + type state_arrt is array (0 to 7) of state_t; + + type unsigned_arr is array(0 to 7) of unsigned(6 downto 0); + signal sample_good, sample_bad : unsigned_arr := (others => (others => '0')); + signal first_good, first_bad : unsigned_arr := (others => (others => '1')); + signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0')); + signal active_i : std_logic_vector(7 downto 0); + signal data_i_mult : std_logic_vector_array_16(0 to 7); + signal s_cflag_mult : std_logic_vector_array_8(0 to 7); + signal input_select : integer range 0 to 31; + +begin + +reset_i <= RESET when rising_edge(CLK); + +gen_inputs : for i in 0 to INPUT_NUMBER-1 generate + THE_IN : entity work.mimosis_inp + port map ( + clkin=>CLK, + reset=>reset_i, + sclk=>open, + data_cflag(7 downto 0)=>s_cflag_mult(i), + data_direction(7 downto 0)=>(others => '0'), + data_loadn(7 downto 0)=>s_loadn, + data_move(7 downto 0)=>s_move, + datain(7 downto 0)=>DIN(i), + q(15 downto 0)=>data_i_mult(i) + ); +end generate; + +data_i <= data_i_mult(input_select) when rising_edge(CLK); +s_cflag <= s_cflag_mult(input_select) when rising_edge(CLK); + +DOUT <= data_i; +ACTIVE <= and(active_i); + +gen_finders : for i in 0 to 7 generate + signal timer : unsigned(14 downto 0); + signal state : state_t; + signal count : unsigned(11 downto 0); + signal pos : unsigned(6 downto 0); + signal lastsample : std_logic; + signal train : unsigned(3 downto 0); + signal last : std_logic_vector(1 downto 0); + +begin + PROC_FIND : process begin + wait until rising_edge(CLK); + s_loadn(i) <= not add_reg(i+16); + active_i(i) <= '0'; + + case state is + when START => + timer <= 0; + count <= 0; + s_move(i) <= '0'; + state <= LISTEN; + + when LISTEN => + if timer(timer'left) = '1' then + state <= STEP; + if count >= 2047 and count <= 2049 then + sample_good(i) <= sample_good(i) + 1; + lastsample <= '1'; + if first_good(i) > pos then + first_good(i) <= pos; + end if; + if last_bad(i) < pos and lastsample = '0' then + last_bad(i) <= pos; + end if; + + else + lastsample <= '0'; + sample_bad(i) <= sample_bad(i) + 1; + if first_bad(i) > pos then + first_bad(i) <= pos; + end if; + if last_good(i) < pos and lastsample = '1' then + last_good(i) <= pos; + end if; + end if; + else + timer <= timer + 1; + end if; + + last <= data_i(i*2+1 downto i*2); + + if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and + data_i(i*2+1 downto i*2) = last then + train <= train + 1; + else + train <= x"0"; + end if; + + if train = x"3" then + count <= count + 1; + end if; + + + when STEP => + if s_cflag(i) = '0' then + s_move(i) <= '1'; + pos <= pos + 1; + state <= START; + else + state <= CALC; + s_loadn(i) <= '0'; + end if; + + when CALC => + if first_good(i) = "0000000" then + pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; + else + pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1); + end if; + state <= SET0; + + when SET0 => + posi(i) <= pos; + state <= SET1; + + when SET1 => + state <= SET2; + s_move(i) <= '1'; + + when SET2 => + s_move(i) <= '0'; + if pos = 0 then + state <= ENDWAIT; + else + state <= SET3; + pos <= pos - 1; + end if; + + when SET3 => + state <= SET1; + + when ENDWAIT => + active_i(i) <= '1'; + state <= ENDWAIT; + + end case; + + if reset_i = '1' or add_reg(0) = '1' then + state <= START; + pos <= 0; + s_loadn(i) <= '0'; + active_i(i) <= '0'; + sample_good(i) <= 0; + sample_bad(i) <= 0; + last_good(i) <= 0; + last_bad(i) <= 0; + first_good(i) <= (others => '1'); + first_bad(i) <= (others => '1'); + end if; + end process; +end generate; + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + addr := to_integer(unsigned(BUS_RX.addr(2 downto 0))); + if BUS_RX.write = '1' then + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.ack <= '1'; + add_reg <= BUS_RX.data; + elsif BUS_RX.addr(15 downto 0) = x"0011" then + BUS_TX.ack <= '1'; + input_select <= to_integer(unsigned(BUS_RX.data(4 downto 0))); + else + BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.data <= add_reg; + elsif BUS_RX.addr(15 downto 0) = x"0011" then + BUS_TX.data(4 downto 0) <= std_logic_vector(to_unsigned(input_select,5)); + elsif BUS_RX.addr(15 downto 4) = x"000" then + if BUS_RX.addr(3) = '0' then + BUS_TX.data(6 downto 0) <= std_logic_vector(sample_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(sample_bad(addr)); + BUS_TX.data(16) <= s_cflag(addr); + BUS_TX.data(20) <= active_i(addr); + BUS_TX.data(30 downto 24)<= std_logic_vector(posi(addr)); + else + BUS_TX.data(6 downto 0) <= std_logic_vector(first_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(last_good(addr)); + BUS_TX.data(22 downto 16) <= std_logic_vector(first_bad(addr)); + BUS_TX.data(30 downto 24) <= std_logic_vector(last_bad(addr)); + end if; + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + + end if; + end if; +end process; + + + + +end architecture; diff --git a/mimosis/code/MimosisInputMulti.vhd b/mimosis/code/MimosisInputMulti.vhd new file mode 100644 index 0000000..ba1a579 --- /dev/null +++ b/mimosis/code/MimosisInputMulti.vhd @@ -0,0 +1,356 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity MimosisInputMulti is + generic( + INPUT_NUMBER : integer := 8 + ); + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector_array_8(0 to 7); + + BUSRDO_RX : in READOUT_RX; + BUSRDO_TX : out READOUT_TX; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of MimosisInputMulti is + constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; + constant WORD_LIMIT : integer := 4000; + signal input_active_i : std_logic; + signal data_i : std_logic_vector(15 downto 0); + signal inp_i : std_logic_vector(7 downto 0); + signal word_i : std_logic_vector(31 downto 0); + signal word_valid : std_logic; + + signal businp_rx, busword_rx, busmimosis_rx : CTRLBUS_RX; + signal businp_tx, busword_tx, busmimosis_tx : CTRLBUS_TX; + + signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic; + signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic; + signal ct_fifo_data_out : std_logic_vector(31 downto 0); + + signal buffer_empty, buffer_full : std_logic; + signal buffer_write, buffer_read : std_logic; + signal buffer_valid, buffer_nextvalid : std_logic; + signal buffer_din, buffer_dout : std_logic_vector(31 downto 0); + signal buffer_fill : std_logic_vector(13 downto 0); + + type state_t is (IDLE,START_COPY, START_COPY2, COPY,FINISH,DONE); + signal state : state_t; + signal word_count : integer range 0 to 8191; + + signal frame_number : std_logic_vector(31 downto 0); + signal frame_length : std_logic_vector(15 downto 0); + signal count_words : unsigned(15 downto 0); + signal count_header : unsigned(31 downto 0); + signal count_trailer : unsigned(31 downto 0); + signal count_fe : unsigned(31 downto 0); + signal count_ff : unsigned(31 downto 0); + signal count_oof : unsigned(31 downto 0); + signal pulse_stats : std_logic_vector(31 downto 0); + signal buffer_blocked : std_logic; + type frame_state_t is (IDLE,HDR1,HDR2,HDR3,WRITING); + signal frame_state : frame_state_t; + + +begin + + THE_IN : entity work.InputStageMulti + port map ( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => INPUT, + DOUT => data_i, + ACTIVE => input_active_i, + + BUS_RX => businp_rx, + BUS_TX => businp_tx + ); + + + THE_WORDS: entity work.WordAlign + port map( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => data_i, + DOUT => word_i, + VALID => word_valid, + + ACTIVE => input_active_i, + + BUS_RX => busword_rx, + BUS_TX => busword_tx + ); + + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg + port map( + Data(31 downto 0) => word_i(31 downto 0), + Data(35 downto 32) => "0000", + WrClock => CLK, + RdClock => CLK_SYS, + WrEn => word_valid, + RdEn => ct_fifo_read, + Reset => RESET, + RPReset => RESET, + Q(31 downto 0) => ct_fifo_data_out(31 downto 0), + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + ct_fifo_read <= '1'; + ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS); + ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS); + +---------------------------------------------------------------------- +-- Frame Copy +---------------------------------------------------------------------- + +PROC_FRAMES : process begin + wait until rising_edge(CLK_SYS); + buffer_write <= '0'; + buffer_din <= ct_fifo_data_out; + + if ct_fifo_valid = '1' then + count_words <= count_words + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + count_fe <= count_fe + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + count_ff <= count_ff + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then + count_oof <= count_oof + 1; + end if; + + case frame_state is + when IDLE => + count_words <= (others => '0'); + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + frame_state <= HDR1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= '1' when buffer_full = '0' and state = IDLE else '0'; + buffer_blocked <= '0' when buffer_full = '0' and state = IDLE else '1'; + count_header <= count_header + 1; + end if; + when HDR1 => + if ct_fifo_valid = '1' then + frame_state <= HDR2; + frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_blocked; + end if; + when HDR2 => + if ct_fifo_valid = '1' then + frame_state <= HDR3; + buffer_din(23 downto 16) <= pulse_stats(7 downto 0); + buffer_din(7 downto 0) <= pulse_stats(15 downto 8); + buffer_write <= not buffer_blocked; + end if; + when HDR3 => + if ct_fifo_valid = '1' then + frame_state <= WRITING; + buffer_din(23 downto 16) <= pulse_stats(23 downto 16); + buffer_din(7 downto 0) <= pulse_stats(31 downto 24); + buffer_write <= not buffer_blocked; + end if; + when WRITING => + buffer_write <= ct_fifo_valid and not buffer_blocked; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + frame_state <= IDLE; + frame_length <= std_logic_vector(count_words); + count_trailer <= count_trailer + 1; + end if; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" and count_words >= x"0004" then + frame_state <= HDR1; + count_header <= count_header + 1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_full; + buffer_blocked <= buffer_full; + end if; + end case; + + end process; + + + +---------------------------------------------------------------------- +-- Main Fifo +---------------------------------------------------------------------- +THE_FIFO : entity work.fifo_36x8k_oreg + port map( + Data(31 downto 0) => buffer_din, + Clock => CLK_SYS, + WrEn => buffer_write, + RdEn => buffer_read, + Reset => RESET, + AmFullThresh => "0010000000000", + Q(31 downto 0) => buffer_dout, + WCNT => buffer_fill, + Empty => buffer_empty, + Full => open, + AlmostFull => buffer_full + ); + + buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS); + buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS); + +--------------------------------------------------------------------------- +-- Buffer Handler +--------------------------------------------------------------------------- +PROC_RDO : process begin + wait until rising_edge(CLK_SYS); +-- if state = IDLE and buffer_full = '1' then +-- buffer_read <= '1'; +-- else + buffer_read <= '0'; +-- end if; + + + BUSRDO_TX.busy_release <= '0'; + BUSRDO_TX.data_write <= '0'; + BUSRDO_TX.data_finished <= '0'; + + case state is + when IDLE => + if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then + state <= START_COPY; + buffer_read <= '1'; + word_count <= 0; + end if; + if BUSRDO_RX.invalid_trg = '1' then + state <= FINISH; + end if; + + when START_COPY => + state <= START_COPY2; + buffer_read <= '1'; + word_count <= word_count + 1; + + when START_COPY2 => + state <= COPY; + buffer_read <= '1'; + word_count <= word_count + 1; + + when COPY => + + if word_count = WORD_LIMIT or buffer_valid = '0' then + state <= FINISH; + else + buffer_read <= '1'; + word_count <= word_count + 1; + BUSRDO_TX.data <= buffer_dout; + BUSRDO_TX.data_write <= '1'; + end if; + + when FINISH => + BUSRDO_TX.data_finished <= '1'; + state <= DONE; + + when DONE => + BUSRDO_TX.busy_release <= '1'; + state <= IDLE; + end case; + +end process; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"), + PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 4, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => CLK_SYS, + RESET => RESET, + + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + + BUS_RX(0) => businp_rx, + BUS_RX(1) => busword_rx, + BUS_RX(2) => busmimosis_rx, + + BUS_TX(0) => businp_tx, + BUS_TX(1) => busword_tx, + BUS_TX(2) => busmimosis_tx, + STAT_DEBUG => open + ); + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '0'; + busmimosis_tx.nack <= '0'; + busmimosis_tx.data <= (others => '0'); + + if busmimosis_rx.write = '1' then + if busmimosis_rx.addr = x"0009" then + pulse_stats <= busmimosis_rx.data; + busmimosis_tx.ack <= '1'; + else + busmimosis_tx.unknown <= '1'; + end if; + elsif busmimosis_rx.read = '1' then + busmimosis_tx.ack <= '1'; + if busmimosis_rx.addr = x"0000" then + busmimosis_tx.data <= std_logic_vector(count_header); + elsif busmimosis_rx.addr = x"0001" then + busmimosis_tx.data <= std_logic_vector(count_trailer); + elsif busmimosis_rx.addr = x"0002" then + busmimosis_tx.data <= x"0000" & frame_length; + elsif busmimosis_rx.addr = x"0003" then + busmimosis_tx.data <= frame_number; + elsif busmimosis_rx.addr = x"0004" then + busmimosis_tx.data <= x"0000" & std_logic_vector(count_words); + elsif busmimosis_rx.addr = x"0005" then + busmimosis_tx.data <= x"0000" & "00" & buffer_fill; + elsif busmimosis_rx.addr = x"0006" then + busmimosis_tx.data <= std_logic_vector(count_fe); + elsif busmimosis_rx.addr = x"0007" then + busmimosis_tx.data <= std_logic_vector(count_ff); + elsif busmimosis_rx.addr = x"0008" then + busmimosis_tx.data <= std_logic_vector(count_oof); + elsif busmimosis_rx.addr = x"0009" then + busmimosis_tx.data <= pulse_stats; + else + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '1'; + + end if; + end if; +end process; + +end architecture; diff --git a/mimosis_feb/par.p2t b/mimosis_feb/par.p2t index acca99b..cf04f8e 100644 --- a/mimosis_feb/par.p2t +++ b/mimosis_feb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 20 +-t 1 -c 2 -e 2 -i 10 diff --git a/mimosis_feb/trb5sc_mimosis.prj b/mimosis_feb/trb5sc_mimosis.prj index 34ed411..9444a25 100644 --- a/mimosis_feb/trb5sc_mimosis.prj +++ b/mimosis_feb/trb5sc_mimosis.prj @@ -288,12 +288,28 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" add_file -vhdl -lib work "../mimosis/cores/mimosis_inp.vhd" add_file -vhdl -lib work "../mimosis/cores/testout.vhd" -add_file -vhdl -lib work "../mimosis/code/MimosisInput.vhd" -add_file -vhdl -lib work "../mimosis/code/InputStage.vhd" +add_file -vhdl -lib work "../mimosis/code/MimosisInputMulti.vhd" +add_file -vhdl -lib work "../mimosis/code/InputStageMulti.vhd" add_file -vhdl -lib work "../mimosis/code/WordAlign.vhd" add_file -vhdl -lib work "../mimosis/cores/pll_200_160/pll_200_160.vhd" +#GBT Core +add_file -vhdl -lib work "../vldb/code/gbt_core.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/gbtsc_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_deserializer.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_pkg.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_rx_fifo.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_rx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/SCA/sca_tx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_deserializer.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_rx_fifo.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_rx.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_top.vhd" +add_file -vhdl -lib work "../vldb/code/GBT-SC/IC/ic_tx.vhd" + + add_file -vhdl -lib work "./trb5sc_mimosis.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/mimosis_feb/trb5sc_mimosis.vhd b/mimosis_feb/trb5sc_mimosis.vhd index 84c7ef7..0305bfd 100644 --- a/mimosis_feb/trb5sc_mimosis.vhd +++ b/mimosis_feb/trb5sc_mimosis.vhd @@ -28,25 +28,25 @@ entity trb5sc_mimosis is SFP_MOD_0 : in std_logic; --HDMI AddOn - LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); - LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); - LED_ADDON_RJ : out std_logic_vector(1 downto 0); - SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); - SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - - RJ : inout std_logic_vector(3 downto 0); - H1 : inout std_logic_vector(4 downto 0); - H2 : inout std_logic_vector(4 downto 0); - H3 : inout std_logic_vector(3 downto 0); - H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(3 downto 0); - H6 : inout std_logic_vector(4 downto 0); - H7 : inout std_logic_vector(4 downto 0); - - PIN : out std_logic_vector(8 downto 1); - - MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + H00 : in std_logic_vector(7 downto 0); + H01 : in std_logic_vector(7 downto 0); + H10 : in std_logic_vector(7 downto 0); + H11 : in std_logic_vector(7 downto 0); + V00 : in std_logic_vector(7 downto 0); + V01 : in std_logic_vector(7 downto 0); + V10 : in std_logic_vector(7 downto 0); + V11 : in std_logic_vector(7 downto 0); + + FE_CLK : out std_logic_vector(3 downto 1); --1: 320, 2: 40, 3: all on second connector + SCA_CLK : out std_logic; + SCA_RX : out std_logic; + SCA_TX : in std_logic; + SCA_RST_B : out std_logic; + SCA2_CLK : out std_logic; + SCA2_RX : out std_logic; + SCA2_TX : in std_logic; + SCA2_RST_B : out std_logic; --ADC ADC_SCLK : out std_logic; @@ -118,8 +118,8 @@ architecture arch of trb5sc_mimosis is - signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, buscts_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, busmimosis_tx, busi2c_tx,busgbtcore_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, buscts_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, busmimosis_rx, busi2c_rx,busgbtcore_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -255,13 +255,9 @@ begin CLKOS3=> clk_80 ); - H3(3) <= clk_320; - - -- For IPHC Proxy - -- RJ(0) <= clk_40; - -- For IKF Proxy - H1(4) <= clk_40; - + FE_CLK(1) <= clk_320; + FE_CLK(2) <= clk_40; + FE_CLK(3) <= '0'; proc_make_reset : process begin wait until rising_edge(clk_sys); @@ -609,9 +605,10 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, others => 0), + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"d000", 1 => x"a000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"de00", 7 => x"d600", + others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 11, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 5, 7 => 4, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -629,6 +626,7 @@ begin BUS_RX(4) => busgbeip_rx, BUS_RX(5) => busgbereg_rx, BUS_RX(6) => busi2c_rx, + BUS_RX(7) => busgbtcore_rx, BUS_TX(0) => bustools_tx, -- BUS_TX(1) => bussci_tx, @@ -638,6 +636,8 @@ begin BUS_TX(4) => busgbeip_tx, BUS_TX(5) => busgbereg_tx, BUS_TX(6) => busi2c_tx, + BUS_TX(7) => busgbtcore_tx, + STAT_DEBUG => open ); @@ -700,8 +700,10 @@ begin DEBUG_OUT => debug_tools ); - PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + -- PIN(5) <= '0' when (add_reg(30) = '0') else 'Z'; + SCA_RST_B <= not add_reg(16); + SCA2_RST_B <= not add_reg(17); FLASH_HOLD <= '1'; FLASH_WP <= '1'; @@ -710,132 +712,142 @@ begin --------------------------------------------------------------------------- -- I2C --------------------------------------------------------------------------- - THE_I2C : entity work.i2c_slim2 - port map( - CLOCK => clk_40, - RESET => reset_i, - -- I2C command / setup - I2C_GO_IN => i2c_go, - ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read - WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word - DIRECT_IN => i2c_reg_1(4), -- don't send command - I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) - I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) - I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command - I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command - STATUS_OUT => i2c_reg_4(23 downto 16), - VALID_OUT => i2c_reg_4(31), - I2C_BUSY_OUT => i2c_reg_4(30), - I2C_DONE_OUT => i2c_reg_4(29), - -- I2C connections - SDA_IN => PIN(4), - SDA_OUT => mimosis_sda_drv, - SCL_IN => PIN(3), - SCL_OUT => mimosis_scl_drv, - -- Debug - BSM_OUT => i2c_reg_4(27 downto 24) - ); - --- I2C signal open collector driver --- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; --- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; - - PIN(4) <= MIMOSIS_SDA; - PIN(3) <= MIMOSIS_SCL; - MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; - MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; - --- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; --- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; - - - H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC - PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START - PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET +-- THE_I2C : entity work.i2c_slim2 +-- port map( +-- CLOCK => clk_40, +-- RESET => reset_i, +-- -- I2C command / setup +-- I2C_GO_IN => i2c_go, +-- ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read +-- WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word +-- DIRECT_IN => i2c_reg_1(4), -- don't send command +-- I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) +-- I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) +-- I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) +-- I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command +-- I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command +-- STATUS_OUT => i2c_reg_4(23 downto 16), +-- VALID_OUT => i2c_reg_4(31), +-- I2C_BUSY_OUT => i2c_reg_4(30), +-- I2C_DONE_OUT => i2c_reg_4(29), +-- -- I2C connections +-- SDA_IN => PIN(4), +-- SDA_OUT => mimosis_sda_drv, +-- SCL_IN => PIN(3), +-- SCL_OUT => mimosis_scl_drv, +-- -- Debug +-- BSM_OUT => i2c_reg_4(27 downto 24) +-- ); +-- +-- -- I2C signal open collector driver +-- -- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- -- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; +-- +-- PIN(4) <= MIMOSIS_SDA; +-- PIN(3) <= MIMOSIS_SCL; +-- MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +-- +-- -- PIN(4) <= '0' when (mimosis_sda_drv = '0' or i2c_reg_1(31) = '1') else 'Z'; +-- -- PIN(3) <= '0' when (mimosis_scl_drv = '0' or i2c_reg_1(30) = '1') else 'Z'; +-- +-- +-- H3(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC +-- PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START +-- PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET PROC_I2C_REGS : process begin wait until rising_edge(CLK_SYS); busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '0'; + busi2c_tx.unknown <= busi2c_rx.write or busi2c_rx.read; busi2c_tx.nack <= '0'; busi2c_tx.data <= (others => '0'); - i2c_go_100 <= '0'; - - if busi2c_rx.write = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - i2c_reg_0 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - i2c_reg_1 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - i2c_reg_2 <= busi2c_rx.data; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - i2c_go_100 <= busi2c_rx.data(0); - elsif busi2c_rx.addr(3 downto 0) = x"5" then - i2c_reg_5 <= busi2c_rx.data; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - end if; - elsif busi2c_rx.read = '1' then - busi2c_tx.ack <= '1'; - if busi2c_rx.addr(3 downto 0) = x"0" then - busi2c_tx.data <= i2c_reg_0; - elsif busi2c_rx.addr(3 downto 0) = x"1" then - busi2c_tx.data <= i2c_reg_1; - elsif busi2c_rx.addr(3 downto 0) = x"2" then - busi2c_tx.data <= i2c_reg_2; - elsif busi2c_rx.addr(3 downto 0) = x"3" then - busi2c_tx.data <= (others => '0'); - elsif busi2c_rx.addr(3 downto 0) = x"4" then - busi2c_tx.data <= i2c_reg_4; - elsif busi2c_rx.addr(3 downto 0) = x"5" then - busi2c_tx.data <= i2c_reg_5; - else - busi2c_tx.ack <= '0'; - busi2c_tx.unknown <= '1'; - - end if; - end if; + -- i2c_go_100 <= '0'; + -- + -- if busi2c_rx.write = '1' then + -- busi2c_tx.ack <= '1'; + -- if busi2c_rx.addr(3 downto 0) = x"0" then + -- i2c_reg_0 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"1" then + -- i2c_reg_1 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"2" then + -- i2c_reg_2 <= busi2c_rx.data; + -- elsif busi2c_rx.addr(3 downto 0) = x"3" then + -- i2c_go_100 <= busi2c_rx.data(0); + -- elsif busi2c_rx.addr(3 downto 0) = x"5" then + -- i2c_reg_5 <= busi2c_rx.data; + -- else + -- busi2c_tx.ack <= '0'; + -- busi2c_tx.unknown <= '1'; + -- end if; + -- elsif busi2c_rx.read = '1' then + -- busi2c_tx.ack <= '1'; + -- if busi2c_rx.addr(3 downto 0) = x"0" then + -- busi2c_tx.data <= i2c_reg_0; + -- elsif busi2c_rx.addr(3 downto 0) = x"1" then + -- busi2c_tx.data <= i2c_reg_1; + -- elsif busi2c_rx.addr(3 downto 0) = x"2" then + -- busi2c_tx.data <= i2c_reg_2; + -- elsif busi2c_rx.addr(3 downto 0) = x"3" then + -- busi2c_tx.data <= (others => '0'); + -- elsif busi2c_rx.addr(3 downto 0) = x"4" then + -- busi2c_tx.data <= i2c_reg_4; + -- elsif busi2c_rx.addr(3 downto 0) = x"5" then + -- busi2c_tx.data <= i2c_reg_5; + -- else + -- busi2c_tx.ack <= '0'; + -- busi2c_tx.unknown <= '1'; + -- + -- end if; + -- end if; end process; - THE_I2C_GO_SYNC : pulse_sync - port map( - CLK_A_IN => clk_sys, - RESET_A_IN => reset_i, - PULSE_A_IN => i2c_go_100, - CLK_B_IN => clk_40, - RESET_B_IN => reset_i, - PULSE_B_OUT => i2c_go - ); - - THE_MIMOSIS_SIGNAL_SYNC : signal_sync - generic map( - WIDTH => 32, - DEPTH => 2 - ) - port map( - RESET => reset_i, - CLK0 => clk_sys, - CLK1 => clk_40, - D_IN => i2c_reg_5, - D_OUT => i2c_reg_5_40 - ); + -- THE_I2C_GO_SYNC : pulse_sync + -- port map( + -- CLK_A_IN => clk_sys, + -- RESET_A_IN => reset_i, + -- PULSE_A_IN => i2c_go_100, + -- CLK_B_IN => clk_40, + -- RESET_B_IN => reset_i, + -- PULSE_B_OUT => i2c_go + -- ); + + -- THE_MIMOSIS_SIGNAL_SYNC : signal_sync + -- generic map( + -- WIDTH => 32, + -- DEPTH => 2 + -- ) + -- port map( + -- RESET => reset_i, + -- CLK0 => clk_sys, + -- CLK1 => clk_40, + -- D_IN => i2c_reg_5, + -- D_OUT => i2c_reg_5_40 + -- ); --------------------------------------------------------------------------- -- Input stage --------------------------------------------------------------------------- - THE_MIMOSIS : entity work.MimosisInput + THE_MIMOSIS : entity work.MimosisInputMulti + generic map( + INPUT_NUMBER => 8 + ) port map( CLK => clk_160, CLK_SYS => clk_sys, RESET => reset_i, - INPUT => inp_i, + INPUT(0) => H00, + INPUT(1) => H01, + INPUT(2) => H10, + INPUT(3) => H11, + INPUT(4) => V00, + INPUT(5) => V01, + INPUT(6) => V10, + INPUT(7) => V11, BUSRDO_RX => cts_rdo_rx, BUSRDO_TX => cts_rdo_additional(0), @@ -844,9 +856,27 @@ begin BUS_TX => busmimosis_tx ); --- inp_i <= H2(3 downto 0) & H1(3 downto 0); - inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); - +--------------------------------------------------------------------------- +-- GBT Core +--------------------------------------------------------------------------- + THE_GBT_CORE : entity work.gbt_core + port map( + CLK_SYS => clk_sys, + CLK => clk_40, + CLK_80 => clk_80, + RESET => reset_i, + + BUS_RX => busgbtcore_rx, + BUS_TX => busgbtcore_tx, + + TESTOUT => LED, + + -- ELINK_RX => H3(2), + ELINK_RX => SCA_TX, + ELINK_TX => SCA_RX + ); + + SCA_CLK <= clk_40; --------------------------------------------------------------------------- -- LED @@ -858,7 +888,7 @@ begin -- LED_SFP_GREEN <= not med2int(0).stat_op(9); -- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); -- LED_SFP_YELLOW <= not med2int(0).stat_op(8); - LED <= x"FF"; + -- LED <= x"FF"; LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used LED_RJ_GREEN(0)<= '1' when led_off = '1' else '0'; --on if SFP is used (next to SFP) LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used diff --git a/pinout/trb5sc_mimosisfeb.lpf b/pinout/trb5sc_mimosisfeb.lpf index f6912b2..162cb81 100644 --- a/pinout/trb5sc_mimosisfeb.lpf +++ b/pinout/trb5sc_mimosisfeb.lpf @@ -136,70 +136,70 @@ IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 ; # LOCATE COMP "FE_DIFF_61_N" SITE "AC6"; # LOCATE COMP "FE_DIFF_62_N" SITE "AB6"; # LOCATE COMP "FE_DIFF_63_N" SITE "AD7"; -LOCATE COMP "H01_D7" SITE "R29" ; #"FE_DIFF[0]" -LOCATE COMP "H01_D3" SITE "T29" ; #"FE_DIFF[1]" -LOCATE COMP "H00_D1" SITE "P31" ; #"FE_DIFF[2]" -LOCATE COMP "H11_D1" SITE "R30" ; #"FE_DIFF[3]" -LOCATE COMP "H00_D3" SITE "N32" ; #"FE_DIFF[4]" -LOCATE COMP "H00_D5" SITE "U31" ; #"FE_DIFF[5]" -LOCATE COMP "H11_D3" SITE "R32" ; #"FE_DIFF[6]" -LOCATE COMP "H01_D1" SITE "W30" ; #"FE_DIFF[7]" -LOCATE COMP "H01_D5" SITE "T32" ; #"FE_DIFF[8]" -LOCATE COMP "H01_D6" SITE "V32" ; #"FE_DIFF[9]" -LOCATE COMP "H00_D7" SITE "Y26" ; #"FE_DIFF[10]" -LOCATE COMP "H01_D2" SITE "Y28" ; #"FE_DIFF[11]" -LOCATE COMP "H00_D0" SITE "Y29" ; #"FE_DIFF[12]" -LOCATE COMP "H11_D0" SITE "AB26" ; #"FE_DIFF[13]" -LOCATE COMP "H10_D7" SITE "AB28" ; #"FE_DIFF[14]" -LOCATE COMP "H00_D2" SITE "AC26" ; #"FE_DIFF[15]" -LOCATE COMP "H10_D5" SITE "D29" ; #"FE_DIFF[16]" -LOCATE COMP "H00_D4" SITE "F29" ; #"FE_DIFF[17]" -LOCATE COMP "H11_D2" SITE "B32" ; #"FE_DIFF[18]" -LOCATE COMP "H01_D0" SITE "D30" ; #"FE_DIFF[19]" -LOCATE COMP "H10_D1" SITE "F30" ; #"FE_DIFF[20]" -LOCATE COMP "H01_D4" SITE "C32" ; #"FE_DIFF[21]" -LOCATE COMP "H10_D3" SITE "F31" ; #"FE_DIFF[22]" -LOCATE COMP "H00_D6" SITE "F32" ; #"FE_DIFF[23]" -LOCATE COMP "H10_D6" SITE "H31" ; #"FE_DIFF[24]" -LOCATE COMP "H11_D7" SITE "J30" ; #"FE_DIFF[25]" -LOCATE COMP "H10_D4" SITE "K31" ; #"FE_DIFF[26]" -LOCATE COMP "H11_D5" SITE "K32" ; #"FE_DIFF[27]" -LOCATE COMP "H11_D6" SITE "L31" ; #"FE_DIFF[28]" -LOCATE COMP "H10_D0" SITE "J29" ; #"FE_DIFF[29]" -LOCATE COMP "H11_D4" SITE "H27" ; #"FE_DIFF[30]" -LOCATE COMP "H10_D2" SITE "K27" ; #"FE_DIFF[31]" +LOCATE COMP "H01_7" SITE "R29" ; #"FE_DIFF[0]" +LOCATE COMP "H01_3" SITE "T29" ; #"FE_DIFF[1]" +LOCATE COMP "H00_1" SITE "P31" ; #"FE_DIFF[2]" +LOCATE COMP "H11_1" SITE "R30" ; #"FE_DIFF[3]" +LOCATE COMP "H00_3" SITE "N32" ; #"FE_DIFF[4]" +LOCATE COMP "H00_5" SITE "U31" ; #"FE_DIFF[5]" +LOCATE COMP "H11_3" SITE "R32" ; #"FE_DIFF[6]" +LOCATE COMP "H01_1" SITE "W30" ; #"FE_DIFF[7]" +LOCATE COMP "H01_5" SITE "T32" ; #"FE_DIFF[8]" +LOCATE COMP "H01_6" SITE "V32" ; #"FE_DIFF[9]" +LOCATE COMP "H00_7" SITE "Y26" ; #"FE_DIFF[10]" +LOCATE COMP "H01_2" SITE "Y28" ; #"FE_DIFF[11]" +LOCATE COMP "H00_0" SITE "Y29" ; #"FE_DIFF[12]" +LOCATE COMP "H11_0" SITE "AB26" ; #"FE_DIFF[13]" +LOCATE COMP "H10_7" SITE "AB28" ; #"FE_DIFF[14]" +LOCATE COMP "H00_2" SITE "AC26" ; #"FE_DIFF[15]" +LOCATE COMP "H10_5" SITE "D29" ; #"FE_DIFF[16]" +LOCATE COMP "H00_4" SITE "F29" ; #"FE_DIFF[17]" +LOCATE COMP "H11_2" SITE "B32" ; #"FE_DIFF[18]" +LOCATE COMP "H01_0" SITE "D30" ; #"FE_DIFF[19]" +LOCATE COMP "H10_1" SITE "F30" ; #"FE_DIFF[20]" +LOCATE COMP "H01_4" SITE "C32" ; #"FE_DIFF[21]" +LOCATE COMP "H10_3" SITE "F31" ; #"FE_DIFF[22]" +LOCATE COMP "H00_6" SITE "F32" ; #"FE_DIFF[23]" +LOCATE COMP "H10_6" SITE "H31" ; #"FE_DIFF[24]" +LOCATE COMP "H11_7" SITE "J30" ; #"FE_DIFF[25]" +LOCATE COMP "H10_4" SITE "K31" ; #"FE_DIFF[26]" +LOCATE COMP "H11_5" SITE "K32" ; #"FE_DIFF[27]" +LOCATE COMP "H11_6" SITE "L31" ; #"FE_DIFF[28]" +LOCATE COMP "H10_0" SITE "J29" ; #"FE_DIFF[29]" +LOCATE COMP "H11_4" SITE "H27" ; #"FE_DIFF[30]" +LOCATE COMP "H10_2" SITE "K27" ; #"FE_DIFF[31]" LOCATE COMP "FE_CLK[3]" SITE "D4" ; #"FE_DIFF[32]" -LOCATE COMP "V10_D7" SITE "F4" ; #"FE_DIFF[33]" +LOCATE COMP "V10_7" SITE "F4" ; #"FE_DIFF[33]" LOCATE COMP "SCA2_RX" SITE "B1" ; #"FE_DIFF[34]" LOCATE COMP "SCA2_TX" SITE "D3" ; #"FE_DIFF[35]" LOCATE COMP "SCA2_CLK" SITE "F3" ; #"FE_DIFF[36]" -LOCATE COMP "V10_D5" SITE "C1" ; #"FE_DIFF[37]" +LOCATE COMP "V10_5" SITE "C1" ; #"FE_DIFF[37]" #LOCATE COMP "V_D" SITE "F2" ; #"FE_DIFF[38]" -LOCATE COMP "V10_D1" SITE "F1" ; #"FE_DIFF[39]" -LOCATE COMP "V01_D6" SITE "H2" ; #"FE_DIFF[40]" -LOCATE COMP "V00_D3" SITE "J3" ; #"FE_DIFF[41]" -LOCATE COMP "V10_D3" SITE "K2" ; #"FE_DIFF[42]" -LOCATE COMP "V10_D4" SITE "K1" ; #"FE_DIFF[43]" +LOCATE COMP "V10_1" SITE "F1" ; #"FE_DIFF[39]" +LOCATE COMP "V01_6" SITE "H2" ; #"FE_DIFF[40]" +LOCATE COMP "V00_3" SITE "J3" ; #"FE_DIFF[41]" +LOCATE COMP "V10_3" SITE "K2" ; #"FE_DIFF[42]" +LOCATE COMP "V10_4" SITE "K1" ; #"FE_DIFF[43]" LOCATE COMP "SCA_RX" SITE "L2" ; #"FE_DIFF[44]" -LOCATE COMP "V10_D6" SITE "J4" ; #"FE_DIFF[45]" +LOCATE COMP "V10_6" SITE "J4" ; #"FE_DIFF[45]" LOCATE COMP "SCA_CLK" SITE "H6" ; #"FE_DIFF[46]" -LOCATE COMP "V00_D7" SITE "K6" ; #"FE_DIFF[47]" -LOCATE COMP "V01_D2" SITE "R4" ; #"FE_DIFF[48]" +LOCATE COMP "V00_7" SITE "K6" ; #"FE_DIFF[47]" +LOCATE COMP "V01_2" SITE "R4" ; #"FE_DIFF[48]" LOCATE COMP "SCA_TX" SITE "T4" ; #"FE_DIFF[49]" -LOCATE COMP "V00_D5" SITE "P2" ; #"FE_DIFF[50]" -LOCATE COMP "V00_D1" SITE "R3" ; #"FE_DIFF[51]" -LOCATE COMP "V11_D6" SITE "N1" ; #"FE_DIFF[52]" -LOCATE COMP "V01_D4" SITE "U2" ; #"FE_DIFF[53]" -LOCATE COMP "V11_D2" SITE "R1" ; #"FE_DIFF[54]" -LOCATE COMP "V10_D0" SITE "W3" ; #"FE_DIFF[55]" -LOCATE COMP "V00_D2" SITE "T1" ; #"FE_DIFF[56]" -LOCATE COMP "V00_D0" SITE "V1" ; #"FE_DIFF[57]" -LOCATE COMP "V01_D0" SITE "Y7" ; #"FE_DIFF[58]" -LOCATE COMP "V10_D2" SITE "Y5" ; #"FE_DIFF[59]" -LOCATE COMP "V00_D6" SITE "Y4" ; #"FE_DIFF[60]" -LOCATE COMP "V00_D4" SITE "AB7" ; #"FE_DIFF[61]" -LOCATE COMP "V11_D4" SITE "AB5" ; #"FE_DIFF[62]" -LOCATE COMP "V11_D0" SITE "AC7" ; #"FE_DIFF[63]" +LOCATE COMP "V00_5" SITE "P2" ; #"FE_DIFF[50]" +LOCATE COMP "V00_1" SITE "R3" ; #"FE_DIFF[51]" +LOCATE COMP "V11_6" SITE "N1" ; #"FE_DIFF[52]" +LOCATE COMP "V01_4" SITE "U2" ; #"FE_DIFF[53]" +LOCATE COMP "V11_2" SITE "R1" ; #"FE_DIFF[54]" +LOCATE COMP "V10_0" SITE "W3" ; #"FE_DIFF[55]" +LOCATE COMP "V00_2" SITE "T1" ; #"FE_DIFF[56]" +LOCATE COMP "V00_0" SITE "V1" ; #"FE_DIFF[57]" +LOCATE COMP "V01_0" SITE "Y7" ; #"FE_DIFF[58]" +LOCATE COMP "V10_2" SITE "Y5" ; #"FE_DIFF[59]" +LOCATE COMP "V00_6" SITE "Y4" ; #"FE_DIFF[60]" +LOCATE COMP "V00_4" SITE "AB7" ; #"FE_DIFF[61]" +LOCATE COMP "V11_4" SITE "AB5" ; #"FE_DIFF[62]" +LOCATE COMP "V11_0" SITE "AC7" ; #"FE_DIFF[63]" DEFINE PORT GROUP "H0_group" "H0*" ; DEFINE PORT GROUP "H1_group" "H1*" ; diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 46cffb4..ee52b43 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -2,10 +2,14 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library ecp5um; +use ecp5um.components.all; + library work; use work.trb_net_std.all; + entity gbt_core is port( CLK_SYS : in std_logic; @@ -185,18 +189,27 @@ begin end if; end process; + inst_oddrx1f: ODDRX1F + port map ( + D0 => hdlc_from_gbtsc(1), + D1 => hdlc_from_gbtsc(0), + SCLK => CLK, + RST => RESET, + Q => ELINK_TX + ); + - -- HDLC serializer + -- -- HDLC serializer hdlcser_proc: process(CLK_80) - variable bitflip : std_logic := '0'; + -- variable bitflip : std_logic := '0'; begin if rising_edge(CLK_80) then - if bitflip = '1' then - ELINK_TX <= hdlc_from_gbtsc(1); - else - ELINK_TX <= hdlc_from_gbtsc(0); - end if; - bitflip := not bitflip; + -- if bitflip = '1' then + -- ELINK_TX <= hdlc_from_gbtsc(1); + -- else + -- ELINK_TX <= hdlc_from_gbtsc(0); + -- end if; + -- bitflip := not bitflip; hdlc_des <= hdlc_des(2 downto 0) & ELINK_RX; end if; end process; @@ -228,16 +241,16 @@ begin if BUS_RX.addr(3 downto 0) = x"0" then gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); - elsif BUS_RX.addr(3 downto 0) = x"1" then - gbtsc_reset_go <= BUS_RX.data(0); - gbtsc_connect_go <= BUS_RX.data(1); - gbtsc_go <= BUS_RX.data(2); elsif BUS_RX.addr(3 downto 0) = x"2" then gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); elsif BUS_RX.addr(3 downto 0) = x"3" then gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); + elsif BUS_RX.addr(3 downto 0) = x"4" then + gbtsc_reset_go <= BUS_RX.data(0); + gbtsc_connect_go <= BUS_RX.data(1); + gbtsc_go <= BUS_RX.data(2); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; -- 2.51.0