]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/shortlog
trb3.git
2014-09-28 Manuel PenschuckCBM: Wrong status bits for event packer; CTS: clean up
2014-09-24 Manuel PenschuckCBM: Timing issues in sync module due to meta-stab...
2014-09-22 Manuel PenschuckCTS: Included sync module, introduced new constraints...
2014-09-22 Manuel PenschuckCBMNet: First version of sync-module (not fully tested...
2014-09-19 Jan Michelchanged SED checker to use new record based control...
2014-09-15 Jan Michelchanged reset behavior of external clock selection...
2014-09-05 Jan Michellatest adc handler. acknowledges triggers, no readout
2014-08-21 Ludwig MaierRevert "cleanup adc handler"
2014-08-21 Ludwig MaierRevert "tmp"
2014-08-21 Ludwig MaierRevert "nxyter, new working adc handler"
2014-08-21 Ludwig MaierRevert "nxyter, new working adc handler 2"
2014-08-21 Ludwig MaierRevert "nxyter: calibration trigger bug removed"
2014-08-21 Ludwig MaierRevert "nxyter: keep status, working so far"
2014-08-21 Ludwig MaierRevert "geht garnicht"
2014-08-21 Ludwig Maiergeht garnicht
2014-08-21 Ludwig Maiernxyter: keep status, working so far
2014-08-21 Ludwig Maiernxyter: calibration trigger bug removed
2014-08-18 Jan Michellatest status of ADC read-out
2014-08-18 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-08-18 Cahitcbmtof clock manager design
2014-08-14 Ludwig Maiernxyter, new working adc handler 2
2014-08-14 Ludwig Maiernxyter, new working adc handler
2014-08-14 Ludwig Maiertmp
2014-08-14 Ludwig Maiercleanup adc handler
2014-08-14 Ludwig Maiertry new clock domains in nx_data_receiver
2014-08-10 Manuel PenschuckReadout seems to work with TrbNet test-pattern generator
2014-08-07 Manuel PenschuckCBMNet: data_stop-related timing problem in combination...
2014-08-05 Manuel PenschuckCBMNet readout: Debug-Design for Periph-FPGA with Test...
2014-08-04 Jan Micheladded entities for proper ADC readout, reorganized...
2014-07-31 Cahittdc v1.6.3 compatibility with the tdc v1.7.1
2014-07-29 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-29 Cahit32PinAddOn design is brought up-to-date with tdc v1.7.1
2014-07-29 Cahittdc v1.7 and v1.7.1 release
2014-07-29 Jan Michelcreated two CTS constraints files for compatibilty...
2014-07-28 Manuel PenschuckMigrated CTS constraints to Diamond 3.2 (Synplify I...
2014-07-28 Manuel PenschuckMonitoring and Debug features added to CBM-Readout...
2014-07-25 Jan Michelfew more debugging regs for ADC
2014-07-24 Jan Michelsome additional registers for ADC control
2014-07-23 Jan Michelfirst running ADC AddOn version
2014-07-22 Jan Michelnext step towards running ADC board
2014-07-18 Manuel PenschuckCBMNet: Simulation of TrbNet -> CBMNet readout path...
2014-07-18 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-18 Cahittidy up
2014-07-17 Ludwig Maiernxyter ts/adc timestamp delay auto adjust entity implem...
2014-07-17 Manuel PenschuckCBMNet readout backup
2014-07-17 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-17 CahitTDC version v1.6.3 brought uptodate with the new config...
2014-07-17 CahitGeneral Purpose project brought uptodate with tdc core...
2014-07-16 Ludwig Maiernxyter ts/adc timestamp delay auto adjust entity implem...
2014-07-16 Ludwig Maiernxyter: bug fix in slow control
2014-07-16 Andreas NeiserADC: Keeping the ADC SPI pins low (also PULLMODE=DOWN...
2014-07-07 Jan Micheladded flexible UART to all 4conn AddOns via FPGA5_3V3...
2014-07-07 Andreas NeiserADC: Adding many missing things to LPF files...how...
2014-07-07 Andreas NeiserADC: More nxyter like CLK usage...not tested yet
2014-07-07 Andreas NeiserADC: Switching to other CLK also does not help...
2014-07-07 Andreas NeiserADC Addon: Fix CS numbering
2014-07-02 Jan Michelupdate to CTS project file for TDCs
2014-07-02 Jan Michelremoved fast signals from debug word
2014-07-02 Jan Micheladded UART to trb3_gbe design
2014-06-30 Manuel PenschuckAdded CBMNet support to CTS - not working yet
2014-06-30 Manuel Penschuckadded module configuration to CTS prj-file: All include...
2014-06-30 Manuel Penschuckinitial version of the (yet incomplete) read-out handle...
2014-06-30 Manuel Penschuckcbmnet phy: additional debug tools .. data transport...
2014-06-30 Manuel Penschuckmoved CBMNet SFP to base
2014-06-25 Manuel PenschuckCBMNet: Relaxed Timing Constraints - Seems to work
2014-06-25 Manuel PenschuckCBMNet: Relaxed some time critical components. Design...
2014-06-24 Ludwig Maiernxyter: additional debug line out for new addon board
2014-06-24 Ludwig Maiernxyter update
2014-06-24 Ludwig Maiernxyter update
2014-06-24 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-06-24 Cahittdc release 1.6.3
2014-06-23 Jan Michelchanged enable handling in trigger logic
2014-06-23 Jan Michelchanged enable handling in trigger logic
2014-06-21 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-06-18 Manuel PenschuckData transport works in the straight-forward case
2014-06-13 Jan Michelupdated coincidence logic
2014-06-13 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-06-13 CahitStandard AddOn Project is brought up to date with tdc_v...
2014-06-13 Manuel PenschuckSynthesisable with new CBMNet, however initialisation...
2014-06-12 Jan Michelvery simple coincidence logic for trigger logic
2014-06-04 Manuel PenschuckChanges before adopting to new CBMNet version
2014-06-04 Manuel Penschuckcreate_project: more helpful error messages & bug-fix
2014-06-04 Manuel PenschuckChanges before adopting to new CBMNet version
2014-05-27 Jan Micheladded included features map to trb3_gbe design
2014-05-27 Jan Michelsmall change in definition of included features tables
2014-05-26 Ludwig Maiernxyter update
2014-05-25 Ludwig Maiernxyter trb3_periph.prj update
2014-05-25 Ludwig Maiernxyter timestamp histogram added
2014-05-23 Andreas NeiserADC Addon: Better CS mapping, probably...
2014-05-23 Manuel PenschuckCTS typo
2014-05-23 Manuel PenschuckCBMNet before refactoring to slave-only version
2014-05-23 Manuel PenschuckTypo
2014-05-23 Andreas NeiserADC Addon: Fix SPI connections to FPGA (single ended!)
2014-05-23 Andreas NeiserFixing group name clash in LPF for ADC addon
2014-05-23 Andreas NeiserMultiplex the SPI communication for the ADC addon
2014-05-23 Andreas NeiserSomewhat better grepping for errors in compile script
2014-05-23 Andreas NeiserAdding GSI compile script for ADC addon
2014-05-22 Andreas NeiserAdding bus_register_handler.vhd to the project files
2014-05-22 Manuel PenschuckDiamond project creation tool. See daqdocu
2014-05-22 Andreas NeiserCommenting duplicate declaration of FIFO_DC_36x32_OutRe...
next