| 2015-06-13 |
Andreas Neiser | CFD signal implemented, not tested yet |
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| 2015-06-13 |
Andreas Neiser | Changes to properly init for simulation... |
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| 2015-06-13 |
Andreas Neiser | Implement debug slowcontrol stuff |
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| 2015-06-13 |
Andreas Neiser | Rename config record names |
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| 2015-06-13 |
Andreas Neiser | Correct baseline subtracted signal generated |
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| 2015-06-13 |
Andreas Neiser | Finally defined baseline, but averaging not working yet |
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| 2015-06-13 |
Andreas Neiser | Default value in ADC makes baseline calculation work |
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| 2015-06-13 |
Andreas Neiser | Baseline init problem to be solved, but simulation... |
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| 2015-06-13 |
Andreas Neiser | Correct shift register |
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| 2015-06-13 |
Andreas Neiser | Make the testbench test the CFD processor |
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| 2015-06-13 |
Andreas Neiser | Baseline averaging works maybe... |
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| 2015-06-13 |
Andreas Neiser | Starting standalone CFD processor |
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| 2015-06-13 |
Andreas Neiser | Minor config update |
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| 2015-06-13 |
Andreas Neiser | Fix for Modelsim |
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| 2015-06-13 |
Andreas Neiser | Run ADC FIFO in continuous mode if CFD readout |
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| 2015-06-13 |
Andreas Neiser | Introduce READOUT_MODE config option |
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| 2015-06-13 |
Andreas Neiser | Make extra modelsim project for CFD |
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| 2015-06-13 |
Andreas Neiser | Snapshot modelsim project file |
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| 2015-06-13 |
Andreas Neiser | Data output fix |
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| 2015-06-13 |
Andreas Neiser | Restart FIFO properly, otherwise sim does not work |
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| 2015-06-13 |
Andreas Neiser | use restart |
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| 2015-06-13 |
Andreas Neiser | another fix |
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| 2015-06-13 |
Andreas Neiser | more sophisticated inter process signaling... |
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| 2015-06-13 |
Andreas Neiser | Maybe working dummy dqsinput |
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| 2015-06-13 |
Andreas Neiser | Introduce dqsinput, sufficient to simulate deserialize... |
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| 2015-06-13 |
Andreas Neiser | Fix |
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| 2015-06-13 |
Andreas Neiser | Counter on data |
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| 2015-06-13 |
Andreas Neiser | Feed all ADCs... |
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| 2015-06-13 |
Andreas Neiser | Sim works somehow, now feed in reasonable data |
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| 2015-06-13 |
Andreas Neiser | Maybe works |
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| 2015-06-13 |
Andreas Neiser | Sim not working yet |
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| 2015-06-13 |
Andreas Neiser | Testbenching the AD9219 entity |
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| 2015-06-13 |
Andreas Neiser | Register i'th fifo_empty signal |
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| 2015-06-13 |
Andreas Neiser | Try with 80MHz |
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| 2015-06-13 |
Andreas Neiser | Revert "Made each ADC chip separate entity" |
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| 2015-06-13 |
Andreas Neiser | Revert "Add ADC chip entity to project" |
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| 2015-06-13 |
Andreas Neiser | Remove HGROUP stuff again, maybe this is finally the... |
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| 2015-06-13 |
Andreas Neiser | Try with 64MHz |
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| 2015-06-13 |
Andreas Neiser | Add HGROUP to FIFO, to identify it easier in floorplan |
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| 2015-06-13 |
Andreas Neiser | Add ADC chip entity to project |
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| 2015-06-13 |
Andreas Neiser | Made each ADC chip separate entity |
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| 2015-06-13 |
Andreas Neiser | Synplify: Set clock timing for ADC to 163MHz, enable... |
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| 2015-06-13 |
Andreas Neiser | Make map try harder (copied from CTS compile script) |
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| 2015-06-13 |
Andreas Neiser | Make mpartcre try with all seeds |
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| 2015-06-13 |
Andreas Neiser | Minor simulation changes |
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| 2015-06-13 |
Andreas Neiser | Adding pipeline to debug output |
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| 2015-06-13 |
Andreas Neiser | Changing the PLL to 325MHz to cope with 65MS (hopefully) |
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| 2015-06-13 |
Andreas Neiser | ADC: Add 65MHz PLL to project |
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| 2015-06-13 |
Andreas Neiser | ADC: Use 65MHz sampling rate |
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| 2015-06-13 |
Andreas Neiser | Adding 200->65 MHz PLL |
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| 2015-06-13 |
Andreas Neiser | ADC: Keep readout data lines low when not actually... |
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| 2015-06-13 |
Andreas Neiser | Use mpartcre to find designs without timing errors |
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| 2015-06-13 |
Andreas Neiser | Little fix in testbench |
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| 2015-06-13 |
Andreas Neiser | Take polarity into account for CFD subtraction |
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| 2015-06-13 |
Andreas Neiser | Minor testbench changes, saved waveform macro |
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| 2015-06-13 |
Andreas Neiser | Invert polarity ADC signals |
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| 2015-06-13 |
Andreas Neiser | Little improvements for simulation |
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| 2015-06-13 |
Andreas Neiser | Default values for PSA signals |
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| 2015-06-13 |
Andreas Neiser | Reformat source... |
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| 2015-06-13 |
Andreas Neiser | Only check trigger threshold when possible zero crossing |
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| 2015-06-13 |
Andreas Neiser | Use readout threshold to suppress CFD readout on integr... |
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| 2015-06-13 |
Andreas Neiser | Use registers economically |
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| 2015-06-13 |
Andreas Neiser | Fix ram_read_cfd handling |
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| 2015-06-13 |
Andreas Neiser | Minor edits to get simulation running |
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| 2015-06-13 |
Andreas Neiser | Config and testbench updates |
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| 2015-06-13 |
Andreas Neiser | Finished CFD reading state machine |
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| 2015-06-13 |
Andreas Neiser | First modifications for additional CFD readout, CFD... |
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| 2015-06-05 |
Jan Michel | removed old test file |
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| 2015-06-05 |
Jan Michel | new entities and serdes configurations |
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| 2015-06-05 |
Jan Michel | updated periph_hub for new Diamond 3.4 |
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| 2015-05-22 |
Cahit | bugfix in compile script for wasa |
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| 2015-05-22 |
Cahit | updated compile script for wasa |
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| 2015-05-18 |
Cahit | brought the project up-to-date with tdc_v2.1.3 |
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| 2015-05-08 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-05-08 |
Cahit | brought 32 PinAddOn project up-to-date |
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| 2015-05-08 |
Cahit | brought 4-conn-addon (padiwa) project up-to-date |
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| 2015-05-05 |
Jan Michel | new files for fpgatest design |
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| 2015-05-04 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-05-04 |
Cahit | minor changes in the ADA project file |
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| 2015-04-28 |
Jan Michel | added trigger information register to CTS |
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| 2015-04-28 |
Jan Michel | added a sync media interface to cbmtof. Disable it... |
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| 2015-04-27 |
Cahit | ADA AddOn project is brought up-to-date with tdc 2... |
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| 2015-04-17 |
Cahit | updated project file for SFP power read and new tdc... |
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| 2015-04-16 |
Cahit | SFP Digital Diagnostic Monitoring module implemented |
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| 2015-04-08 |
Cahit | 20MHz to 100MHz pll |
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| 2015-04-08 |
Cahit | various changes in version 2.1.2 |
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| 2015-04-08 |
Cahit | tdc_test is moved to the tdc repo |
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| 2015-03-13 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-03-13 |
Cahit | release table written in org mode. Also a script exists... |
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| 2015-03-13 |
Jan Michel | fixed to use internal trigger source for CTS |
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| 2015-03-05 |
Jan Michel | updated CTS to Diamond 3.4, made new simple default... |
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| 2015-03-03 |
Jan Michel | moved CTS with Cbmnet to own config file |
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| 2015-03-03 |
Jan Michel | adjust uart output driver |
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| 2015-02-24 |
Tobias Weber | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-02-24 |
Tobias Weber | additional buffers for synchronizing hitbus and szintil... |
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| 2015-02-24 |
Tobias Weber | high active reset used in all entities and synchronous... |
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| 2015-02-23 |
Tobias Weber | Merge branch 'master' into MuPix |
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| 2015-02-23 |
Tobias Weber | Solved some timing error. But there is one timing error... |
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| 2015-02-23 |
Tobias Weber | some typo errors. Design generates bitstream but has... |
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| 2015-02-23 |
Tobias Weber | adjustable max size for a mupix data frame |
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jspc29 / trb3.git / shortlog