]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/shortlog
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2016-08-25 Jan Michelupdates to sync media interface for dirich modules
2016-08-22 Your Nameupdate
2016-08-10 Your Namekiller ping added
2016-07-11 Jan MichelDisconnect some debug signals for better timing
2016-07-08 Your Namegbe update
2016-07-06 Jan MichelUpdate to ecp5 media interface
2016-05-27 Jan MichelUpdate to UART, fix for wrong bit start signals
2016-03-22 Jan MichelAdding some logic to bus_handler_record to cope with...
2016-03-21 Jan Micheladding testbench for input_to_trigger_logic
2016-03-18 Jan MichelAdditional temperature output for hub
2016-03-18 Jan Michelupdating sync media interfaces: no more high-speed...
2016-03-14 Cahitsyntax correction
2016-01-11 Jan Michelchanging ecp5 fifo name to ecp3 for compatibility
2016-01-07 Jan Michelpreparation of ecp5 media interface and machxo3 fifo
2016-01-04 Jan MichelAdding missing Fifos for ECP5
2015-12-16 Jan MichelClean-up of endpoint ports and adding a new register...
2015-12-15 Jan MichelAdding new port to endpoint for external slow control...
2015-12-09 Jan MichelAdding a testbench for onewire entity
2015-11-27 Jan MichelMoving MAC generation to top level gbe_wrapper
2015-11-25 Jan MichelFixing register read issue in GbE
2015-11-20 Jan Michelfixing slow control register feedback signals
2015-11-20 local accountupdate
2015-11-03 Jan MichelAdding uid as output to timers record.
2015-10-27 Jan MichelAdding debugging register for onewire (0x9).
2015-10-20 Jan Michelchanging handler_ipu as work-around of Synplify K2015 bug
2015-10-16 Jan MichelSeveral changes to synchronous media interfaces
2015-10-16 Jan MichelNew media interface for mixed master/slave operation
2015-10-15 Jan Michelchanging gbe_wrapper to use sctrl records
2015-10-15 local accountupdate
2015-10-13 local accountgbe serdes config file added
2015-10-13 local accountremoved rtanscript
2015-10-13 local accountupdated gbe
2015-10-13 Jan Michelnew register handler with records
2015-08-10 Jan Michelall channels working on hub
2015-08-06 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-08-06 Cahitieee standard packages should be used
2015-08-06 Jan Michelupdate
2015-08-06 Jan Michelupdate
2015-08-06 Jan Michelupdate
2015-08-06 Jan Michelupdate
2015-08-06 Jan Michelupdate
2015-08-06 Jan Micheludpate
2015-08-06 Jan Micheladded new gbe design
2015-07-22 Jan Michelupdating sync media interfaces, some rework still neede...
2015-07-14 Jan Michelignoring some new Diamond files
2015-07-14 Jan Micheladd rate setting feature to SPI interface
2015-07-09 Jan Micheladded a new fifo and a hub wrapper using records
2015-06-23 Jan Micheladding new sync media interface using 4 links
2015-06-23 Jan Michelchanging sync media interface
2015-06-09 Jan Michelfix wrongly connected control register
2015-06-09 Jan Micheladded entity for reading SCI bus
2015-06-08 Andreas NeiserAllowed 14 data buffers in endpoint
2015-06-05 Jan Micheladded few syn_hier constraints
2015-06-03 Jan Michelnew files for TRB3sc
2015-05-27 Andreas NeiserAllowed 13 data buffers in endpoint (dont know if adder...
2015-05-20 Jan Micheladded serdes channel 3 to med_sfp_sync
2015-03-20 Cahitpll IP moved to dirich
2015-03-20 CahitIP cores for ecp5
2015-03-19 Cahittrbnet fifos are generated for ecp5
2015-03-17 Jan Michelfixed a wrong signal name
2015-03-06 MapsAdded more FIFOs to the directory
2015-03-05 Jan Michelsome debug additions to uart
2015-02-13 Jan Michelchanged cdc fifo to ebr based
2015-02-13 Jan Michelchanged uart ctrlbus interface to records
2015-01-09 Jan Micheladded endpoint with records as ports - only slow contro...
2015-01-06 Jan MichelHouston, we found a bug... the hub data handler messed...
2014-12-19 Manuel PenschuckGbE: Source address configurable
2014-12-08 Jan MichelMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-12-08 Jan Micheladdressing bux fixed
2014-12-05 Jan Michelpatched fifos for ipexpress error
2014-11-21 Jan Michelgbe update
2014-11-17 Jan Michelgbe update
2014-10-12 Manuel PenschuckIncreased number of addition read-out port of TRB3...
2014-09-05 Jan Michelupdated bus_handler_record
2014-09-03 Cahitconflict fix and merge
2014-09-03 Cahit31 bit std_logic array
2014-08-04 Jan MichelAdded regio bus handler version using records for bus...
2014-08-04 Jan MichelAllowed more data buffers in endpoint.
2014-07-30 Jan Micheladded record for trigger and readout ports
2014-07-30 Jan Micheladded optional selection of bit width to spi interface
2014-07-22 Jan Micheladded record for bus handler ports
2014-07-07 Jan Micheladded multiple outputs to uart module
2014-07-02 Jan Micheladded a UART module
2014-07-01 Jan Micheladded uart
2014-06-26 Jan Michelgbe update
2014-06-24 Jan Micheladded locking feature for SPI port
2014-05-25 Ludwig Maiercomponets fix?
2014-05-22 Jan MichelMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-05-22 Jan Michelupdate
2014-05-22 Andreas NeiserSetting default PORT_MASK_ENABLE as in actual declarati...
2014-05-15 Jan Micheladded few more registers to represent configuration...
2014-05-15 Jan MichelRemoved the CompileVersion field in favor of a larger...
2014-05-14 Jan Micheladded bus_handler from TDC to trbnet
2014-05-12 Jan Michelchanged generic COMPILE_VERSION from 16 to 64 bit
2014-05-08 Jan Michelsmall clean-up in hub files
2014-05-04 Jan Michelupdate
2014-04-23 Jan Michelgbe update
2014-04-13 Jan Michelupdate
2014-03-26 Jan Michelgbe update
2014-03-24 Jan Michelcorrected libs for ECP3 serdesses
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