]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/shortlog
dirich.git
2022-01-18 Adrian Weberprepare combiner for potential shift to retransmission...
2021-10-31 Adrian Weberadd SIG(5) with output of 2.5V to fix startup issue... blackcat deepsea
2021-09-20 Adrian Weberrename of dirich5s files for name appearance in bitfile
2021-09-13 Adrian Weberadd new board DiRICH5s with some debug settings
2021-09-13 Adrian Webersmall fixes related to trbnet updates
2021-08-03 Adrian Weberchange calibration range to lower values due to problem...
2021-06-01 Adrian Weberswitch threshold firmware between DiRICh versions by...
2021-05-24 Adrian Weberfix online calibration for full backplane in CBM enviro...
2021-03-16 Adrian Weberconnection of trigger type to DLM trigger generator...
2021-02-01 Adrian Weberinclude original register 0x006 information to calibrat...
2021-02-01 Adrian WeberIncrease number of connected boards for calib from...
2021-01-19 Adrian Weberadd missing files from last commit
2021-01-19 Adrian Weberexchange MBS logic to new DLm to CTS logic. No inbetwee...
2021-01-12 Adrian Weberchange of the calibration clock to a derived clock...
2020-10-15 Adrian WeberAdded DLM signal to RJ45 Port for debugging
2020-10-08 Thomas Gesslercombiner_cts: Change uplink to 2.4 Gbps
2020-10-06 Adrian Weberextra control for refTime channel on online calibration
2020-10-02 Adrian Webercombiner CTS with calibration and TDC activated.
2020-09-30 Adrian Weberminor changes to TDC/Calib handling
2020-09-23 Adrian Weberpreparation and inclusion for calibration on data path...
2020-09-23 Adrian Weberdifferent way of calculation for ram addressing due...
2020-09-21 Adrian Webermbs trigger isgnal generation is moved to deciated...
2020-09-21 Adrian Weberminor fix for a version without TDC. Now CTS is functio...
2020-09-18 Adrian WeberIncluded MBS, TDC and a online calib entity for MBS...
2020-09-03 Adrian Weberrecovered clock for mbs and debug outputs on rj45
2020-08-31 Adrian Weberadded MBS to combiner. First test. Will be optimised
2020-08-31 Adrian Weberdeleted obsolet files; file are now in cri repository
2020-07-14 Adrian Webercleanup of code and deleted obsolet files
2020-07-13 Adrian Weberdata sending from combiner; NOT as GbeEvents. Now own...
2020-07-06 Adrian Webermerge
2020-07-06 Adrian WeberMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2020-07-06 Adrian Weberdata is sending from combiner and is received by CTS...
2020-07-03 Ingo Froehlichsmall fixes to make it compile again
2020-07-02 Adrian Weberentity to send data from event packer to API/CRI; not...
2020-06-30 Adrian Weberdata handler and changed hub for CRI data receiving...
2020-06-30 Adrian Weberpseudo data readout for combiner with cts. Test has...
2020-06-27 Adrian Weberfunctional Combiner cts readout with internal trigger...
2020-06-24 Adrian WeberMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2020-06-24 Adrian WeberFunctional Trigger with integrated CTS, if no Readout...
2020-06-23 Jan Michelchange dirich project to new Serdes files
2020-06-22 Adrian WeberStart of inclusion of Data from FEE in Path to CRI...
2020-06-18 Adrian Weberfixed the reset to a more stable and well known solutio...
2020-06-17 Adrian WeberCombiner with onboard CTS. SlowControl only. Reset...
2020-06-04 Ingo Froehlichprepared for retransmission
2020-05-22 Ingo Froehlich30 seconds timeout for cfg flash, fixed typo
2020-05-22 Ingo Froehlich30 seconds timeout for cfg flash
2020-05-09 Jan Michelupdate software version and media interface files
2020-05-09 Jan Michelmake SED FPGA size flexible to cope with e.g. MDC-FEE
2020-04-21 Adrian Weberconfig_compile script for CRI server in giessen/JLU
2020-04-20 Adrian Weberstart of combiner with integrated CTS. (files for onlin...
2020-01-03 Adrian Weberpreparation of threshold FPGA for DiRICH4; still compat...
2020-01-01 Adrian Weberfix of backpressure problem in online calibration with...
2020-01-01 Adrian Webersome fixes for startup in calibration monitoring
2019-05-13 Ingo FroehlichMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2019-05-13 Ingo Froehlichadjusted cfg timeout
2019-04-29 Adrian WeberStartup fix for Online Calibration
2019-02-19 Jan MichelResize media interface region.
2019-02-19 Jan MichelMove TDC input stage closer to inputs
2019-02-18 Ingo FroehlichMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2019-02-18 Ingo Froehlichchanged config
2018-11-13 Adrian Weberbetetr flexibility + less hardware consuming monitoring
2018-09-11 Adrian Weberbugfix in monitoring -AW
2018-09-08 Adrian Weberadded Monitoring -AW
2018-08-27 Adrian Weberclean up of Calibration -AW
2018-08-24 Adrian Webererror fixes + debuging outputs
2018-08-22 a.weberdelete sim.mpf -AW
2018-08-22 Adrian Weberfixes due to simulation -AW
2018-08-21 a.weberEBR file
2018-08-21 a.weber...was not in last commit
2018-08-20 a.weberMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2018-08-20 a.webernew calibration Method; old one did not fit in FPGA -W
2018-08-16 Jan Michelfix 'included features' in Concentrator
2018-08-14 a.weberFirst working Calibration;All FPGAs as one; Chnls are...
2018-08-13 a.weberCalibration Files; First Try -AW
2018-08-08 a.weberaddress in data ; FIFO too slow (<4MB/s) -AW
2018-08-07 a.weberworking fifo; missing HubAddress in Data -AW
2018-07-24 a.weberNew Project: combiner with internal calibration - AW
2018-07-16 Jan Micheldisable unused debug registers
2018-06-14 Jan Michelchange reset handler to newer scheme
2018-06-14 Jan Michelfix calibration clock for DiRich 3
2018-06-14 Jan Michelcombiner: select right reference time input by default
2018-06-14 Jan Michelinclude dynamic word limit and increase buffer size
2018-03-28 Jan Michelfix order of interfaces and I/O standards on combiner
2018-03-08 local accountpwm with 133MHz
2018-03-08 local accountpwm with 133MHz
2018-03-08 Ingo Froehlich16 bit flash, IF
2018-01-25 Ingo FroehlichMerge branch 'master' of jspc29:dirich
2018-01-25 Ingo Froehlichadjustment, IF
2017-12-22 Jan MichelUpdate dirich diamond project and combiner trigger...
2017-11-24 local accountchange of Trigger Connection, AW
2017-11-24 local accountchange of Trigger Connection, AW
2017-11-09 Jan MichelUpdate Dirich with latest TDC code
2017-08-25 Ingo Froehlichsmall change for new flash ctrl, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-07-27 Jan MichelMove threshold FPGA design files to new vhdlbasics...
2017-07-18 Jan MichelUse raw clock rather than 200 MHz output from PLL
2017-07-18 Jan MichelAdd override option for Link control signals in combiner
2017-07-18 Jan MichelUpdate Serdes settings
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