]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/shortlog
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2014-10-26 Manuel PenschuckCTS: Migrated back to TDC 1.6.3 and code clean up
2014-10-26 Manuel PenschuckCTS: Migrated back to TDC 1.6.3 and code clean up
2014-10-26 Manuel PenschuckCBMNet: PCS-Reset issued when receive a Link-Reinit...
2014-10-26 Manuel PenschuckBillboard: Corrected HW-ID
2014-10-26 Manuel PenschuckMerge conflict
2014-10-26 Jan Micheladded checker for ADC words
2014-10-25 Manuel PenschuckCBMNET: TX-GEAR back-up
2014-10-24 Manuel PenschuckAdd Billboard design (includes storage billboard and...
2014-10-23 Jan Micheladded sed checker to ADC design
2014-10-23 Manuel PenschuckCTS: Backup before migrating to TDC v1.6.3 and MBS
2014-10-20 Cahitsymbolic links for the top entities
2014-10-20 Cahitconflict fix
2014-10-20 Cahittdc release 2.0.xx
2014-10-20 Cahittdc release 1.7.xx
2014-10-20 Cahittop file update for designs
2014-10-20 Cahitbase folder update
2014-10-20 Cahitwasa design update
2014-10-20 CahitADA Addon design update
2014-10-20 Cahit32PinAddOn design update
2014-10-20 Cahitcbmtof design update
2014-10-20 Cahitnew pll core
2014-10-20 Andreas NeiserADC: Compile script now actually works...
2014-10-20 Cahitremove obselete files
2014-10-20 Andreas NeiserADC: Patch compile script for GSI machines
2014-10-18 Manuel PenschuckCBMNet: Script to convert TrbNet into CBMNet time using...
2014-10-16 Manuel PenschuckCTS: Timestamp-Included flag was missing in the CTS...
2014-10-16 Manuel PenschuckCTS: Included bigger CBMNET read-out buffer in project...
2014-10-16 Manuel PenschuckCBMNET: Adopted peripherial test design to new pattern...
2014-10-16 Manuel PenschuckCBMNet: Private tool to analyse sync-scheme of bridge
2014-10-16 Manuel PenschuckCBMNet: Increase read-out buffer to 128 kb, TrbNet...
2014-10-15 Manuel PenschuckCreateProject: Now supports verilog-includePath and...
2014-10-15 Manuel PenschuckCBMNet: Test design adopted to new cbmnet_bridge component
2014-10-14 Manuel PenschuckCTS: Included TDC v1.7.1 and replace individual CBMNET...
2014-10-14 Manuel PenschuckTrigger and Clock Select (not working, but commit neces...
2014-10-14 Manuel PenschuckCBMNet: Encapsulated whole stack into a dedicated entity
2014-10-14 Manuel PenschuckCBMNET: Fine-Tuning of PHY
2014-10-10 Jan Michellatest version of ADC code. Processor seems to be fine...
2014-10-10 Jan Micheladded clock for power converters to central FPGA
2014-10-06 Jan MichelLatest version of adc code, with status trigger
2014-09-30 Jan Micheladded SED to hub design and switched to new Diamond
2014-09-30 Jan Micheladded 4 MHz clock output for Enpirion regulators
2014-09-28 Manuel PenschuckCTS: Back-Up before migrating to CBMNet LPv3
2014-09-28 Manuel PenschuckCBM: Wrong status bits for event packer; CTS: clean up
2014-09-24 Manuel PenschuckCBM: Timing issues in sync module due to meta-stab...
2014-09-22 Manuel PenschuckCTS: Included sync module, introduced new constraints...
2014-09-22 Manuel PenschuckCBMNet: First version of sync-module (not fully tested...
2014-09-19 Jan Michelchanged SED checker to use new record based control...
2014-09-15 Jan Michelchanged reset behavior of external clock selection...
2014-09-05 Jan Michellatest adc handler. acknowledges triggers, no readout
2014-08-21 Ludwig MaierRevert "cleanup adc handler"
2014-08-21 Ludwig MaierRevert "tmp"
2014-08-21 Ludwig MaierRevert "nxyter, new working adc handler"
2014-08-21 Ludwig MaierRevert "nxyter, new working adc handler 2"
2014-08-21 Ludwig MaierRevert "nxyter: calibration trigger bug removed"
2014-08-21 Ludwig MaierRevert "nxyter: keep status, working so far"
2014-08-21 Ludwig MaierRevert "geht garnicht"
2014-08-21 Ludwig Maiergeht garnicht
2014-08-21 Ludwig Maiernxyter: keep status, working so far
2014-08-21 Ludwig Maiernxyter: calibration trigger bug removed
2014-08-18 Jan Michellatest status of ADC read-out
2014-08-18 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-08-18 Cahitcbmtof clock manager design
2014-08-14 Ludwig Maiernxyter, new working adc handler 2
2014-08-14 Ludwig Maiernxyter, new working adc handler
2014-08-14 Ludwig Maiertmp
2014-08-14 Ludwig Maiercleanup adc handler
2014-08-14 Ludwig Maiertry new clock domains in nx_data_receiver
2014-08-10 Manuel PenschuckReadout seems to work with TrbNet test-pattern generator
2014-08-07 Manuel PenschuckCBMNet: data_stop-related timing problem in combination...
2014-08-05 Manuel PenschuckCBMNet readout: Debug-Design for Periph-FPGA with Test...
2014-08-04 Jan Micheladded entities for proper ADC readout, reorganized...
2014-07-31 Cahittdc v1.6.3 compatibility with the tdc v1.7.1
2014-07-29 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-29 Cahit32PinAddOn design is brought up-to-date with tdc v1.7.1
2014-07-29 Cahittdc v1.7 and v1.7.1 release
2014-07-29 Jan Michelcreated two CTS constraints files for compatibilty...
2014-07-28 Manuel PenschuckMigrated CTS constraints to Diamond 3.2 (Synplify I...
2014-07-28 Manuel PenschuckMonitoring and Debug features added to CBM-Readout...
2014-07-25 Jan Michelfew more debugging regs for ADC
2014-07-24 Jan Michelsome additional registers for ADC control
2014-07-23 Jan Michelfirst running ADC AddOn version
2014-07-22 Jan Michelnext step towards running ADC board
2014-07-18 Manuel PenschuckCBMNet: Simulation of TrbNet -> CBMNet readout path...
2014-07-18 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-18 Cahittidy up
2014-07-17 Ludwig Maiernxyter ts/adc timestamp delay auto adjust entity implem...
2014-07-17 Manuel PenschuckCBMNet readout backup
2014-07-17 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-07-17 CahitTDC version v1.6.3 brought uptodate with the new config...
2014-07-17 CahitGeneral Purpose project brought uptodate with tdc core...
2014-07-16 Ludwig Maiernxyter ts/adc timestamp delay auto adjust entity implem...
2014-07-16 Ludwig Maiernxyter: bug fix in slow control
2014-07-16 Andreas NeiserADC: Keeping the ADC SPI pins low (also PULLMODE=DOWN...
2014-07-07 Jan Micheladded flexible UART to all 4conn AddOns via FPGA5_3V3...
2014-07-07 Andreas NeiserADC: Adding many missing things to LPF files...how...
2014-07-07 Andreas NeiserADC: More nxyter like CLK usage...not tested yet
2014-07-07 Andreas NeiserADC: Switching to other CLK also does not help...
2014-07-07 Andreas NeiserADC Addon: Fix CS numbering
2014-07-02 Jan Michelupdate to CTS project file for TDCs
2014-07-02 Jan Michelremoved fast signals from debug word
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