]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/shortlog
dirich.git
2019-02-18 Ingo Froehlichchanged config
2018-09-11 Adrian Weberbugfix in monitoring -AW
2018-09-08 Adrian Weberadded Monitoring -AW
2018-08-27 Adrian Weberclean up of Calibration -AW
2018-08-24 Adrian Webererror fixes + debuging outputs
2018-08-22 a.weberdelete sim.mpf -AW
2018-08-22 Adrian Weberfixes due to simulation -AW
2018-08-21 a.weberEBR file
2018-08-21 a.weber...was not in last commit
2018-08-20 a.weberMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2018-08-20 a.webernew calibration Method; old one did not fit in FPGA -W
2018-08-16 Jan Michelfix 'included features' in Concentrator
2018-08-14 a.weberFirst working Calibration;All FPGAs as one; Chnls are...
2018-08-13 a.weberCalibration Files; First Try -AW
2018-08-08 a.weberaddress in data ; FIFO too slow (<4MB/s) -AW
2018-08-07 a.weberworking fifo; missing HubAddress in Data -AW
2018-07-24 a.weberNew Project: combiner with internal calibration - AW
2018-07-16 Jan Micheldisable unused debug registers
2018-06-14 Jan Michelchange reset handler to newer scheme
2018-06-14 Jan Michelfix calibration clock for DiRich 3
2018-06-14 Jan Michelcombiner: select right reference time input by default
2018-06-14 Jan Michelinclude dynamic word limit and increase buffer size
2018-03-28 Jan Michelfix order of interfaces and I/O standards on combiner
2018-03-08 local accountpwm with 133MHz
2018-03-08 local accountpwm with 133MHz
2018-03-08 Ingo Froehlich16 bit flash, IF
2018-01-25 Ingo FroehlichMerge branch 'master' of jspc29:dirich
2018-01-25 Ingo Froehlichadjustment, IF
2017-12-22 Jan MichelUpdate dirich diamond project and combiner trigger...
2017-11-24 local accountchange of Trigger Connection, AW
2017-11-24 local accountchange of Trigger Connection, AW
2017-11-09 Jan MichelUpdate Dirich with latest TDC code
2017-08-25 Ingo Froehlichsmall change for new flash ctrl, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-08-22 Ingo Froehlichnew dirich flash scheme, IF
2017-07-27 Jan MichelMove threshold FPGA design files to new vhdlbasics...
2017-07-18 Jan MichelUse raw clock rather than 200 MHz output from PLL
2017-07-18 Jan MichelAdd override option for Link control signals in combiner
2017-07-18 Jan MichelUpdate Serdes settings
2017-07-18 Jan Michelremove Dirich1 features by default
2017-07-18 Jan MichelUpdate compile settings to defaults from Diamond
2017-07-18 Jan MichelUpdate pull resistors on Link control lines
2017-07-18 Jan MichelMove some MachXO3 files to new repository 'vhdlbasics'
2017-06-22 local accountMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2017-06-22 local accountlatest Version of threshold FPGA - FLASH included
2017-05-31 Jan MichelChange reset to include clear on reset.
2017-05-18 local accountAddes Flash support and minor fixes for MachXO34300E
2017-05-18 local accountAddes Flash support and minor fixes for MachXO34300E
2017-05-14 Jan Michelone lpf file for each Dirich version because current...
2017-05-14 Jan Michelcount SPI pins from 0 to 1, not 1 to 2
2017-05-10 Jan Michelfix names of SPI ports
2017-04-25 Cahitsolved conflicts
2017-04-25 Cahituploaded extre files
2017-04-24 local accountMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2017-04-24 local accountthreshold-fpga design with spi connection and preparati...
2017-04-24 Jan MichelUpdate Dirich design with new SPI port and option to...
2017-04-24 Jan MichelUpdate pinout files for all FPGA
2017-04-24 Jan MichelUpdate placement of serdes in combiner
2017-01-24 Jan MichelUpdate dirich with minor changes
2017-01-24 Jan MichelUpdate threshold FPGA code
2017-01-24 Jan MichelCombiner: default trigger input selection corrected
2017-01-24 Jan MichelAdd adapted version of PWM for external threshold FPGA
2016-10-27 local accountImplemented SPI and changed to testboard
2016-08-25 Jan MichelFixing conflicts due to reformatting of code
2016-08-25 Jan Micheladd pulldown to control pins
2016-08-25 Jan MichelFew minor changes to combiner
2016-08-22 Cahitcorrected databuffer threshold calculation for the...
2016-08-22 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2016-08-19 Jan MichelAdd current serdes cores to git
2016-08-18 Jan MichelAdding necessary changes to allow reading of ADC on...
2016-07-26 Jan MichelUpdate dirich with LED for PLL lock
2016-07-26 Jan Michelchange media interface clocks for non-synchronous clock...
2016-07-26 Jan MichelUpdate pinout files
2016-07-26 Jan MichelAdd design skeleton for PWM FPGAs
2016-07-15 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2016-07-15 Cahitedited compile config for ecp5 compilation
2016-07-11 Jan Michelchanged feedback in pll, lower frequency pwm, flash...
2016-07-06 Jan MichelUpdate dirich files
2016-06-26 Cahitadded link to the tdc repo for dirich top module
2016-04-01 Jan MichelCommitting missing changes from depc363
2016-03-21 Cahitcorrected merge
2016-03-21 Cahitupdated project file, config compile file, tdc version...
2016-03-18 Jan MichelDirich update: input clock 200 MHz, flash connected...
2016-03-18 Jan MichelMinor updates to dirich design and lpf
2016-03-18 Jan MichelAdding lpf and design for combiner board
2016-03-04 Jan MichelAdding first files for DiRich combiner module. Not...
2016-01-22 Jan MichelFixing some mistakes in the DiRich lpf
2016-01-22 Jan MichelUpdating dirich lpf
2016-01-21 Jan MichelAdding PWM generator incl. temperature compensation...
2016-01-06 Jan MichelAdding preliminary pinout and device config for dirich
2016-01-06 Jan MichelMoving Diamond Project
2016-01-06 Jan MichelFile update, compiling, but media interface missing
2016-01-06 Jan MichelAdding ecp5 libs
2016-01-06 Jan MichelMore DiRich files
2015-12-22 Jan MichelAdding first files for dirich project. Not compiling...