]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/shortlog
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2025-02-10 Jan Micheladd missing fd broadcast to hub master
2025-01-14 Jan Michelupdate streaming accelerator to work with Hades CTS
2024-12-20 Jan MichelMerge branch 'origin/updated_ecp5_serdes'
2024-12-20 Jan Micheledge detect for fpga reboot updated_ecp5_serdes
2024-12-13 Jan Micheladd option to remove data output from CTS to save memor...
2024-12-13 Jan Michelre-add small slow control buffer in GbE (4k instead...
2024-10-21 Jan Micheladd debug line for CV
2024-10-21 Jan Michelfix reboot on reset sequence for ECP5
2024-08-07 Jan Micheladd ecp5 memory block 36x1k
2024-05-17 Jan Michelfix old reset signal in sync_control, enable ECP5_RESET...
2024-05-10 Jan Micheladd missing changes to control signals
2024-05-08 Jan Micheladd ECP3 2x64k fifo
2024-05-08 Jan Micheladd ECP3 2x64k fifo
2024-05-08 Jan Michelchanged ECP5 Serdes settings
2024-05-08 Jan Michelchange reboot code to prevent race condition between...
2024-02-15 Jan Michelchange timer range to ~15s
2024-02-15 Jan Michelfix timer in ECP5 media interface
2024-02-14 Jan Micheladd an uptime timer to ecp5 media interfaces
2024-02-14 Jan Michelchanged few memories to use block RAM instead of distri...
2023-09-20 Jan Michelremove second tx reset from dual
2023-09-18 Jan Micheladd few debug ports to GbE
2023-09-18 Jan MichelIPU reset makes release
2023-08-28 Jan Michelfix syntax error
2023-08-23 Jan Micheladd hub status register 0x80++ to data bus at 4180++
2023-08-23 Jan Micheladd option to disable readout of word alignment in...
2023-07-20 Jan Micheladd generic to use ecp5 serdes with changed reset logic
2023-07-20 Jan Michelrevert change of LOL settings in ECP5 serdes
2023-07-20 Jan Micheladd further conditions to TRM reading in hub
2023-07-20 Jan Micheladd signal in advance of reboot to e.g. switch of Serde...
2023-07-20 Jan Michelmove unused files to old directory
2023-06-28 Jan Micheladd long reset signal for i2c bus
2023-06-28 Jan Michelfix reset receiving in GbE endpoint
2023-06-28 Jan Michelfix reset generation via GbE - failed in 1% of cases
2023-06-28 Jan Micheladd external slow control bus (flashsettings, debuguart...
2023-06-28 Jan Micheladd option to generate reset signal in ECP5 with fallin...
2023-04-12 Jan Micheladd support for TMP112 temperature sensor and its 13bit...
2023-02-10 Jan Micheladd gbe ecp5 ram for new ping
2023-02-10 Jan Micheladd external reset to clock handler
2023-02-10 Jan Michelupdate ecp5 media interfaces with 2-link interface...
2023-01-09 Jan Michelchange reset of GbE link autonegotiation to run even...
2022-12-15 Jan Micheladd GbE ping module from blackcat branch
2022-12-15 Jan Micheladd bus master input to accel hub
2022-11-01 Jan Micheladd input for automatic settings from flash to hub...
2022-10-27 Jan Micheladd status port to gbe wrapper for possible LED use
2022-08-23 Jan Micheladd adc reader to components, add new memory file
2022-08-11 Jan Michelstable GbE link: change reset for sgmii in ECP5
2022-08-11 Jan MichelGbE:
2022-08-09 Jan Michelrename gbe wrapper file
2022-08-09 Jan Michelfix ecp5 gbe_wrapper, remove _single from name for...
2022-07-22 Jan Micheladd bugfixes from aacbbc8a26fcaf865c039b3388b7572a2f1712ac
2022-07-01 Michael BoehmerLED ACT added
2022-07-01 Jan MichelInclude ecp5 gbe files in main branch
2022-06-30 Jan Micheladd new i2c for combined temperature and id chip tmp117
2022-06-30 Jan Micheladd bug fix for read signal in slow control interface...
2022-06-30 Jan Michelfixed new standalone endpoint for slow control
2022-06-30 Jan Micheladd default values to gbe_wrapper to simplify partial...
2022-06-30 Jan MichelAdd new endpoint with slow control only, no MII, just...
2022-06-29 Michael BoehmerECP5 GbE stuff (MB)
2022-06-29 Michael BoehmerMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2022-06-29 Michael BoehmerRSL for SerDes, some ECP5 cores
2022-06-28 Jan Micheladd option to reboot-on-reset to reload handler
2022-06-13 Jan Micheladd register for address setting to hub
2022-06-08 Michael BoehmerGbE bug on SCTRL fixed, causing the last word of last...
2022-05-04 Adrian WeberSERDES cores and entity for 240MHz connection of ECP5...
2022-05-04 Adrian Weberfix for CONF_ADDRESSES for trb_net16_hub_base.vhd error...
2022-03-20 Michael Boehmerfixed write bug in SCI reader
2022-03-15 Jan Micheladd registers to update network address
2021-11-10 Michael Boehmertext formating
2021-11-09 Michael Boehmerfile permissions fixed
2021-11-09 Michael Boehmer1.25Gbps media interfaces without retransmission
2021-11-09 Michael BoehmerSerDes files for 1.25Gbps operation (P-ONE?)
2021-11-09 Michael BoehmerMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2021-11-09 Michael Boehmerpermissions of files changed
2021-10-26 Jan Micheladd Serdes configurations for ECP5
2021-08-23 Jan Michelnew hub register to store status of slow control hub...
2021-08-11 Jan Micheladd missing PCS file
2021-08-09 Jan Michelupdate ECP5 media interface
2021-08-09 Jan Micheladd new ECP5 fifos
2021-07-02 Jan Micheladd a 36x16 fifo for ECP5
2021-07-02 Jan Michelchange maximum data buffer size to 32k
2021-06-08 Thomas Gesslertrb_net_xdna: Add option for external DNA
2021-06-01 Jan Micheladd register 0x44 - default and broadcast addresses
2021-04-20 Thomas GesslerXCKU MGTs: Set free-running clock freq to 40 MHz
2021-03-24 Thomas GesslerXCKU MGTs: Set DISABLE_LOC_XDC to 1
2021-03-17 Thomas GesslerClean up XCKU IP cores
2021-03-17 Thomas GesslerXCKU MGTs: Add TX PI, BUFSTATUS, optional soft rst
2021-01-13 Adrian WeberAdd I2C to streaming_port_sctrl_cts and the component...
2020-11-19 Jan Michelnew ECP5 media interface for 2 links
2020-11-19 Jan Micheladd small fifo for ECP5 in Hub
2020-11-19 Jan MichelInclude I2C to hub, add onewire monitor for old designs
2020-11-19 Jan MichelFix error register
2020-11-19 Jan Michelupdate GbE for old mdchub to match shower board settings
2020-10-08 Thomas GesslerXCKU media interface: Reset RX on errors
2020-10-08 Thomas GesslerECP3 SERDES: Add core for 2.4 Gbps with 240 MHz
2020-09-30 Thomas GesslerAdapt Xilinx SYSMON reader to 120 MHz clock
2020-09-30 Thomas GesslerXCKU MGTs: Change from quads to individual links
2020-09-18 Thomas GesslerXCKU MGTs: Expose transceiver debug ports
2020-09-11 Thomas GesslerOverhaul clocking for XCKU MGTs
2020-09-11 Thomas Gesslerfifo_18x16_dualport_oreg_xcku: Add missing ports
2020-09-04 Thomas GesslerFix Xilinx FIFO counts, remove unused FIFOs
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