]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/shortlog
dirich.git
2017-05-14 Jan Michelcount SPI pins from 0 to 1, not 1 to 2
2017-05-10 Jan Michelfix names of SPI ports
2017-04-25 Cahitsolved conflicts
2017-04-25 Cahituploaded extre files
2017-04-24 local accountMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2017-04-24 local accountthreshold-fpga design with spi connection and preparati...
2017-04-24 Jan MichelUpdate Dirich design with new SPI port and option to...
2017-04-24 Jan MichelUpdate pinout files for all FPGA
2017-04-24 Jan MichelUpdate placement of serdes in combiner
2017-01-24 Jan MichelUpdate dirich with minor changes
2017-01-24 Jan MichelUpdate threshold FPGA code
2017-01-24 Jan MichelCombiner: default trigger input selection corrected
2017-01-24 Jan MichelAdd adapted version of PWM for external threshold FPGA
2016-10-27 local accountImplemented SPI and changed to testboard
2016-08-25 Jan MichelFixing conflicts due to reformatting of code
2016-08-25 Jan Micheladd pulldown to control pins
2016-08-25 Jan MichelFew minor changes to combiner
2016-08-22 Cahitcorrected databuffer threshold calculation for the...
2016-08-22 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2016-08-19 Jan MichelAdd current serdes cores to git
2016-08-18 Jan MichelAdding necessary changes to allow reading of ADC on...
2016-07-26 Jan MichelUpdate dirich with LED for PLL lock
2016-07-26 Jan Michelchange media interface clocks for non-synchronous clock...
2016-07-26 Jan MichelUpdate pinout files
2016-07-26 Jan MichelAdd design skeleton for PWM FPGAs
2016-07-15 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2016-07-15 Cahitedited compile config for ecp5 compilation
2016-07-11 Jan Michelchanged feedback in pll, lower frequency pwm, flash...
2016-07-06 Jan MichelUpdate dirich files
2016-06-26 Cahitadded link to the tdc repo for dirich top module
2016-04-01 Jan MichelCommitting missing changes from depc363
2016-03-21 Cahitcorrected merge
2016-03-21 Cahitupdated project file, config compile file, tdc version...
2016-03-18 Jan MichelDirich update: input clock 200 MHz, flash connected...
2016-03-18 Jan MichelMinor updates to dirich design and lpf
2016-03-18 Jan MichelAdding lpf and design for combiner board
2016-03-04 Jan MichelAdding first files for DiRich combiner module. Not...
2016-01-22 Jan MichelFixing some mistakes in the DiRich lpf
2016-01-22 Jan MichelUpdating dirich lpf
2016-01-21 Jan MichelAdding PWM generator incl. temperature compensation...
2016-01-06 Jan MichelAdding preliminary pinout and device config for dirich
2016-01-06 Jan MichelMoving Diamond Project
2016-01-06 Jan MichelFile update, compiling, but media interface missing
2016-01-06 Jan MichelAdding ecp5 libs
2016-01-06 Jan MichelMore DiRich files
2015-12-22 Jan MichelAdding first files for dirich project. Not compiling...