| 2015-03-05 |
Jan Michel | updated CTS to Diamond 3.4, made new simple default... |
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| 2015-03-03 |
Jan Michel | moved CTS with Cbmnet to own config file |
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| 2015-03-03 |
Jan Michel | adjust uart output driver |
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| 2015-02-24 |
Tobias Weber | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-02-24 |
Tobias Weber | additional buffers for synchronizing hitbus and szintil... |
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| 2015-02-24 |
Tobias Weber | high active reset used in all entities and synchronous... |
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| 2015-02-23 |
Tobias Weber | Merge branch 'master' into MuPix |
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| 2015-02-23 |
Tobias Weber | Solved some timing error. But there is one timing error... |
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| 2015-02-23 |
Tobias Weber | some typo errors. Design generates bitstream but has... |
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| 2015-02-23 |
Tobias Weber | adjustable max size for a mupix data frame |
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| 2015-02-23 |
Tobias Weber | Error in constraints for auxilliary signals |
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| 2015-02-23 |
Tobias Weber | Include time walk measurement into existing design |
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| 2015-02-23 |
Tobias Weber | entity for time walk measurement |
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| 2015-02-18 |
Jan Michel | added clock switch to gbe hub - if configured for exter... |
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| 2015-02-14 |
Cahit | tdc_v2.1.2 version release |
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| 2015-02-13 |
Jan Michel | correcting changes in lpf files |
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| 2015-02-13 |
Jan Michel | updated central hub with new uart |
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| 2015-02-04 |
Cahit | projects brought up-to-date with tdc_v2.1.1 |
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| 2015-02-03 |
Cahit | periph_padiwa is brought up-to-date with tdc_v2.1.1 |
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| 2015-02-02 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-02-02 |
Cahit | ring buffer full threshold register moved to 0xc804 |
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| 2015-02-02 |
Cahit | cbmtof is brought up-to-date with tdc_v2.1.1 |
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| 2015-02-02 |
Cahit | tdc version 2.1.1 is released |
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| 2015-02-02 |
Cahit | edge type correction for single edge designs |
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| 2015-01-28 |
Jan Michel | changed pulser project compile script |
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| 2015-01-23 |
Cahit | new fifo core with dynamic threshold |
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| 2015-01-23 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2015-01-23 |
Cahit | tdc version 2.1 is released |
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| 2015-01-21 |
Jan Michel | updated pulser design |
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| 2015-01-21 |
Tobias Weber | Add a Sensor ID to data frames. |
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| 2015-01-15 |
Jan Michel | prepared design for pulser |
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| 2015-01-14 |
Tobias Weber | Trigger bypass is working now. Inactive sensors are... |
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| 2015-01-14 |
Tobias Weber | Broadcast for reseting the of eventcounters and timesta... |
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| 2015-01-14 |
Andreas Neiser | ADC: convert explicitly to std_logic_vector |
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| 2015-01-12 |
Andreas Neiser | Base: create_project: allow whitespace in prj statement... |
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| 2015-01-12 |
Andreas Neiser | ADC: Make compile_constraints.pl work with base/create_... |
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| 2015-01-09 |
Jan Michel | using trb_net16_endpoint_hades_full_handler_record... |
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| 2015-01-08 |
Andreas Neiser | ADC: Make sim work on non-Frankfurt systems, dont forge... |
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| 2014-12-22 |
Tobias Weber | Add trigger bypass to Trigger Handler and flag to ignor... |
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| 2014-12-17 |
Jan Michel | updated ADC with new pulse shape processing. Simulation... |
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| 2014-12-17 |
Jan Michel | added MAC component |
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| 2014-12-15 |
Manuel Penschuck | CTS: Moved selection of trigger module into config... |
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| 2014-12-11 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2014-12-11 |
Cahit | light mode tdc is implemented |
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| 2014-12-11 |
Cahit | tp modules are linked to the current release directory |
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| 2014-12-11 |
Cahit | cbmtof design brought up to tdc_v2.0 |
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| 2014-12-08 |
Andreas Neiser | ADC: Sim: Cosmetic fixes |
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| 2014-12-08 |
Andreas Neiser | ADC: Sim: Correct compile order for VHDL files |
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| 2014-12-08 |
Andreas Neiser | ADC: Sim: Add dummy version.vhd for simulation |
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| 2014-12-08 |
Andreas Neiser | ADC: Sim: use relative path names, work library still... |
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| 2014-12-05 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2014-12-05 |
Cahit | calibration and data trigger switching problem is fixed |
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| 2014-12-05 |
Jan Michel | added buffer size setting to config file of 32pin AddOn |
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| 2014-12-05 |
Jan Michel | added included features to ADC config file |
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| 2014-12-05 |
Jan Michel | added few more control registers for ADC |
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| 2014-12-04 |
Andreas Neiser | CTS: map needs correct arguments...args |
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| 2014-12-04 |
Cahit | projects made compatible with tdc_v2.0.0 |
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| 2014-12-04 |
Cahit | trigger window bug fix and constraints update for v2.0.0 |
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| 2014-12-03 |
Cahit | conflict fix |
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| 2014-12-03 |
Cahit | tdc_v1.6.3 is made back compatible |
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| 2014-12-03 |
Cahit | encoder name correctiongit add Channel.vhd Channel_200... |
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| 2014-12-03 |
Andreas Neiser | CTS: Minor compile scripts fixes |
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| 2014-12-02 |
Manuel Penschuck | CTS: Clock select based on config-constant |
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| 2014-12-02 |
Manuel Penschuck | CTS: ITC on input mux |
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| 2014-12-02 |
Manuel Penschuck | CTS: Total dead time counter |
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| 2014-12-02 |
Andreas Neiser | CTS: Compile script uses single core par, fix bitgen... |
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| 2014-12-02 |
Andreas Neiser | CTS: Remove DRIVE for JTTL ports |
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| 2014-12-02 |
Andreas Neiser | Should be rom_encoder_3... |
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| 2014-12-02 |
Andreas Neiser | CTS: Make it work if no CBM but TDC is enabled |
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| 2014-12-02 |
Andreas Neiser | CTS compile script fixes to make it work for Manuel... |
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| 2014-12-02 |
Andreas Neiser | CTS changes to make 1.7.x / 1.6.3 TDC switch easier |
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| 2014-12-02 |
Andreas Neiser | TDC 1.6.3 changes to conform with 1.7.x component handling |
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| 2014-12-02 |
Cahit | rom encoder update for tdc 1.6.3 |
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| 2014-12-02 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2014-12-02 |
Cahit | tdc_components.vhd for tdc version 1.6.x |
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| 2014-12-02 |
Andreas Neiser | CTS: Compile on lxhadeb07 does not work...Synplify... |
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| 2014-12-02 |
Andreas Neiser | CTS: Compile scripts updated, syncing config.vhd |
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| 2014-12-01 |
Jan Michel | update ADC code |
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| 2014-12-01 |
Cahit | 32PinAddOn Design updated for tdc_v2.0 |
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| 2014-12-01 |
Cahit | tdc release notes update |
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| 2014-12-01 |
Cahit | Merge branch 'master' of jspc29.x-matter.uni-frankfurt... |
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| 2014-12-01 |
Cahit | GPIN addon design pin correction |
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| 2014-12-01 |
Cahit | top files and component files for the tdc version 2.0 |
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| 2014-12-01 |
Cahit | unnecessary files are removed from tdc test folder |
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| 2014-12-01 |
Cahit | constraints update for version 1.6.3 |
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| 2014-12-01 |
Cahit | tdc_v2.0 release |
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| 2014-11-28 |
Andreas Neiser | ADC: correct address range to include invalid words... |
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| 2014-11-28 |
Jan Michel | one more attribute to get timing right |
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| 2014-11-23 |
Tobias Weber | Finally Desgin with 2 mupix boards at one periph fpga... |
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| 2014-11-21 |
Tobias Weber | Now Readout of first sensor works, but second does... |
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| 2014-11-21 |
Jan Michel | fixed timeout on sctrl bus in hub without gbe |
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| 2014-11-21 |
Tobias Weber | FiFo 2k depth, 36 bit width |
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| 2014-11-21 |
Tobias Weber | Works fine with 1 sensor per fpga. Implementing 2 senso... |
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| 2014-11-06 |
Tobias Weber | Independent register for second injection DAC |
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| 2014-11-06 |
Tobias Weber | Add a clock divider to the graycount generator |
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| 2014-11-06 |
Manuel Penschuck | CBMNet: Reboot DLM availabe (send 3 DLMS: 0xd, 0x1... |
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| 2014-11-06 |
Manuel Penschuck | CTS: JTTL(15) functions as reboot input (provide 1... |
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| 2014-11-03 |
Manuel Penschuck | CBMNet: Reminder to myself: Don't connect the Reset... |
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| 2014-11-03 |
Manuel Penschuck | CTS: Back up TDC 1.6.3, Better constraints for design |
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| 2014-11-03 |
Manuel Penschuck | CBMNet: Test design compatible to bridge, test-lines... |
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jspc29 / trb3.git / shortlog