jspc29.x-matter.uni-frankfurt.de Git

]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/shortlog

2015-06-13	Andreas Neiser	use 16 cores now	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Lets try without the state debug stuff	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	some more registers for slow control signals	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	CONTROL better clock domain crossing...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	snapshot modelsim project file	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	DEBUG should be in clk_rd aka ADC clock domain	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	snapshot epoch counter at trigger	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	implement trigger delay	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	writing out the epoch counter	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	adding dpram_50x16	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	statebits also to ADC clock domain	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	TRIGGER_OUT in adc clock domain	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Moving CONF to ADC clock domain...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Simu works	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Multicycle does not really solve it I guess	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Use ringbuffer in adc readout	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	adding 50x16 ringbuffer	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	enabling multicycles again	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Add constraints with pure underscore inst specifiers...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	adding timings for synplify	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Now all regions are defined properly according to floor...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Snapshot modellsim project file	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	left adc stuff is larger...args	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Manually locating the ADC processor stuff	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Maybe improved config signal handling	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	also modify ram readout for buffered ram	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Enable outreg again	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	defining UGROUPS	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Revert "Adding HGROUPs again..."	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Adding HGROUPs again...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Remove hierarchical stuff	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	unconstrain also other direction...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	snapshot modelsim project file	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	relax clock constraints for slowcontrol stuff	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Minor index offset fix	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	adding files to project	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	little fix	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	finished config register stuff (untested...)	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Preparing CFD readout mode config	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Reformat source of ADC handler	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Revert "testing with smaller ram counter"	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	this trigger should produce readout race condition	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	resize ram counters properly	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	testing with smaller ram counter	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Add busy logic to prevent race conditions	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Maybe works	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Try this as ram readout	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	No output reg for dpram	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Adding buffer readout	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Finish RAM event writing	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Adding dual port RAM for readout	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Integral delay correctly set	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Integrator, ZeroX detect	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Simulation runs with no warnings	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Init config prevents sim messages	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Little fix and formatting	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	CFD signal implemented, not tested yet	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Changes to properly init for simulation...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Implement debug slowcontrol stuff	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Rename config record names	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Correct baseline subtracted signal generated	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Finally defined baseline, but averaging not working yet	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Default value in ADC makes baseline calculation work	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Baseline init problem to be solved, but simulation...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Correct shift register	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Make the testbench test the CFD processor	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Baseline averaging works maybe...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Starting standalone CFD processor	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Minor config update	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Fix for Modelsim	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Run ADC FIFO in continuous mode if CFD readout	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Introduce READOUT_MODE config option	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Make extra modelsim project for CFD	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Snapshot modelsim project file	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Data output fix	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Restart FIFO properly, otherwise sim does not work	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	use restart	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	another fix	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	more sophisticated inter process signaling...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Maybe working dummy dqsinput	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Introduce dqsinput, sufficient to simulate deserialize...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Fix	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Counter on data	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Feed all ADCs...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Sim works somehow, now feed in reasonable data	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Maybe works	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Sim not working yet	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Testbenching the AD9219 entity	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Register i'th fifo_empty signal	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Try with 80MHz	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Revert "Made each ADC chip separate entity"	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Revert "Add ADC chip entity to project"	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Remove HGROUP stuff again, maybe this is finally the...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Try with 64MHz	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Add HGROUP to FIFO, to identify it easier in floorplan	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Add ADC chip entity to project	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Made each ADC chip separate entity	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Synplify: Set clock timing for ADC to 163MHz, enable...	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Make map try harder (copied from CTS compile script)	commit \| commitdiff \| tree \| snapshot
2015-06-13	Andreas Neiser	Make mpartcre try with all seeds	commit \| commitdiff \| tree \| snapshot
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