]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/shortlog
trb3.git
2015-06-13 Andreas NeiserMake map try harder (copied from CTS compile script)
2015-06-13 Andreas NeiserMake mpartcre try with all seeds
2015-06-13 Andreas NeiserMinor simulation changes
2015-06-13 Andreas NeiserAdding pipeline to debug output
2015-06-13 Andreas NeiserChanging the PLL to 325MHz to cope with 65MS (hopefully)
2015-06-13 Andreas NeiserADC: Add 65MHz PLL to project
2015-06-13 Andreas NeiserADC: Use 65MHz sampling rate
2015-06-13 Andreas NeiserAdding 200->65 MHz PLL
2015-06-13 Andreas NeiserADC: Keep readout data lines low when not actually...
2015-06-13 Andreas NeiserUse mpartcre to find designs without timing errors
2015-06-13 Andreas NeiserLittle fix in testbench
2015-06-13 Andreas NeiserTake polarity into account for CFD subtraction
2015-06-13 Andreas NeiserMinor testbench changes, saved waveform macro
2015-06-13 Andreas NeiserInvert polarity ADC signals
2015-06-13 Andreas NeiserLittle improvements for simulation
2015-06-13 Andreas NeiserDefault values for PSA signals
2015-06-13 Andreas NeiserReformat source...
2015-06-13 Andreas NeiserOnly check trigger threshold when possible zero crossing
2015-06-13 Andreas NeiserUse readout threshold to suppress CFD readout on integr...
2015-06-13 Andreas NeiserUse registers economically
2015-06-13 Andreas NeiserFix ram_read_cfd handling
2015-06-13 Andreas NeiserMinor edits to get simulation running
2015-06-13 Andreas NeiserConfig and testbench updates
2015-06-13 Andreas NeiserFinished CFD reading state machine
2015-06-13 Andreas NeiserFirst modifications for additional CFD readout, CFD...
2015-06-05 Jan Michelremoved old test file
2015-06-05 Jan Michelnew entities and serdes configurations
2015-06-05 Jan Michelupdated periph_hub for new Diamond 3.4
2015-05-22 Cahitbugfix in compile script for wasa
2015-05-22 Cahitupdated compile script for wasa
2015-05-18 Cahitbrought the project up-to-date with tdc_v2.1.3
2015-05-08 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-05-08 Cahitbrought 32 PinAddOn project up-to-date
2015-05-08 Cahitbrought 4-conn-addon (padiwa) project up-to-date
2015-05-05 Jan Michelnew files for fpgatest design
2015-05-04 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-05-04 Cahitminor changes in the ADA project file
2015-04-28 Jan Micheladded trigger information register to CTS
2015-04-28 Jan Micheladded a sync media interface to cbmtof. Disable it...
2015-04-27 CahitADA AddOn project is brought up-to-date with tdc 2...
2015-04-17 Cahitupdated project file for SFP power read and new tdc...
2015-04-16 CahitSFP Digital Diagnostic Monitoring module implemented
2015-04-08 Cahit20MHz to 100MHz pll
2015-04-08 Cahitvarious changes in version 2.1.2
2015-04-08 Cahittdc_test is moved to the tdc repo
2015-03-13 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-03-13 Cahitrelease table written in org mode. Also a script exists...
2015-03-13 Jan Michelfixed to use internal trigger source for CTS
2015-03-05 Jan Michelupdated CTS to Diamond 3.4, made new simple default...
2015-03-03 Jan Michelmoved CTS with Cbmnet to own config file
2015-03-03 Jan Micheladjust uart output driver
2015-02-24 Tobias WeberMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-02-24 Tobias Weberadditional buffers for synchronizing hitbus and szintil...
2015-02-24 Tobias Weberhigh active reset used in all entities and synchronous...
2015-02-23 Tobias WeberMerge branch 'master' into MuPix
2015-02-23 Tobias WeberSolved some timing error. But there is one timing error...
2015-02-23 Tobias Webersome typo errors. Design generates bitstream but has...
2015-02-23 Tobias Weberadjustable max size for a mupix data frame
2015-02-23 Tobias WeberError in constraints for auxilliary signals
2015-02-23 Tobias WeberInclude time walk measurement into existing design
2015-02-23 Tobias Weberentity for time walk measurement
2015-02-18 Jan Micheladded clock switch to gbe hub - if configured for exter...
2015-02-14 Cahittdc_v2.1.2 version release
2015-02-13 Jan Michelcorrecting changes in lpf files
2015-02-13 Jan Michelupdated central hub with new uart
2015-02-04 Cahitprojects brought up-to-date with tdc_v2.1.1
2015-02-03 Cahitperiph_padiwa is brought up-to-date with tdc_v2.1.1
2015-02-02 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-02-02 Cahitring buffer full threshold register moved to 0xc804
2015-02-02 Cahitcbmtof is brought up-to-date with tdc_v2.1.1
2015-02-02 Cahittdc version 2.1.1 is released
2015-02-02 Cahitedge type correction for single edge designs
2015-01-28 Jan Michelchanged pulser project compile script
2015-01-23 Cahitnew fifo core with dynamic threshold
2015-01-23 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2015-01-23 Cahittdc version 2.1 is released
2015-01-21 Jan Michelupdated pulser design
2015-01-21 Tobias WeberAdd a Sensor ID to data frames.
2015-01-15 Jan Michelprepared design for pulser
2015-01-14 Tobias WeberTrigger bypass is working now. Inactive sensors are...
2015-01-14 Tobias WeberBroadcast for reseting the of eventcounters and timesta...
2015-01-14 Andreas NeiserADC: convert explicitly to std_logic_vector
2015-01-12 Andreas NeiserBase: create_project: allow whitespace in prj statement...
2015-01-12 Andreas NeiserADC: Make compile_constraints.pl work with base/create_...
2015-01-09 Jan Michelusing trb_net16_endpoint_hades_full_handler_record...
2015-01-08 Andreas NeiserADC: Make sim work on non-Frankfurt systems, dont forge...
2014-12-22 Tobias WeberAdd trigger bypass to Trigger Handler and flag to ignor...
2014-12-17 Jan Michelupdated ADC with new pulse shape processing. Simulation...
2014-12-17 Jan Micheladded MAC component
2014-12-15 Manuel PenschuckCTS: Moved selection of trigger module into config...
2014-12-11 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-12-11 Cahitlight mode tdc is implemented
2014-12-11 Cahittp modules are linked to the current release directory
2014-12-11 Cahitcbmtof design brought up to tdc_v2.0
2014-12-08 Andreas NeiserADC: Sim: Cosmetic fixes
2014-12-08 Andreas NeiserADC: Sim: Correct compile order for VHDL files
2014-12-08 Andreas NeiserADC: Sim: Add dummy version.vhd for simulation
2014-12-08 Andreas NeiserADC: Sim: use relative path names, work library still...
2014-12-05 CahitMerge branch 'master' of jspc29.x-matter.uni-frankfurt...
2014-12-05 Cahitcalibration and data trigger switching problem is fixed
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