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descriptionVHDL modules for low resolution clocked TDC
last changeFri, 23 May 2025 08:59:32 +0000 (10:59 +0200)
shortlog
2025-05-23 Jan Michelupdate simulation file master commit | commitdiff | tree | snapshot
2025-05-23 Jan Micheladd saving of hits exceeding maxToT commit | commitdiff | tree | snapshot
2025-01-06 Jan Michelchange to calibration trigger type A only commit | commitdiff | tree | snapshot
2024-08-29 Jan Michelfix ToTExceededCounter commit | commitdiff | tree | snapshot
2024-08-28 Jan Micheladd more hit counters commit | commitdiff | tree | snapshot
2024-08-27 Jan Micheladd counter for recorded hits and configuration info commit | commitdiff | tree | snapshot
2024-08-27 Jan Michelextend documentation and update default settings commit | commitdiff | tree | snapshot
2024-08-27 Jan Micheldo calibration only on D and A type triggers commit | commitdiff | tree | snapshot
2022-12-15 Jan Michelfix two lines in documentation commit | commitdiff | tree | snapshot
2022-12-08 Jan Micheladd data format document, slight change to header word commit | commitdiff | tree | snapshot
2022-12-02 Jan Micheladd settings for trigger window and max ToT commit | commitdiff | tree | snapshot
2022-04-29 Jan MichelMerge branch 'fra_devel' into master commit | commitdiff | tree | snapshot
2022-04-29 Jan Michelremove old files from master commit | commitdiff | tree | snapshot
2022-04-29 Jan Michelcheck in latest version of code fra_devel commit | commitdiff | tree | snapshot
2021-08-09 Jan Michelfirst version of TDC commit | commitdiff | tree | snapshot
2021-08-09 Jan Micheladd testbench and simulation files commit | commitdiff | tree | snapshot
...
heads
2 weeks ago master shortlog | log | tree
3 years ago fra_devel shortlog | log | tree
3 years ago cracow_devel shortlog | log | tree
VHDL modules for low resolution clocked TDC