]> jspc29.x-matter.uni-frankfurt.de Git - cri.git/summary
 
descriptionVHDL modules for TrbNet on CBM Xilinx hardware
last changeFri, 10 Dec 2021 15:06:35 +0000 (16:06 +0100)
shortlog
2021-12-10 Adrian Weberupdate of IP cores for Vivado 2021.2 master
2021-11-29 Adrian Weberfix of dummy assignment in regio bus handler of slowcon...
2021-11-22 Adrian Weberadd possibility to not using uplink in hubs or terminat...
2021-11-18 Adrian Weberadd separate reset signal to DCA communication (DCA...
2021-11-17 Adrian Webergeneralisation of even and odd downlinks
2021-11-16 Adrian Weberallow odd numbers of downlinks for CRI hub
2021-11-15 Adrian Webergenerate Init_endpoint ids based on SLRs of CRI
2021-10-15 Adrian Weberrestructured hub generation and reduced needed function...
2021-10-13 Adrian Webercommit again to test mirroring
2021-10-13 Adrian Weberadd calculation of is_downlink and is_uplink to general...
2021-04-26 Adrian Weberfix of a bug in reset of trbnet from trbnet bridge...
2021-04-15 Adrian Weberadd sync for preload signal with additional variable...
2021-04-08 Adrian Webersynch of DCA clock signals to sysclock for FSM to relax...
2021-04-07 Adrian Weberminor change in reset of links in cri hub. more similar...
2021-04-07 Adrian Weberadditional wait state to compensate fifo read issue...
2021-04-06 Adrian Weberset Trbnet Bridge Port to stream port. Reorder data...
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heads
3 years ago master