]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/summary
 
descriptionTRB3 VHDL
last changeMon, 22 Jul 2024 07:25:56 +0000 (09:25 +0200)
shortlog
2024-07-22 Jan Michelupdated 4conn design for optional additional trigger... master
2024-03-12 Jan Michelvarious minor edits to many projects
2024-02-15 Jan Micheladd Trb3 periph inputs to regular Input multiplexers
2024-02-15 Jan Michelincrease number of coincidences from 16 to 24 to cover...
2023-05-12 Jan Michelupdate ADA design to contain fee test signals
2023-05-12 Jan Micheladd option of reference time output on output multiplex...
2023-04-18 Jan Michelallow to have more than 8 cts input multiplexer
2023-04-12 Jan Micheladd downscaling option to CTS input modules
2022-12-15 Jan Micheladd CTS busy signal as option in output multiplexer
2022-12-15 Jan Michelenable monitoring counters by default
2022-08-11 Jan MichelCTS: support new platform on Trb3sc backplane master
2022-06-29 HADES DAQadded needed links for trb5sc/gbe_template to compile, mt
2022-06-28 Jan Michelchange compile script back to synplify_premier_dp
2022-06-28 Jan Michelfix address decoder for SED
2022-06-28 Jan Micheladd R3B timestamp receiver to CTS
2021-11-02 Jan Michelfix readback of df35 register (mult logic 0) blackcat deepsea
...
heads
10 months ago master
3 years ago blackcat
3 years ago deepsea
9 years ago MuPix
9 years ago adc_feature_extraction
9 years ago normandy
10 years ago nx_adc_failure
11 years ago mainz-testing
11 years ago ctsplacement
12 years ago mainz-a2