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update of IP cores for Vivado 2021.2
-rw-r--r-- 336 .gitignore blob | history | raw
drwxr-xr-x - endpoint_test tree | history
drwxr-xr-x - hub_test tree | history
drwxr-xr-x - src tree | history
VHDL modules for TrbNet on CBM Xilinx hardware