]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/summary
 
descriptionTrbNet VHDL code
last changeMon, 10 Feb 2025 15:41:15 +0000 (16:41 +0100)
shortlog
2025-02-10 Jan Micheladd missing fd broadcast to hub master
2025-01-14 Jan Michelupdate streaming accelerator to work with Hades CTS
2024-12-20 Jan MichelMerge branch 'origin/updated_ecp5_serdes'
2024-12-20 Jan Micheledge detect for fpga reboot updated_ecp5_serdes
2024-12-13 Jan Micheladd option to remove data output from CTS to save memor...
2024-12-13 Jan Michelre-add small slow control buffer in GbE (4k instead...
2024-10-21 Jan Micheladd debug line for CV
2024-10-21 Jan Michelfix reboot on reset sequence for ECP5
2024-08-07 Jan Micheladd ecp5 memory block 36x1k
2024-05-17 Jan Michelfix old reset signal in sync_control, enable ECP5_RESET...
2024-05-10 Jan Micheladd missing changes to control signals
2024-05-08 Jan Micheladd ECP3 2x64k fifo
2024-05-08 Jan Micheladd ECP3 2x64k fifo
2024-05-08 Jan Michelchanged ECP5 Serdes settings
2024-05-08 Jan Michelchange reboot code to prevent race condition between...
2024-02-15 Jan Michelchange timer range to ~15s
...
tags
11 years ago oldGBE last version with old GBE files
heads
2 months ago master
3 months ago updated_ecp5_serdes
23 months ago GbeLargeSctrl
2 years ago dirich5s1_new_reset_cdr_fix
2 years ago blackcat
2 years ago deepsea
2 years ago cbm_rich
3 years ago trb5_GbE
4 years ago retransmission
4 years ago syncTRB
7 years ago fixedIP
8 years ago update
11 years ago newGBE