November 2019

• Trb3sc based CTS

  There are two new setups for the central trigger system available, both based on a Trb3sc: a stand-alone version with 20 TDC channels that allows a fully independent read-out system for one Padiwa board. A 32 channel version might be available on request. One SFP allows to connect further front-end boards. a CTS to connect up to 8 front-ends boards. This requires a SFP-AddOn-v2 and an adapter board with 9 RJ connectors (shown in the photo). The front-ends can be connected directly with an optical fiber and one RJ-45 cable - no additional fan-out for the reference time is needed. It allows provides two inputs on each RJ connector to feed back trigger signals from the front-ends to the CTS.

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October 2019

• Mux-Fanout-Board

  A 16 channel 1:4 fan-out board, compatible to our usual 40-pin signal cables. The input is either on a 40-pin connector or on pin-header. Outputs are in parallel on two 40-pin connectors and 2 pin-headers.

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• Trb5sc

  The latest family member of our TRB group: Trb5sc featuring a single ECP5 FPGA for up to 32 high-resolution TDC channels or 64 general purpose LVDS I/O. The form factor is new, including an "inline" AddOn board (here: a new "4conn" AddOn). Together with the AddOn the form factor is the same as a TRB3sc without AddOn and the boards fit into the same crates.

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February 2019

• Tip of the week…

  The buffers in all FPGAs to store data are quite large to offer some flexibility, but in most applications it makes sense to constrain the maximum amount of data: The ring buffers in each TDC channel can store up to 124 words - if these are filled by noise data it may generate more than 60 us of dead time for each trigger to scan the buffers for relevant data The event buffer in each TDC can store a few thousand words in total, with a limit of typically 500 words per event ("MaxEventSize", register 0x7111) The size of each sub-event (data sent over one Ethernet link) is limited to 60 kB or about 15,000 TDC words. This limit can be reached or exceeded quite easily. The TDC and TrbNet offer two levels of data limiting: The buffer in each TDC channel can be reduced ("DataLimit", TDC GUI, register 0xc804). The amount of event data generated by an individual endpoint can be limited ("SetMaxEventSize",TrbNet -> Readout, register 0x7111). This should be…

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January 2019

• RJ45 AddOn Board

  This RJ45 AddOn board provides 12 standard network cable sockets allowing to transmit the LVDS signals via shielded cables (CAT 6, S/FTP). This reduces crosstalk and signal edge distortions on neighboring signal lines, especially for longer cables. This AddOn board uses the PADIWA 4-conn I/O schematics. The SPI lines are either available via the RJ45 sockets or on the a separate 2x10-pin connector. Furthermore, a 3.3V and 6V connection is available via a 2x2-pin connector.

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