Design Files

CTS

Date Bitfile Comment
2020-06-29 trb3_central_cts_20200629.bit
2019-01-21 trb3_central_cts_20190121_4sfp.bit no TDC, no ETM, 1 GbE, 4 SFP, 4 periph. inputs, 4 coincidences, 4 muxes
2017.11.29 trb3_central_cts_20171129_4sfp_nothingspecial.bit no TDC, no ETM, 1 GbE, 4 SFP
2016.10.06 trb3_central_cts_20161006.bit no TDC, no ETM, 1 GbE, 1 SFP, 7 inputs - 4 available on RJ45
2016.09.20 trb3_central_cts_20160920_mbsmaster_allinputs_noetm.bit no TDC, no ETM, 1 GbE, 4 SFP, 7 inputs - 2 available on RJ45, MBS trigger output
2016.01.26 trb3_central_cts_20160126.bit CTS without TDC, two GbE links, MBS module, 8 input mux

TRB3 central FPGA

Date Bitfile Comment
2020-11-29 trb3_central_gbe_20201129.bit with GbE
2020-01-09 trb3_central_hub_20200109.bit without GbE
2015.02.18 trb3_central_gbe_20150218.bit
2014.06.27 trb3_central_gbe2_20140627.bit Data loss above 1.4kByte subevent size, internal clock only
2014.06.13 trb3_central_gbe_20140613.bit internal clock only

PADIWA AddOn-4ConnAddOn

Date TDC Ch # Type Buff Bitfile Comment
2020.07.08 2.4.0 48 stretcher trb3_periph_padiwa_tdc_48_20200708.bit
2018.10.24 2.4.0 32 stretcher 4096 trb3_periph_padiwa_tdc_32_..._20181024.bit contains additional trigger generation logic in parallel
2015.08.10 2.1.5 32 DE alternating 4096 trb3_periph_padiwa_20150810.bit
2015.06.18 2.1.4 48 SE 4096 trb3_periph_padiwa_20150618.bit
2015.06.12 2.1.4 48 DE same + stretcher 4096 trb3_periph_padiwa_20150612.bit

ADA AddOn

Date TDC Ch # Type Buff Bitfile Comment
2018.08.08 2.3.0 32 stretcher trb3_periph_ADA_32ch_stretch_20180808.bit no calibration
2018.08.10 2.3.0 32 stretcher trb3_periph_tdc_ADA_16_stretch_everyfourthchannel_20180810.bit uses only every fourth channel (NINO)
2018.01.26 2.3.0 32 DE same + stretcher 1024 trb3_periph_ADA_32_stretch_20180126.bit no calibration
2017.10.11 2.3.0 32 DE same, no stretcher
4 trb3_periph_ADA_nostretch_20171011.bit new: configurable coincidence logic
2018.02.15 2.3.0 16 DE same, stretcher
4096 trb3_periph_tdc_ADA_16_str... fourth_20180215.bit uses only every fourth channel (NINO)
2015.04.08 2.1.2 32 DE same + stretcher 4096 trb3_periph_ADA_20150408.bit with SPI interface for PADI

GPIN AddOn

Date TDC Ch #
Type Buff Bitfile Comment
2018.08.07 2.3.0 24 stretch 4096 trb3_periph_gpin_20180807.bit
2015.10.07 2.2 48 DE alternating 4096 trb3_periph_gpin_20151007.bit
2015.06.18 2.1.4 24 DE same + stretcher 4096 trb3_periph_gpin_20150618.bit

32Pin AddOn

Date TDC Ch #
Type Buff/Chan Buff Bitfile Comment
2021.03.09 2.4.0 32 DE same + stretcher 32 1024 trb3_periph_32PinAddOn_20210309.bit
2016.03.24 2.3.0 32 DE same + stretcher 32 1024 trb3_periph_32PinAddOn_32ch_strch_20160324.bit
2016.03.24 2.3.0 64 DE alternating 32 1024 trb3_periph_32PinAddOn_64ch_dbl_alt_20160324.bit
2015.11.06 2.2.0 16 DE same + stretcher Flexible 4096 trb3_periph_32PinAddOn_20151106.bit

HUB AddOn

Date Other1 Other2 Bitfile Comment
2015.09.22 - - trb3_periph_hub_20150922.bit SFP diagnostic interface implemented (Rx signal strength readout)
2014.09.24 - - trb3_periph_hub_20140924.bit
2013.10.21 - - trb3_periph_hub_20131021.bit

Padiwa

Date Version Other1 Other2 Bitfile Comment
2013.05.13 v1 - - padiwa_20130513_v1.jed
2013.07.15 v2 - - padiwa_20130715_v2_tempcorrection.jed First design with Temperature correction
2014.11.21 v3 - - padiwa_20141121_v3.jed including some more debugging features
2014.06.26 amps - - padiwa_amps_short_discharge.jed Short discharge
2014.02.06 amps - - padiwa_amps_20140206.jed Standard design
2018.11.08 amps2 - -

padiwa_amps2_20181108.jed

last fixes for discharge disable and LED

Trb3sc Pulser AddOn

Date Bitfile Comment
2015.08.06 trb3sc_pulser_20150806.bit All basic features for analog and digital pulses included. Stand-alone operation only.

Trb3sc Master

Date Bitfile Comment
2020-09-04 trb3sc_master_20200904.bit Master for backplane, with GbE, monitoring and trigger generation inputs on KEL and from backplane
2020-03-20 trb3sc_master_20200320.bit Master for backplane, with GbE, monitoring and trigger generation inputs on KEL and from backplane
2018-12-07 trb3sc_master_20181207.bit Master for backplane, with GbE (200 MHz oscillator)
2017.07.04 trb3sc_backplanemaster_20170704.bit Master for backplane, with GbE (240 MHz oscillator)
2018.02.02 trb3sc_master_20180322.bit Master for backplane, with GbE (200 MHz oscillator)

Trb3sc ADC AddOn

Date Bitfile Comment
2019.11.22 trb3sc_adc_sfp_20191122.bit ADC AddOn design, internal clock only, TrbNet via SFP, 200MHz oscillator
2016.06.13 trb3sc_adc_standalone_20160613.bit ADC AddOn design, internal clock only, TrbNet via SFP, 240MHz oscillator

Trb3sc SFP-AddOn

Date Bitfile Comment
trb3sc_hub_gbe_bkpl... Hub with GbE and uplink on backplane. 8 SFP downlinks
trb3sc_hub_gbe_nobkpl... Hub with GbE and uplink on SFP. 7 SFP downlinks
trb3sc_hub_nogbe_bkpl... Hub without GbE and uplink on backplane. 10 SFP downlinks
trb3sc_hub_nogbe_nobkpl... Hub without GbE and uplink on SFP. 9 SFP downlinks

Trb3sc TDC

Available configurations:

  • TDC version 2.4.0
  • Default with double edge measurement, stretcher and basic trigger generation logic
  • Input/AddOn: 32pin, ADA, 4conn or on-board KEL
  • 48 channels (if input permits), (up to 56 channels on special request)
  • Operation with SFP or in crate
  • Option: use every fourth input on ADA (compatibility to high resolution mode of HPTDC)
  • Option: additional 2 test signals on ADA-connectors (e.g. for HADES RPC)
  • Option: extended 28 channel trigger generation logic (up to 48 channels TDC)

Trb3sc CTS

Date Bitfile Description
2020-03-23 trb3sc_cts_8sfp_rjadapter... CTS with 8 SFP, 8 RJ-connections for trigger input and reference time output
2020-05-01 trb3sc_cts_32tdc... CTS with 32 TDC channels and 1 SFP link, 32 trigger inputs on KEL, 1 SFP
trb3sc_cts_master... CTS with 1 SFP and backplane connection, trigger inputs from backplane and RJ

Trb5sc TDC

Date Bitfile Description
2020-05-09 trb5sc_tdc_sfp... Normal TDC with 32 channels, usable with all AddOns, stand-alone use with SFP
2020-05-11 trb5sc_tdc_bkpl... Normal TDC with 32 channels, usable with all AddOns, use in crate

DreamPlug Designs