TRB Collaboration

Most endpoint designs need some configuration bits being programmed after the FPGA has been initialized. Usually these settings depend on the use of the design or specific hardware (e.g. thresholds) and can not be hard coded in the design itself. Now there is the option to store register settings in a separate section of the on-board Flash ROM - all user registers (addresses above 0x8000) can be stored there and can be loaded automatically after a reload of the FPGA design. This can be used e.g. to power cycle an FPGA without requiring interaction from some software and have it back in operation after about 1.5s (ECP3-150, using latest media interfaces) or within milliseconds like the Padwia-FPGA.

In general, this feature is available for all TRB3 and TRB3sc designs, but at the moment is implemented on special request only. One caveat to note: The registers configuration file needs to be prepared by hand and is not generated automatically.