TRB3 Documents
The main manual with information about Trb3, Modules, AddOns, Computer environment: TRB3 Manual
The manual of the Padiwa-Series of modules: Padiwa Manual
More information on how TrbNet is used in HADES and details on common registers: TrbNet Manual
Short summary of the features of the DAQ and Analysis Software
The central trigger system: Bachelor Thesis
Time Performance Measurements with the TRB3: Internship Report
DABC documentation: Weblink to DABC documentation for TRBs
TDC Calibration Procedure documentation: Weblink to DABC documentation for calibration of the FPGA-TDC data
CentOS VirtualBox Image to be able to program Lattice FPGAs via any computer (with VirtualBox): Image with Readme
Docker Container with the full software package (root, dabc, stream, go4, trbnettools, daqtools)
everything you need to run a TRB data acquisition system
Manual: README.txt
Git with Dockerfile and startup scripts: git clone git://jspc29.x-matter.uni-frankfurt.de/projects/dockerfiles.git
Mini datasheet of some basic features of the TRB3-platform
(what does TRB mean? You can chose between: TDC-Readout-Board, Triggered-Readout-Board and Triggerless-Readout-Board)
Item | Value |
---|---|
Supply Voltage | 48 V (40-50V), galvanically isolated on board |
Power Supply Current | 0.5A minimum without AddOns |
GbE-connectivity |
max. 95 MBytes/s transfer per link
|
GbE-slow-control | up to 400 registers/transfer, speed depends on GbE latency |
Connectivity | Max. 8 SFPs, each 2GBit/s on board. With hub-addon: max. 32 SFP |
4 AddONs on top (208 pin), 1 AddOn on bottom | |
Max Readout Trigger Rate | about 300 KHz (depending on configuration and network size) |
Max Hit Rate | 50 MHz (burst of 63 hits) |
TDC Channels | 260 (Single edge detection) |
Time Precision | <20 ps |
Minimum pulse width |
<500 ps
|