Tip of the week: Know your limits

The buffers in all FPGAs to store data are quite large to offer some flexibility, but in most applications it makes sense to constrain the maximum amount of data:

  • The ring buffers in each TDC channel can store up to 124 words - if these are filled by noise data it may generate more than 60 us of dead time for each trigger to scan the buffers for relevant data
  • The event buffer in each TDC can store a few thousand words in total, with a limit of typically 500 words per event ("MaxEventSize", register 0x7111)
  • The size of each sub-event (data sent over one Ethernet link) is limited to 60 kB or about 15,000 TDC words. This limit can be reached or exceeded quite easily.

The TDC and TrbNet offer two levels of data limiting:

  • The buffer in each TDC channel can be reduced ("DataLimit", TDC GUI, register 0xc804).
  • The amount of event data generated by an individual endpoint can be limited ("SetMaxEventSize",TrbNet -> Readout, register 0x7111). This should be adjusted such that data from all channels can be transported even if TDC buffers are full and at the same time, the maximum sub-event size can not be exceeded by all endpoints connected to the same Ethernet Link.

In setups with many front-ends and low hit occupancy it can be handy to discard data from all front-ends that didn't measure any hit - The overhead from TDC headers and reference time measurement sums up to quite large amounts. The endpoints can be configured to discard all events with less than a certain amount of data ("MinEventSize", TrbNet -> Readout, register 0x7114). Setting to 5 discards all data that just contains the reference time but no other hits.

RJ45 AddOn Board

This RJ45 AddOn board provides 12 standard network cable sockets allowing to transmit the LVDS signals via shielded cables (CAT 6, S/FTP). This reduces crosstalk and signal edge distortions on neighboring signal lines, especially for longer cables. This AddOn board uses the PADIWA 4-conn I/O schematics. The SPI lines are either available via the RJ45 sockets or on the a separate 2x10-pin connector. Furthermore, a 3.3V and 6V connection is available via a 2x2-pin connector.

Logic Box - Family Picture

Here's a family picture of all the boards in the Logicbox family. In the middle you can see the two main boards - either a plain power module or the full main board including an FPGA for any kind of signal measurement and manipulation.
To the left, two of the three input modules can be seen. In the top corner, the LEMO input module accepting NIM and TTL signals. In the bottom corner the LVDS/TTL input module with pin-headers. Not in the picture is the analog input module with two amplifiers and discriminators to convert signals from, e.g., photo-multipliers.
To the right, the two output modules are shown: The LEMO module with NIM or LVTTL outputs as well as the LVDS/TTL output module.

The second image is a close-up of the main board - the smallest FPGA module in the TRB family. It was already successfully used as 9-channel TDC with 500 ps binning - albeit limited in rates due to the slow connection to the PC via UART and USB.

Tip of the week: CTS settings

In case you want to store your CTS settings and load them automatically with the next DAQ startup, the CTS GUI has a handy export feature. It gives you all the settings of the CTS, including comments and speaking names of settings. You can just reference this settings file in your start-up script.

Tip of the week: Serial Numbers

The network map now shows additional information: Besides a (rough, not necessarily complete) list of features implemented in the design, it now shows the unique ID and endpoint ID for each board. For the most common boards, the corresponding serial number is retrieved from the serials.db file and shown as well. Designs including a GbE interface also show their MAC address (in case of single-link designs which are not older than about one year).